| commit | 0a38b227c802abbc0dbe966860d6e3521d5475ba | |
| author | Lee Leahy <leroy.p.leahy@intel.com> | |
| Sun, 24 Jul 2016 15:26:06 +0000 (24 08:26 -0700) | ||
| committer | Lee Leahy <leroy.p.leahy@intel.com> | |
| Wed, 3 Aug 2016 04:13:53 +0000 (3 06:13 +0200) | ||
| tree | 8b654a876bc351ee73337a8c5225b8b52b760ab0 | treesnapshot (tar.gz zip) |
| parent | cc5be8b72ba5b072030fdd1d382d7156da43114f | commitdiff |
drivers/intel/fsp2_0: Monitor FSP setting of MTRRs
Display the MTRR values in the following locations:
* Before the call to FspMemoryInit to document coreboot settings
* After the call to FspMemoryInit
* Before the call to FspSiliconInit
* After the call to FspSiliconInit
* After the call to FspNotify
* Before the call to FspNotify added in patch 15855
TEST=Build and run on Galileo Gen2
Change-Id: I8942ef4ca4677501a5c38abaff1c3489eebea53c
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15849
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Display the MTRR values in the following locations:
* Before the call to FspMemoryInit to document coreboot settings
* After the call to FspMemoryInit
* Before the call to FspSiliconInit
* After the call to FspSiliconInit
* After the call to FspNotify
* Before the call to FspNotify added in patch 15855
TEST=Build and run on Galileo Gen2
Change-Id: I8942ef4ca4677501a5c38abaff1c3489eebea53c
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15849
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
| src/drivers/intel/fsp2_0/debug.c | diffblobblamehistory |