| commit | 09f7303518c796d7633eb996dfa18ecb26fd6260 | |
| author | Felix Held <felix-coreboot@felixheld.de> | |
| Fri, 17 Dec 2021 00:50:05 +0000 (17 01:50 +0100) | ||
| committer | Felix Held <felix-coreboot@felixheld.de> | |
| Sat, 18 Dec 2021 02:06:28 +0000 (18 02:06 +0000) | ||
| tree | 28f8cbfe02ab517ea832dda4b3266ce9c198b564 | treesnapshot (tar.gz zip) |
| parent | f5dfe248ce30ff91a02430b925f3e4bd5dda955a | commitdiff |
soc/amd/common/block/acpimmio/print_reset_status: add missing status bit
Both the Picasso PPR #55570 Rev 3.18 and the Cezanne PPR #56569 Rev 3.03
define bit 9 of the PM_RST_STATUS register as internal Thermal Trip
reset status bit.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ida8b13fe62b16c18fc9924520b83220e73eca624
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Both the Picasso PPR #55570 Rev 3.18 and the Cezanne PPR #56569 Rev 3.03
define bit 9 of the PM_RST_STATUS register as internal Thermal Trip
reset status bit.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ida8b13fe62b16c18fc9924520b83220e73eca624
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
| src/soc/amd/common/block/acpimmio/print_reset_status.c | diffblobblamehistory |