| commit | 07ccc8d9cd52f484f75761d52b4efbb99029d473 | |
| author | Angel Pons <th3fanbus@gmail.com> | |
| Fri, 26 Mar 2021 18:07:49 +0000 (26 19:07 +0100) | ||
| committer | Angel Pons <th3fanbus@gmail.com> | |
| Fri, 2 Apr 2021 14:34:23 +0000 (2 14:34 +0000) | ||
| tree | 068d28f92a9b141072e81e25dc8fbf6bd9d83a79 | treesnapshot (tar.gz zip) |
| parent | b77f01642cd7332e258e1c2ef51c470b96466b4f | commitdiff |
nb/intel/pineview: Correct COMP register write
Reference code does an and-or operation with zero as or-value, reading
and writing to the same address. The accessed register is 32-bit, and
reference code programs bits 22, 21, 20, 16 to zero. However, coreboot
code reads the value from bits 7..0 instead. Correct this.
Change-Id: I33bf268449c2f799321be81a02bbccff855ee1fe
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51861
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reference code does an and-or operation with zero as or-value, reading
and writing to the same address. The accessed register is 32-bit, and
reference code programs bits 22, 21, 20, 16 to zero. However, coreboot
code reads the value from bits 7..0 instead. Correct this.
Change-Id: I33bf268449c2f799321be81a02bbccff855ee1fe
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51861
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| src/northbridge/intel/pineview/raminit.c | diffblobblamehistory |