| commit | 06cfb21e243ec74660e4886cef2f2e9c6c755d9e | |
| author | Roy Mingi Park <roy.mingi.park@intel.com> | |
| Mon, 3 Jun 2019 23:11:25 +0000 (3 16:11 -0700) | ||
| committer | Duncan Laurie <dlaurie@chromium.org> | |
| Tue, 4 Jun 2019 16:49:46 +0000 (4 16:49 +0000) | ||
| tree | 19ec89696683d0864e5df4952a57e22b9f705e4c | treesnapshot (tar.gz zip) |
| parent | 13539d2f9d671099764f12e45b8e6d4e41c8e4af | commitdiff |
mb/google/sarien: Fix SSD's power off sequence before going to S5
BUG=b:133389422
TEST=check SSD's power off sequence to meet PCIE requirement.
SSD's reset should be cleared before clearing SSD's power EN Pin.
Change-Id: Ia106b805deafb8a442b56bcce91b51135cb32988
Signed-off-by: Roy Mingi Park <roy.mingi.park@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33182
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
BUG=b:133389422
TEST=check SSD's power off sequence to meet PCIE requirement.
SSD's reset should be cleared before clearing SSD's power EN Pin.
Change-Id: Ia106b805deafb8a442b56bcce91b51135cb32988
Signed-off-by: Roy Mingi Park <roy.mingi.park@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33182
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl | diffblobblamehistory | |
| src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl | diffblobblamehistory |