| commit | 047835aba7e0dea609590797c6ce72c331f94536 | |
| author | Angel Pons <th3fanbus@gmail.com> | |
| Fri, 15 Oct 2021 13:39:32 +0000 (15 15:39 +0200) | ||
| committer | Felix Held <felix-coreboot@felixheld.de> | |
| Fri, 29 Oct 2021 15:00:55 +0000 (29 15:00 +0000) | ||
| tree | 48947ae075eaf43f356413bd2f2b747db8952038 | treesnapshot (tar.gz zip) |
| parent | 69dcc1e5154260359c516d85ab728a2094aa600b | commitdiff |
mb/prodrive/hermes: Map PCIe clocks to root ports
Map each PCIe clock source to the corresponding root port. Also, correct
the CLKREQ# mapping for clock sources not associated to any CLKREQ# pin.
The default `PcieClkSrcClkReq` value of 0 corresponds to CLKREQ# 0.
TEST=Check that Linux sees the same PCIe devices with this commit:
- All 5 onboard Ethernet NICs
- BMC
- Two random graphics cards in PEG0 and PEG1 slots
- M.2 M NVMe SSD
Change-Id: I0515877a36d42fb8858a0f0b3c0af1199a18d9af
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Map each PCIe clock source to the corresponding root port. Also, correct
the CLKREQ# mapping for clock sources not associated to any CLKREQ# pin.
The default `PcieClkSrcClkReq` value of 0 corresponds to CLKREQ# 0.
TEST=Check that Linux sees the same PCIe devices with this commit:
- All 5 onboard Ethernet NICs
- BMC
- Two random graphics cards in PEG0 and PEG1 slots
- M.2 M NVMe SSD
Change-Id: I0515877a36d42fb8858a0f0b3c0af1199a18d9af
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
| src/mainboard/prodrive/hermes/devicetree.cb | diffblobblamehistory |