| commit | 037ee4b5562099771795d52cf7149ddff8dd3595 | |
| author | Martin Roth <martin@coreboot.org> | |
| Wed, 8 Jul 2020 22:19:37 +0000 (8 16:19 -0600) | ||
| committer | Martin Roth <martinroth@google.com> | |
| Thu, 9 Jul 2020 00:26:05 +0000 (9 00:26 +0000) | ||
| tree | 995ae6ab809ee40482132a11acfc28091c804d92 | treesnapshot (tar.gz zip) |
| parent | 85dcd2f1ea2cc140f1bbd724d32db532d4908a44 | commitdiff |
soc/amd/picasso: Add dummy spinlock for psp_verstage
If CONFIG_CMOS_POST is enabled, psp_verstage breaks because the
spinlock code is missing. Add dummy spinlock code as the spinlocks
aren't needed in the PSP.
TEST=Build with CONFIG_CMOS_POST enabled.
BUG=None
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Iea6f31e500e1b26f0b974c6eaa486209b9c81459
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43310
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If CONFIG_CMOS_POST is enabled, psp_verstage breaks because the
spinlock code is missing. Add dummy spinlock code as the spinlocks
aren't needed in the PSP.
TEST=Build with CONFIG_CMOS_POST enabled.
BUG=None
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Iea6f31e500e1b26f0b974c6eaa486209b9c81459
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43310
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| src/soc/amd/picasso/psp_verstage/include/arch/smp/spinlock.h | [new file with mode: 0644] | blob |