src/southbridge/intel/i82801jx/smihandler.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008-2009 coresystems GmbH
   5  *               2012 secunet Security Networks AG
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; version 2 of
  10  * the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <types.h>
  19 #include <console/console.h>
  20 #include <cpu/x86/cache.h>
  21 #include <cpu/x86/smm.h>
  22 #include <device/pci_def.h>
  23 #include <southbridge/intel/common/pmutil.h>
  24 #include "i82801jx.h"
  25
  26 #include "nvs.h"
  27
  28 /* While we read PMBASE dynamically in case it changed, let's
  29  * initialize it with a sane value
  30  */
  31 u16 pmbase = DEFAULT_PMBASE;
  32 u8 smm_initialized = 0;
  33
  34 /* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located
  35  * by coreboot.
  36  */
  37 global_nvs_t *gnvs = (global_nvs_t *)0x0;
  38 void *tcg = (void *)0x0;
  39 void *smi1 = (void *)0x0;
  40
  41 int southbridge_io_trap_handler(int smif)
  42 {
  43         switch (smif) {
  44         case 0x32:
  45                 printk(BIOS_DEBUG, "OS Init\n");
  46                 /* gnvs->smif:
  47                  *  On success, the IO Trap Handler returns 0
  48                  *  On failure, the IO Trap Handler returns a value != 0
  49                  */
  50                 gnvs->smif = 0;
  51                 return 1; /* IO trap handled */
  52         }
  53
  54         /* Not handled */
  55         return 0;
  56 }
  57
  58 void southbridge_update_gnvs(u8 apm_cnt, int *smm_done)
  59 {
  60         gnvs = *(global_nvs_t **)0x500;
  61         tcg  = *(void **)0x504;
  62         smi1 = *(void **)0x508;
  63         *smm_done = 1;
  64 }
  65
  66 void southbridge_smi_monitor(void)
  67 {
  68 #define IOTRAP(x) (trap_sts & (1 << x))
  69         u32 trap_sts, trap_cycle;
  70         u32 data, mask = 0;
  71         int i;
  72
  73         trap_sts = RCBA32(0x1e00); // TRSR - Trap Status Register
  74         RCBA32(0x1e00) = trap_sts; // Clear trap(s) in TRSR
  75
  76         trap_cycle = RCBA32(0x1e10);
  77         for (i=16; i<20; i++) {
  78                 if (trap_cycle & (1 << i))
  79                         mask |= (0xff << ((i - 16) << 3));
  80         }
  81
  82
  83         /* IOTRAP(3) SMI function call */
  84         if (IOTRAP(3)) {
  85                 if (gnvs && gnvs->smif)
  86                         io_trap_handler(gnvs->smif); // call function smif
  87                 return;
  88         }
  89
  90         /* IOTRAP(2) currently unused
  91          * IOTRAP(1) currently unused */
  92
  93         /* IOTRAP(0) SMIC */
  94         if (IOTRAP(0)) {
  95                 if (!(trap_cycle & (1 << 24))) { // It's a write
  96                         printk(BIOS_DEBUG, "SMI1 command\n");
  97                         data = RCBA32(0x1e18);
  98                         data &= mask;
  99                         // if (smi1)
 100                         //      southbridge_smi_command(data);
 101                         // return;
 102                 }
 103                 // Fall through to debug
 104         }
 105
 106         printk(BIOS_DEBUG, "  trapped io address = 0x%x\n", trap_cycle & 0xfffc);
 107         for (i=0; i < 4; i++) if (IOTRAP(i)) printk(BIOS_DEBUG, "  TRAP = %d\n", i);
 108         printk(BIOS_DEBUG, "  AHBE = %x\n", (trap_cycle >> 16) & 0xf);
 109         printk(BIOS_DEBUG, "  MASK = 0x%08x\n", mask);
 110         printk(BIOS_DEBUG, "  read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write");
 111
 112         if (!(trap_cycle & (1 << 24))) {
 113                 /* Write Cycle */
 114                 data = RCBA32(0x1e18);
 115                 printk(BIOS_DEBUG, "  iotrap written data = 0x%08x\n", data);
 116         }
 117 #undef IOTRAP
 118 }
 119
 120 void southbridge_finalize_all(void)
 121 {
 122 }