2 * This file is part of the coreboot project.
4 * Copyright (C) 2010 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 /* DefinitionBlock Statement */
17 #include <arch/acpi.h>
19 "DSDT.AML", /* Output filename */
20 "DSDT", /* Signature */
21 0x02, /* DSDT Revision, needs to be 2 for 64bit */
24 0x00010001 /* OEM Revision */
26 { /* Start of ASL file */
27 /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */
29 /* Data to be patched by the BIOS during POST */
30 /* FIXME the patching is not done yet! */
31 /* Memory related values */
32 Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
33 Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
34 Name(PBLN, 0x0) /* Length of BIOS area */
36 Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
37 Name(HPBA, 0xFED00000) /* Base address of HPET table */
39 /* USB overcurrent mapping pins. */
51 /* Some global data */
52 Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
53 Name(OSV, Ones) /* Assume nothing */
54 Name(PMOD, One) /* Assume APIC */
60 Scope (\_PR) { /* define processor scope */
62 CPU0, /* name space name */
63 0, /* Unique number for this processor */
64 0x808, /* PBLK system I/O address !hardcoded! */
65 0x06 /* PBLKLEN for boot processor */
67 #include "acpi/cpstate.asl"
71 CPU1, /* name space name */
72 1, /* Unique number for this processor */
73 0x0000, /* PBLK system I/O address !hardcoded! */
74 0x00 /* PBLKLEN for boot processor */
76 #include "acpi/cpstate.asl"
80 CPU2, /* name space name */
81 2, /* Unique number for this processor */
82 0x0000, /* PBLK system I/O address !hardcoded! */
83 0x00 /* PBLKLEN for boot processor */
85 #include "acpi/cpstate.asl"
89 CPU3, /* name space name */
90 3, /* Unique number for this processor */
91 0x0000, /* PBLK system I/O address !hardcoded! */
92 0x00 /* PBLKLEN for boot processor */
94 #include "acpi/cpstate.asl"
98 /* PIC IRQ mapping registers, C00h-C01h */
99 OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
100 Field(PRQM, ByteAcc, NoLock, Preserve) {
102 PRQD, 0x00000008, /* Offset: 1h */
104 IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
105 PINA, 0x00000008, /* Index 0 */
106 PINB, 0x00000008, /* Index 1 */
107 PINC, 0x00000008, /* Index 2 */
108 PIND, 0x00000008, /* Index 3 */
109 AINT, 0x00000008, /* Index 4 */
110 SINT, 0x00000008, /* Index 5 */
111 , 0x00000008, /* Index 6 */
112 AAUD, 0x00000008, /* Index 7 */
113 AMOD, 0x00000008, /* Index 8 */
114 PINE, 0x00000008, /* Index 9 */
115 PINF, 0x00000008, /* Index A */
116 PING, 0x00000008, /* Index B */
117 PINH, 0x00000008, /* Index C */
120 /* PCI Error control register */
121 OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
122 Field(PERC, ByteAcc, NoLock, Preserve) {
129 /* Client Management index/data registers */
130 OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
131 Field(CMT, ByteAcc, NoLock, Preserve) {
133 /* Client Management Data register */
141 /* GPM Port register */
142 OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
143 Field(GPT, ByteAcc, NoLock, Preserve) {
154 /* Flash ROM program enable register */
155 OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
156 Field(FRE, ByteAcc, NoLock, Preserve) {
161 /* PM2 index/data registers */
162 OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
163 Field(PM2R, ByteAcc, NoLock, Preserve) {
168 /* Power Management I/O registers */
169 OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
170 Field(PIOR, ByteAcc, NoLock, Preserve) {
174 IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
175 Offset(0x00), /* MiscControl */
179 Offset(0x01), /* MiscStatus */
183 Offset(0x04), /* SmiWakeUpEventEnable3 */
186 Offset(0x07), /* SmiWakeUpEventStatus3 */
189 Offset(0x10), /* AcpiEnable */
192 Offset(0x1C), /* ProgramIoEnable */
199 Offset(0x1D), /* IOMonitorStatus */
206 Offset(0x20), /* AcpiPmEvtBlk */
208 Offset(0x36), /* GEvtLevelConfig */
212 Offset(0x37), /* GPMLevelConfig0 */
219 Offset(0x38), /* GPMLevelConfig1 */
226 Offset(0x3B), /* PMEStatus1 */
235 Offset(0x55), /* SoftPciRst */
243 /* Offset(0x61), */ /* Options_1 */
247 Offset(0x65), /* UsbPMControl */
250 Offset(0x68), /* MiscEnable68 */
254 Offset(0x92), /* GEVENTIN */
257 Offset(0x96), /* GPM98IN */
260 Offset(0x9A), /* EnhanceControl */
263 Offset(0xA8), /* PIO7654Enable */
268 Offset(0xA9), /* PIO7654Status */
276 * First word is PM1_Status, Second word is PM1_Enable
278 OperationRegion(P1EB, SystemIO, APEB, 0x04)
279 Field(P1EB, ByteAcc, NoLock, Preserve) {
304 /* PCIe Configuration Space for 16 busses */
305 OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */
306 Field(PCFG, ByteAcc, NoLock, Preserve) {
307 /* Byte offsets are computed using the following technique:
308 * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
309 * The 8 comes from 8 functions per device, and 4096 bytes per function config space
311 Offset(0x00090024), /* Byte offset to SATA register 24h - Bus 0, Device 18, Function 0 */
313 Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
324 Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */
327 Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */
329 Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */
331 Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */
333 P92E, 1, /* Port92 decode enable */
336 OperationRegion(SB5, SystemMemory, STB5, 0x1000)
337 Field(SB5, AnyAcc, NoLock, Preserve){
339 Offset(0x120), /* Port 0 Task file status */
345 Offset(0x128), /* Port 0 Serial ATA status */
349 Offset(0x12C), /* Port 0 Serial ATA control */
351 Offset(0x130), /* Port 0 Serial ATA error */
356 offset(0x1A0), /* Port 1 Task file status */
362 Offset(0x1A8), /* Port 1 Serial ATA status */
366 Offset(0x1AC), /* Port 1 Serial ATA control */
368 Offset(0x1B0), /* Port 1 Serial ATA error */
373 Offset(0x220), /* Port 2 Task file status */
379 Offset(0x228), /* Port 2 Serial ATA status */
383 Offset(0x22C), /* Port 2 Serial ATA control */
385 Offset(0x230), /* Port 2 Serial ATA error */
390 Offset(0x2A0), /* Port 3 Task file status */
396 Offset(0x2A8), /* Port 3 Serial ATA status */
400 Offset(0x2AC), /* Port 3 Serial ATA control */
402 Offset(0x2B0), /* Port 3 Serial ATA error */
409 #include "acpi/routing.asl"
415 if(LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */
419 Store(1, OSVR) /* Assume some form of XP */
420 if (\_OSI("Windows 2006")) /* Vista */
425 If(WCMP(\_OS,"Linux")) {
426 Store(3, OSVR) /* Linux */
428 Store(4, OSVR) /* Gotta be WinCE */
434 Method(_PIC, 0x01, NotSerialized)
442 Method(CIRQ, 0x00, NotSerialized){
453 Name(IRQB, ResourceTemplate(){
454 IRQ(Level,ActiveLow,Shared){15}
457 Name(IRQP, ResourceTemplate(){
458 IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15}
461 Name(PITF, ResourceTemplate(){
462 IRQ(Level,ActiveLow,Exclusive){9}
466 Name(_HID, EISAID("PNP0C0F"))
471 Return(0x0B) /* sata is invisible */
473 Return(0x09) /* sata is disabled */
475 } /* End Method(_SB.INTA._STA) */
478 /* DBGO("\\_SB\\LNKA\\_DIS\n") */
480 } /* End Method(_SB.INTA._DIS) */
483 /* DBGO("\\_SB\\LNKA\\_PRS\n") */
485 } /* Method(_SB.INTA._PRS) */
488 /* DBGO("\\_SB\\LNKA\\_CRS\n") */
489 CreateWordField(IRQB, 0x1, IRQN)
490 ShiftLeft(1, PINA, IRQN)
492 } /* Method(_SB.INTA._CRS) */
495 /* DBGO("\\_SB\\LNKA\\_CRS\n") */
496 CreateWordField(ARG0, 1, IRQM)
498 /* Use lowest available IRQ */
499 FindSetRightBit(IRQM, Local0)
504 } /* End Method(_SB.INTA._SRS) */
505 } /* End Device(INTA) */
508 Name(_HID, EISAID("PNP0C0F"))
513 Return(0x0B) /* sata is invisible */
515 Return(0x09) /* sata is disabled */
517 } /* End Method(_SB.INTB._STA) */
520 /* DBGO("\\_SB\\LNKB\\_DIS\n") */
522 } /* End Method(_SB.INTB._DIS) */
525 /* DBGO("\\_SB\\LNKB\\_PRS\n") */
527 } /* Method(_SB.INTB._PRS) */
530 /* DBGO("\\_SB\\LNKB\\_CRS\n") */
531 CreateWordField(IRQB, 0x1, IRQN)
532 ShiftLeft(1, PINB, IRQN)
534 } /* Method(_SB.INTB._CRS) */
537 /* DBGO("\\_SB\\LNKB\\_CRS\n") */
538 CreateWordField(ARG0, 1, IRQM)
540 /* Use lowest available IRQ */
541 FindSetRightBit(IRQM, Local0)
546 } /* End Method(_SB.INTB._SRS) */
547 } /* End Device(INTB) */
550 Name(_HID, EISAID("PNP0C0F"))
555 Return(0x0B) /* sata is invisible */
557 Return(0x09) /* sata is disabled */
559 } /* End Method(_SB.INTC._STA) */
562 /* DBGO("\\_SB\\LNKC\\_DIS\n") */
564 } /* End Method(_SB.INTC._DIS) */
567 /* DBGO("\\_SB\\LNKC\\_PRS\n") */
569 } /* Method(_SB.INTC._PRS) */
572 /* DBGO("\\_SB\\LNKC\\_CRS\n") */
573 CreateWordField(IRQB, 0x1, IRQN)
574 ShiftLeft(1, PINC, IRQN)
576 } /* Method(_SB.INTC._CRS) */
579 /* DBGO("\\_SB\\LNKC\\_CRS\n") */
580 CreateWordField(ARG0, 1, IRQM)
582 /* Use lowest available IRQ */
583 FindSetRightBit(IRQM, Local0)
588 } /* End Method(_SB.INTC._SRS) */
589 } /* End Device(INTC) */
592 Name(_HID, EISAID("PNP0C0F"))
597 Return(0x0B) /* sata is invisible */
599 Return(0x09) /* sata is disabled */
601 } /* End Method(_SB.INTD._STA) */
604 /* DBGO("\\_SB\\LNKD\\_DIS\n") */
606 } /* End Method(_SB.INTD._DIS) */
609 /* DBGO("\\_SB\\LNKD\\_PRS\n") */
611 } /* Method(_SB.INTD._PRS) */
614 /* DBGO("\\_SB\\LNKD\\_CRS\n") */
615 CreateWordField(IRQB, 0x1, IRQN)
616 ShiftLeft(1, PIND, IRQN)
618 } /* Method(_SB.INTD._CRS) */
621 /* DBGO("\\_SB\\LNKD\\_CRS\n") */
622 CreateWordField(ARG0, 1, IRQM)
624 /* Use lowest available IRQ */
625 FindSetRightBit(IRQM, Local0)
630 } /* End Method(_SB.INTD._SRS) */
631 } /* End Device(INTD) */
634 Name(_HID, EISAID("PNP0C0F"))
639 Return(0x0B) /* sata is invisible */
641 Return(0x09) /* sata is disabled */
643 } /* End Method(_SB.INTE._STA) */
646 /* DBGO("\\_SB\\LNKE\\_DIS\n") */
648 } /* End Method(_SB.INTE._DIS) */
651 /* DBGO("\\_SB\\LNKE\\_PRS\n") */
653 } /* Method(_SB.INTE._PRS) */
656 /* DBGO("\\_SB\\LNKE\\_CRS\n") */
657 CreateWordField(IRQB, 0x1, IRQN)
658 ShiftLeft(1, PINE, IRQN)
660 } /* Method(_SB.INTE._CRS) */
663 /* DBGO("\\_SB\\LNKE\\_CRS\n") */
664 CreateWordField(ARG0, 1, IRQM)
666 /* Use lowest available IRQ */
667 FindSetRightBit(IRQM, Local0)
672 } /* End Method(_SB.INTE._SRS) */
673 } /* End Device(INTE) */
676 Name(_HID, EISAID("PNP0C0F"))
681 Return(0x0B) /* sata is invisible */
683 Return(0x09) /* sata is disabled */
685 } /* End Method(_SB.INTF._STA) */
688 /* DBGO("\\_SB\\LNKF\\_DIS\n") */
690 } /* End Method(_SB.INTF._DIS) */
693 /* DBGO("\\_SB\\LNKF\\_PRS\n") */
695 } /* Method(_SB.INTF._PRS) */
698 /* DBGO("\\_SB\\LNKF\\_CRS\n") */
699 CreateWordField(IRQB, 0x1, IRQN)
700 ShiftLeft(1, PINF, IRQN)
702 } /* Method(_SB.INTF._CRS) */
705 /* DBGO("\\_SB\\LNKF\\_CRS\n") */
706 CreateWordField(ARG0, 1, IRQM)
708 /* Use lowest available IRQ */
709 FindSetRightBit(IRQM, Local0)
714 } /* End Method(_SB.INTF._SRS) */
715 } /* End Device(INTF) */
718 Name(_HID, EISAID("PNP0C0F"))
723 Return(0x0B) /* sata is invisible */
725 Return(0x09) /* sata is disabled */
727 } /* End Method(_SB.INTG._STA) */
730 /* DBGO("\\_SB\\LNKG\\_DIS\n") */
732 } /* End Method(_SB.INTG._DIS) */
735 /* DBGO("\\_SB\\LNKG\\_PRS\n") */
737 } /* Method(_SB.INTG._CRS) */
740 /* DBGO("\\_SB\\LNKG\\_CRS\n") */
741 CreateWordField(IRQB, 0x1, IRQN)
742 ShiftLeft(1, PING, IRQN)
744 } /* Method(_SB.INTG._CRS) */
747 /* DBGO("\\_SB\\LNKG\\_CRS\n") */
748 CreateWordField(ARG0, 1, IRQM)
750 /* Use lowest available IRQ */
751 FindSetRightBit(IRQM, Local0)
756 } /* End Method(_SB.INTG._SRS) */
757 } /* End Device(INTG) */
760 Name(_HID, EISAID("PNP0C0F"))
765 Return(0x0B) /* sata is invisible */
767 Return(0x09) /* sata is disabled */
769 } /* End Method(_SB.INTH._STA) */
772 /* DBGO("\\_SB\\LNKH\\_DIS\n") */
774 } /* End Method(_SB.INTH._DIS) */
777 /* DBGO("\\_SB\\LNKH\\_PRS\n") */
779 } /* Method(_SB.INTH._CRS) */
782 /* DBGO("\\_SB\\LNKH\\_CRS\n") */
783 CreateWordField(IRQB, 0x1, IRQN)
784 ShiftLeft(1, PINH, IRQN)
786 } /* Method(_SB.INTH._CRS) */
789 /* DBGO("\\_SB\\LNKH\\_CRS\n") */
790 CreateWordField(ARG0, 1, IRQM)
792 /* Use lowest available IRQ */
793 FindSetRightBit(IRQM, Local0)
798 } /* End Method(_SB.INTH._SRS) */
799 } /* End Device(INTH) */
801 } /* End Scope(_SB) */
803 #include <southbridge/amd/common/acpi/sleepstates.asl>
805 /* Wake status package */
806 Name(WKST,Package(){Zero, Zero})
809 * \_PTS - Prepare to Sleep method
812 * Arg0=The value of the sleeping state S1=1, S2=2, etc
817 * The _PTS control method is executed at the beginning of the sleep process
818 * for S1-S5. The sleeping value is passed to the _PTS control method. This
819 * control method may be executed a relatively long time before entering the
820 * sleep state and the OS may abort the operation without notification to
821 * the ACPI driver. This method cannot modify the configuration or power
822 * state of any device in the system.
825 /* DBGO("\\_PTS\n") */
826 /* DBGO("From S0 to S") */
830 /* Don't allow PCIRST# to reset USB */
835 /* Clear sleep SMI status flag and enable sleep SMI trap. */
839 /* On older chips, clear PciExpWakeDisEn */
840 /*if (LLessEqual(\_SB.SBRI, 0x13)) {
845 /* Clear wake status structure. */
846 Store(0, Index(WKST,0))
847 Store(0, Index(WKST,1))
848 \_SB.PCI0.SIOS (Arg0)
849 } /* End Method(\_PTS) */
852 * The following method results in a "not a valid reserved NameSeg"
853 * warning so I have commented it out for the duration. It isn't
854 * used, so it could be removed.
857 * \_GTS OEM Going To Sleep method
860 * Arg0=The value of the sleeping state S1=1, S2=2
867 * DBGO("From S0 to S")
874 * \_BFS OEM Back From Sleep method
877 * Arg0=The value of the sleeping state S1=1, S2=2
883 /* DBGO("\\_BFS\n") */
886 /* DBGO(" to S0\n") */
890 * \_WAK System Wake method
893 * Arg0=The value of the sleeping state S1=1, S2=2
896 * Return package of 2 DWords
898 * 0x00000000 wake succeeded
899 * 0x00000001 Wake was signaled but failed due to lack of power
900 * 0x00000002 Wake was signaled but failed due to thermal condition
901 * Dword 2 - Power Supply state
902 * if non-zero the effective S-state the power supply entered
905 /* DBGO("\\_WAK\n") */
908 /* DBGO(" to S0\n") */
913 /* Restore PCIRST# so it resets USB */
918 /* Arbitrarily clear PciExpWakeStatus */
922 /* if (DeRefOf(Index(WKST,0))) {
923 * Store(0, Index(WKST,1))
925 * Store(Arg0, Index(WKST,1))
930 } /* End Method(\_WAK) */
932 Scope(\_GPE) { /* Start Scope GPE */
933 /* General event 0 */
935 * DBGO("\\_GPE\\_L00\n")
939 /* General event 1 */
941 * DBGO("\\_GPE\\_L00\n")
945 /* General event 2 */
947 * DBGO("\\_GPE\\_L00\n")
951 /* General event 3 */
953 /* DBGO("\\_GPE\\_L00\n") */
954 Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
957 /* General event 4 */
959 * DBGO("\\_GPE\\_L00\n")
963 /* General event 5 */
965 * DBGO("\\_GPE\\_L00\n")
969 /* General event 6 - Used for GPM6, moved to USB.asl */
971 * DBGO("\\_GPE\\_L00\n")
975 /* General event 7 - Used for GPM7, moved to USB.asl */
977 * DBGO("\\_GPE\\_L07\n")
981 /* Legacy PM event */
983 /* DBGO("\\_GPE\\_L08\n") */
986 /* Temp warning (TWarn) event */
988 /* DBGO("\\_GPE\\_L09\n") */
989 Notify (\_TZ.TZ00, 0x80)
994 * DBGO("\\_GPE\\_L0A\n")
998 /* USB controller PME# */
1000 /* DBGO("\\_GPE\\_L0B\n") */
1001 Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
1002 Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
1003 Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
1004 Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
1005 Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
1006 Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
1007 Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
1010 /* AC97 controller PME# */
1012 * DBGO("\\_GPE\\_L0C\n")
1016 /* OtherTherm PME# */
1018 * DBGO("\\_GPE\\_L0D\n")
1022 /* GPM9 SCI event - Moved to USB.asl */
1024 * DBGO("\\_GPE\\_L0E\n")
1028 /* PCIe HotPlug event */
1030 * DBGO("\\_GPE\\_L0F\n")
1034 /* ExtEvent0 SCI event */
1036 /* DBGO("\\_GPE\\_L10\n") */
1040 /* ExtEvent1 SCI event */
1042 /* DBGO("\\_GPE\\_L11\n") */
1045 /* PCIe PME# event */
1047 * DBGO("\\_GPE\\_L12\n")
1051 /* GPM0 SCI event - Moved to USB.asl */
1053 * DBGO("\\_GPE\\_L13\n")
1057 /* GPM1 SCI event - Moved to USB.asl */
1059 * DBGO("\\_GPE\\_L14\n")
1063 /* GPM2 SCI event - Moved to USB.asl */
1065 * DBGO("\\_GPE\\_L15\n")
1069 /* GPM3 SCI event - Moved to USB.asl */
1071 * DBGO("\\_GPE\\_L16\n")
1075 /* GPM8 SCI event - Moved to USB.asl */
1077 * DBGO("\\_GPE\\_L17\n")
1081 /* GPIO0 or GEvent8 event */
1083 /* DBGO("\\_GPE\\_L18\n") */
1084 Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */
1085 Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
1086 Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
1087 Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
1088 Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
1089 Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
1092 /* GPM4 SCI event - Moved to USB.asl */
1094 * DBGO("\\_GPE\\_L19\n")
1098 /* GPM5 SCI event - Moved to USB.asl */
1100 * DBGO("\\_GPE\\_L1A\n")
1104 /* Azalia SCI event */
1106 /* DBGO("\\_GPE\\_L1B\n") */
1107 Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
1108 Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
1111 /* GPM6 SCI event - Reassigned to _L06 */
1113 * DBGO("\\_GPE\\_L1C\n")
1117 /* GPM7 SCI event - Reassigned to _L07 */
1119 * DBGO("\\_GPE\\_L1D\n")
1123 /* GPIO2 or GPIO66 SCI event */
1125 * DBGO("\\_GPE\\_L1E\n")
1129 /* SATA SCI event - Moved to sata.asl */
1131 * DBGO("\\_GPE\\_L1F\n")
1135 } /* End Scope GPE */
1137 #include "acpi/usb.asl"
1140 Scope(\_SB) { /* Start \_SB scope */
1141 #include <arch/x86/acpi/globutil.asl> /* global utility methods expected within the \_SB scope */
1144 /* Note: Only need HID on Primary Bus */
1147 External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */
1148 Name(_HID, EISAID("PNP0A03"))
1149 Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
1150 Method(_BBN, 0) { /* Bus number = 0 */
1154 /* DBGO("\\_SB\\PCI0\\_STA\n") */
1155 Return(0x0B) /* Status is visible */
1159 If(PMOD){ Return(APR0) } /* APIC mode */
1160 Return (PR0) /* PIC Mode */
1163 /* Describe the Northbridge devices */
1165 Name(_ADR, 0x00000000)
1168 /* The internal GFX bridge */
1170 Name(_ADR, 0x00010000)
1171 Name(_PRW, Package() {0x18, 4})
1177 /* The external GFX bridge */
1179 Name(_ADR, 0x00020000)
1180 Name(_PRW, Package() {0x18, 4})
1182 If(PMOD){ Return(APS2) } /* APIC mode */
1183 Return (PS2) /* PIC Mode */
1187 /* Dev3 is also an external GFX bridge, not used in Herring */
1190 Name(_ADR, 0x00040000)
1191 Name(_PRW, Package() {0x18, 4})
1193 If(PMOD){ Return(APS4) } /* APIC mode */
1194 Return (PS4) /* PIC Mode */
1199 Name(_ADR, 0x00050000)
1200 Name(_PRW, Package() {0x18, 4})
1202 If(PMOD){ Return(APS5) } /* APIC mode */
1203 Return (PS5) /* PIC Mode */
1208 Name(_ADR, 0x00060000)
1209 Name(_PRW, Package() {0x18, 4})
1211 If(PMOD){ Return(APS6) } /* APIC mode */
1212 Return (PS6) /* PIC Mode */
1216 /* The onboard EtherNet chip */
1218 Name(_ADR, 0x00070000)
1219 Name(_PRW, Package() {0x18, 4})
1221 If(PMOD){ Return(APS7) } /* APIC mode */
1222 Return (PS7) /* PIC Mode */
1228 Name(_ADR, 0x00090000)
1229 Name(_PRW, Package() {0x18, 4})
1231 If(PMOD){ Return(APS9) } /* APIC mode */
1232 Return (PS9) /* PIC Mode */
1237 Name(_ADR, 0x000A0000)
1238 Name(_PRW, Package() {0x18, 4})
1240 If(PMOD){ Return(APSa) } /* APIC mode */
1241 Return (PSa) /* PIC Mode */
1246 /* PCI slot 1, 2, 3 */
1248 Name(_ADR, 0x00140004)
1249 Name(_PRW, Package() {0x18, 4})
1256 /* Describe the Southbridge devices */
1258 Name(_ADR, 0x00110000)
1259 #include "acpi/sata.asl"
1263 Name(_ADR, 0x00130000)
1264 Name(_PRW, Package() {0x0B, 3})
1268 Name(_ADR, 0x00130001)
1269 Name(_PRW, Package() {0x0B, 3})
1273 Name(_ADR, 0x00130002)
1274 Name(_PRW, Package() {0x0B, 3})
1278 Name(_ADR, 0x00130003)
1279 Name(_PRW, Package() {0x0B, 3})
1283 Name(_ADR, 0x00130004)
1284 Name(_PRW, Package() {0x0B, 3})
1288 Name(_ADR, 0x00130005)
1289 Name(_PRW, Package() {0x0B, 3})
1293 Name(_ADR, 0x00140000)
1296 /* Primary (and only) IDE channel */
1298 Name(_ADR, 0x00140001)
1299 #include "acpi/ide.asl"
1303 Name(_ADR, 0x00140002)
1304 OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
1305 Field(AZPD, AnyAcc, NoLock, Preserve) {
1329 If(LEqual(OSVR,3)){ /* If we are running Linux */
1338 Name(_ADR, 0x00140003)
1340 * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
1341 } */ /* End Method(_SB.SBRDG._INI) */
1343 /* Real Time Clock Device */
1345 Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */
1346 Name(_CRS, ResourceTemplate() {
1348 IO(Decode16,0x0070, 0x0070, 0, 2)
1349 /* IO(Decode16,0x0070, 0x0070, 0, 4) */
1351 } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
1353 Device(TMR) { /* Timer */
1354 Name(_HID,EISAID("PNP0100")) /* System Timer */
1355 Name(_CRS, ResourceTemplate() {
1357 IO(Decode16, 0x0040, 0x0040, 0, 4)
1358 /* IO(Decode16, 0x0048, 0x0048, 0, 4) */
1360 } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
1362 Device(SPKR) { /* Speaker */
1363 Name(_HID,EISAID("PNP0800")) /* AT style speaker */
1364 Name(_CRS, ResourceTemplate() {
1365 IO(Decode16, 0x0061, 0x0061, 0, 1)
1367 } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
1370 Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */
1371 Name(_CRS, ResourceTemplate() {
1373 IO(Decode16,0x0020, 0x0020, 0, 2)
1374 IO(Decode16,0x00A0, 0x00A0, 0, 2)
1375 /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
1376 /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
1378 } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
1380 Device(MAD) { /* 8257 DMA */
1381 Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */
1382 Name(_CRS, ResourceTemplate() {
1383 DMA(Compatibility,BusMaster,Transfer8){4}
1384 IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
1385 IO(Decode16, 0x0081, 0x0081, 0x01, 0x03)
1386 IO(Decode16, 0x0087, 0x0087, 0x01, 0x01)
1387 IO(Decode16, 0x0089, 0x0089, 0x01, 0x03)
1388 IO(Decode16, 0x008F, 0x008F, 0x01, 0x01)
1389 IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
1390 }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
1391 } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
1394 Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */
1395 Name(_CRS, ResourceTemplate() {
1396 IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
1399 } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
1402 Name(_HID,EISAID("PNP0103"))
1403 Name(CRS,ResourceTemplate() {
1404 Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */
1407 Return(0x0F) /* sata is visible */
1410 CreateDwordField(CRS, ^HPT._BAS, HPBX)
1414 } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
1418 Name(_ADR, 0x00140004)
1419 } /* end HostPciBr */
1422 Name(_ADR, 0x00140005)
1423 } /* end Ac97audio */
1426 Name(_ADR, 0x00140006)
1427 } /* end Ac97modem */
1429 /* ITE8718 Support */
1430 OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */
1431 Field (IOID, ByteAcc, NoLock, Preserve)
1433 SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */
1436 IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve)
1439 LDN, 8, /* Logical Device Number */
1441 CID1, 8, /* Chip ID Byte 1, 0x87 */
1442 CID2, 8, /* Chip ID Byte 2, 0x12 */
1444 ACTR, 8, /* Function activate */
1446 APC0, 8, /* APC/PME Event Enable Register */
1447 APC1, 8, /* APC/PME Status Register */
1448 APC2, 8, /* APC/PME Control Register 1 */
1449 APC3, 8, /* Environment Controller Special Configuration Register */
1450 APC4, 8 /* APC/PME Control Register 2 */
1453 /* Enter the 8718 MB PnP Mode */
1459 Store(0x55, SIOI) /* 8718 magic number */
1461 /* Exit the 8718 MB PnP Mode */
1468 * Keyboard PME is routed to SB700 Gevent3. We can wake
1469 * up the system by pressing the key.
1473 /* We only enable KBD PME for S5. */
1474 If (LLess (Arg0, 0x05))
1477 /* DBGO("8718F\n") */
1480 Store (One, ACTR) /* Enable EC */
1484 */ /* falling edge. which mode? Not sure. */
1487 Store (0x08, APC1) /* clear PME status, Use 0x18 for mouse & KBD */
1489 Store (0x08, APC0) /* enable PME, Use 0x18 for mouse & KBD */
1498 Store (Zero, APC0) /* disable keyboard PME */
1500 Store (0xFF, APC1) /* clear keyboard PME status */
1504 Name(CRES, ResourceTemplate() {
1505 IO(Decode16, 0x0CF8, 0x0CF8, 1, 8)
1507 WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
1508 0x0000, /* address granularity */
1509 0x0000, /* range minimum */
1510 0x0CF7, /* range maximum */
1511 0x0000, /* translation */
1515 WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
1516 0x0000, /* address granularity */
1517 0x0D00, /* range minimum */
1518 0xFFFF, /* range maximum */
1519 0x0000, /* translation */
1523 Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
1524 Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
1525 Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */
1526 Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */
1528 /* DRAM Memory from 1MB to TopMem */
1529 Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem */
1531 /* BIOS space just below 4GB */
1533 ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
1534 0x00, /* Granularity */
1535 0x00000000, /* Min */
1536 0x00000000, /* Max */
1537 0x00000000, /* Translation */
1538 0x00000001, /* Max-Min, RLEN */
1543 /* DRAM memory from 4GB to TopMem2 */
1544 QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
1545 0x00000000, /* Granularity */
1546 0x00000000, /* Min */
1547 0x00000000, /* Max */
1548 0x00000000, /* Translation */
1549 0x00000001, /* Max-Min, RLEN */
1554 /* BIOS space just below 16EB */
1555 QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
1556 0x00000000, /* Granularity */
1557 0x00000000, /* Min */
1558 0x00000000, /* Max */
1559 0x00000000, /* Translation */
1560 0x00000001, /* Max-Min, RLEN */
1565 }) /* End Name(_SB.PCI0.CRES) */
1568 /* DBGO("\\_SB\\PCI0\\_CRS\n") */
1570 CreateDWordField(CRES, ^EMM1._BAS, EM1B)
1571 CreateDWordField(CRES, ^EMM1._LEN, EM1L)
1572 CreateDWordField(CRES, ^DMLO._BAS, DMLB)
1573 CreateDWordField(CRES, ^DMLO._LEN, DMLL)
1574 CreateDWordField(CRES, ^PCBM._MIN, PBMB)
1575 CreateDWordField(CRES, ^PCBM._LEN, PBML)
1577 CreateQWordField(CRES, ^DMHI._MIN, DMHB)
1578 CreateQWordField(CRES, ^DMHI._LEN, DMHL)
1579 CreateQWordField(CRES, ^PEBM._MIN, EBMB)
1580 CreateQWordField(CRES, ^PEBM._LEN, EBML)
1582 If(LGreater(LOMH, 0xC0000)){
1583 Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */
1584 Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */
1587 /* Set size of memory from 1MB to TopMem */
1588 Subtract(TOM1, 0x100000, DMLL)
1591 * If(LNotEqual(TOM2, 0x00000000)){
1592 * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2
1593 * ShiftLeft(TOM2, 20, Local0)
1594 * Subtract(Local0, 0x100000000, DMHL)
1598 /* If there is no memory above 4GB, put the BIOS just below 4GB */
1599 If(LEqual(TOM2, 0x00000000)){
1600 Store(PBAD,PBMB) /* Reserve the "BIOS" space */
1603 Else { /* Otherwise, put the BIOS just below 16EB */
1604 ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */
1608 Return(CRES) /* note to change the Name buffer */
1609 } /* end of Method(_SB.PCI0._CRS) */
1613 * FIRST METHOD CALLED UPON BOOT
1615 * 1. If debugging, print current OS and ACPI interpreter.
1616 * 2. Get PCI Interrupt routing from ACPI VSM, this
1617 * value is based on user choice in BIOS setup.
1620 /* DBGO("\\_SB\\_INI\n") */
1621 /* DBGO(" DSDT.ASL code from ") */
1622 /* DBGO(__DATE__) */
1624 /* DBGO(__TIME__) */
1625 /* DBGO("\n Sleep states supported: ") */
1627 /* DBGO(" \\_OS=") */
1629 /* DBGO("\n \\_REV=") */
1633 /* Determine the OS we're running on */
1636 /* On older chips, clear PciExpWakeDisEn */
1637 /*if (LLessEqual(\SBRI, 0x13)) {
1641 } /* End Method(_SB._INI) */
1642 } /* End Device(PCI0) */
1644 Device(PWRB) { /* Start Power button device */
1645 Name(_HID, EISAID("PNP0C0C"))
1647 Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */
1648 Name(_STA, 0x0B) /* sata is invisible */
1650 } /* End \_SB scope */
1654 /* DBGO("\\_SI\\_SST\n") */
1655 /* DBGO(" New Indicator state: ") */
1659 } /* End Scope SI */
1661 #include <southbridge/amd/cimx/sb800/acpi/smbus.asl>
1670 Method(_AC0,0) { /* Active Cooling 0 (0=highest fan speed) */
1671 /* DBGO("\\_TZ\\TZ00\\_AC0\n") */
1672 Return(Add(0, 2730))
1674 Method(_AL0,0) { /* Returns package of cooling device to turn on */
1675 /* DBGO("\\_TZ\\TZ00\\_AL0\n") */
1676 Return(Package() {\_TZ.TZ00.FAN0})
1679 Name(_HID, EISAID("PNP0C0B"))
1680 Name(_PR0, Package() {PFN0})
1683 PowerResource(PFN0,0,0) {
1689 /* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */
1692 /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */
1696 Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */
1697 /* DBGO("\\_TZ\\TZ00\\_HOT\n") */
1698 Return (Add (THOT, KELV))
1700 Method(_CRT,0) { /* return critical temp in tenths degree Kelvin */
1701 /* DBGO("\\_TZ\\TZ00\\_CRT\n") */
1702 Return (Add (TCRT, KELV))
1704 Method(_TMP,0) { /* return current temp of this zone */
1705 Store (SMBR (0x07, 0x4C,, 0x00), Local0)
1706 If (LGreater (Local0, 0x10)) {
1707 Store (Local0, Local1)
1710 Add (Local0, THOT, Local0)
1711 Return (Add (400, KELV))
1714 Store (SMBR (0x07, 0x4C, 0x01), Local0)
1715 /* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */
1716 /* Store (SMBR (0x07, 0x4C, 0x10), Local2) */
1717 If (LGreater (Local0, 0x10)) {
1718 If (LGreater (Local0, Local1)) {
1719 Store (Local0, Local1)
1722 Multiply (Local1, 10, Local1)
1723 Return (Add (Local1, KELV))
1726 Add (Local0, THOT, Local0)
1727 Return (Add (400 , KELV))
1733 /* End of ASL file */