src/mainboard/amd/thatcher/dsdt.asl

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2012 Advanced Micro Devices, Inc.
   5  * Copyright (C) 2013 Sage Electronic Engineering, LLC
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 /* DefinitionBlock Statement */
  18 #include <arch/acpi.h>
  19 DefinitionBlock (
  20         "DSDT.AML",             /* Output filename */
  21         "DSDT",                 /* Signature */
  22         0x02,                   /* DSDT Revision, needs to be 2 for 64bit */
  23         OEM_ID,
  24         ACPI_TABLE_CREATOR,
  25         0x00010001              /* OEM Revision */
  26         )
  27 {       /* Start of ASL file */
  28         /* #include <arch/x86/acpi/debug.asl> */        /* Include global debug methods if needed */
  29
  30         /* Globals for the platform */
  31         #include "acpi/mainboard.asl"
  32
  33         /* Describe the USB Overcurrent pins */
  34         #include "acpi/usb_oc.asl"
  35
  36         /* PCI IRQ mapping for the Southbridge */
  37         #include <southbridge/amd/agesa/hudson/acpi/pcie.asl>
  38
  39         /* Describe the processor tree (\_PR) */
  40         #include <cpu/amd/agesa/family15tn/acpi/cpu.asl>
  41
  42         /* Describe the supported Sleep States for this Southbridge */
  43         #include <southbridge/amd/common/acpi/sleepstates.asl>
  44
  45         /* Describe the Sleep Methods (WAK, PTS, GTS, etc.) for this platform */
  46         #include "acpi/sleep.asl"
  47
  48         Scope(\_SB) {
  49                 /* global utility methods expected within the \_SB scope */
  50                 #include <arch/x86/acpi/globutil.asl>
  51
  52                 /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
  53                 #include "acpi/routing.asl"
  54
  55                 Device(PWRB) {
  56                         Name(_HID, EISAID("PNP0C0C"))
  57                         Name(_UID, 0xAA)
  58                         Name(_PRW, Package () {3, 0x04})
  59                         Name(_STA, 0x0B)
  60                 }
  61
  62                 Device(PCI0) {
  63                         /* Describe the AMD Northbridge */
  64                         #include <northbridge/amd/agesa/family15tn/acpi/northbridge.asl>
  65
  66                         /* Describe the AMD Fusion Controller Hub Southbridge */
  67                         #include <southbridge/amd/agesa/hudson/acpi/fch.asl>
  68
  69                 }
  70
  71                 /* Describe PCI INT[A-H] for the Southbridge */
  72                 #include <southbridge/amd/agesa/hudson/acpi/pci_int.asl>
  73
  74         }   /* End Scope(_SB)  */
  75
  76         /* Describe SMBUS for the Southbridge */
  77         #include <southbridge/amd/agesa/hudson/acpi/smbus.asl>
  78
  79         /* Define the General Purpose Events for the platform */
  80         #include "acpi/gpe.asl"
  81
  82         /* Define the Thermal zones and methods for the platform */
  83         #include "acpi/thermal.asl"
  84
  85         /* Define the System Indicators for the platform */
  86         #include "acpi/si.asl"
  87
  88 }
  89 /* End of ASL file */