2 * This file is part of the coreboot project.
4 * Copyright (C) 2013 Advanced Micro Devices, Inc.
5 * Copyright (C) 2013 Sage Electronic Engineering, LLC
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
18 #include <arch/acpi.h>
19 DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001
22 #include "routing.asl"
26 /* Routing is in System Bus scope */
29 /* Bus 0, Dev 0 - F16 Host Controller */
31 /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
32 /* Bus 0, Dev 1, Func 1 - HDMI Audio Controller */
33 Package(){0x0001FFFF, 0, INTB, 0 },
34 Package(){0x0001FFFF, 1, INTC, 0 },
37 /* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */
38 Package(){0x0002FFFF, 0, INTC, 0 },
39 Package(){0x0002FFFF, 1, INTD, 0 },
40 Package(){0x0002FFFF, 2, INTA, 0 },
41 Package(){0x0002FFFF, 3, INTB, 0 },
44 /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */
45 Package(){0x0014FFFF, 0, INTA, 0 },
46 Package(){0x0014FFFF, 1, INTB, 0 },
47 Package(){0x0014FFFF, 2, INTC, 0 },
48 Package(){0x0014FFFF, 3, INTD, 0 },
50 /* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */
51 /* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */
52 Package(){0x0012FFFF, 0, INTC, 0 },
53 Package(){0x0012FFFF, 1, INTB, 0 },
55 Package(){0x0013FFFF, 0, INTC, 0 },
56 Package(){0x0013FFFF, 1, INTB, 0 },
58 Package(){0x0016FFFF, 0, INTC, 0 },
59 Package(){0x0016FFFF, 1, INTB, 0 },
61 /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */
62 Package(){0x0010FFFF, 0, INTC, 0 },
63 Package(){0x0010FFFF, 1, INTB, 0 },
65 /* Bus 0, Dev 17 - SATA controller */
66 Package(){0x0011FFFF, 0, INTD, 0 },
71 /* NB devices in APIC mode */
72 /* Bus 0, Dev 0 - F15 Host Controller */
74 /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
75 Package(){0x0001FFFF, 0, 0, 44 },
76 Package(){0x0001FFFF, 1, 0, 45 },
78 /* Bus 0, Dev 2 - PCIe Bridges */
79 Package(){0x0002FFFF, 0, 0, 24 },
80 Package(){0x0002FFFF, 1, 0, 25 },
81 Package(){0x0002FFFF, 2, 0, 26 },
82 Package(){0x0002FFFF, 3, 0, 27 },
85 /* SB devices in APIC mode */
86 /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */
87 Package(){0x0014FFFF, 0, 0, 16 },
88 Package(){0x0014FFFF, 1, 0, 17 },
89 Package(){0x0014FFFF, 2, 0, 18 },
90 Package(){0x0014FFFF, 3, 0, 19 },
92 /* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */
93 /* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */
94 Package(){0x0012FFFF, 0, 0, 18 },
95 Package(){0x0012FFFF, 1, 0, 17 },
97 Package(){0x0013FFFF, 0, 0, 18 },
98 Package(){0x0013FFFF, 1, 0, 17 },
100 Package(){0x0016FFFF, 0, 0, 18 },
101 Package(){0x0016FFFF, 1, 0, 17 },
103 /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */
104 Package(){0x0010FFFF, 0, 0, 0x12},
105 Package(){0x0010FFFF, 1, 0, 0x11},
107 /* Bus 0, Dev 17 - SATA controller */
108 Package(){0x0011FFFF, 0, 0, 19 },
113 Package(){0x0000FFFF, 0, INTC, 0 },
114 Package(){0x0000FFFF, 1, INTD, 0 },
115 Package(){0x0000FFFF, 2, INTA, 0 },
116 Package(){0x0000FFFF, 3, INTB, 0 },
118 Name(APS2, Package(){
119 Package(){0x0000FFFF, 0, 0, 18 },
120 Package(){0x0000FFFF, 1, 0, 19 },
121 Package(){0x0000FFFF, 2, 0, 16 },
122 Package(){0x0000FFFF, 3, 0, 17 },
127 Package(){0x0000FFFF, 0, INTA, 0 },
128 Package(){0x0000FFFF, 1, INTB, 0 },
129 Package(){0x0000FFFF, 2, INTC, 0 },
130 Package(){0x0000FFFF, 3, INTD, 0 },
132 Name(APS4, Package(){
133 /* PCIe slot - Hooked to PCIe slot 4 */
134 Package(){0x0000FFFF, 0, 0, 24 },
135 Package(){0x0000FFFF, 1, 0, 25 },
136 Package(){0x0000FFFF, 2, 0, 26 },
137 Package(){0x0000FFFF, 3, 0, 27 },
142 Package(){0x0000FFFF, 0, INTB, 0 },
143 Package(){0x0000FFFF, 1, INTC, 0 },
144 Package(){0x0000FFFF, 2, INTD, 0 },
145 Package(){0x0000FFFF, 3, INTA, 0 },
147 Name(APS5, Package(){
148 Package(){0x0000FFFF, 0, 0, 28 },
149 Package(){0x0000FFFF, 1, 0, 29 },
150 Package(){0x0000FFFF, 2, 0, 30 },
151 Package(){0x0000FFFF, 3, 0, 31 },
156 Package(){0x0000FFFF, 0, INTC, 0 },
157 Package(){0x0000FFFF, 1, INTD, 0 },
158 Package(){0x0000FFFF, 2, INTA, 0 },
159 Package(){0x0000FFFF, 3, INTB, 0 },
161 Name(APS6, Package(){
162 Package(){0x0000FFFF, 0, 0, 32 },
163 Package(){0x0000FFFF, 1, 0, 33 },
164 Package(){0x0000FFFF, 2, 0, 34 },
165 Package(){0x0000FFFF, 3, 0, 35 },
170 Package(){0x0000FFFF, 0, INTD, 0 },
171 Package(){0x0000FFFF, 1, INTA, 0 },
172 Package(){0x0000FFFF, 2, INTB, 0 },
173 Package(){0x0000FFFF, 3, INTC, 0 },
175 Name(APS7, Package(){
176 Package(){0x0000FFFF, 0, 0, 36 },
177 Package(){0x0000FFFF, 1, 0, 37 },
178 Package(){0x0000FFFF, 2, 0, 38 },
179 Package(){0x0000FFFF, 3, 0, 39 },
184 Package(){0x0000FFFF, 0, INTA, 0 },
185 Package(){0x0000FFFF, 1, INTB, 0 },
186 Package(){0x0000FFFF, 2, INTC, 0 },
187 Package(){0x0000FFFF, 3, INTD, 0 },
189 Name(APS8, Package(){
190 Package(){0x0000FFFF, 0, 0, 40 },
191 Package(){0x0000FFFF, 1, 0, 41 },
192 Package(){0x0000FFFF, 2, 0, 42 },
193 Package(){0x0000FFFF, 3, 0, 43 },