2 * This file is part of the coreboot project.
4 * Copyright 2014 Rockchip Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <device/mmio.h>
18 #include <soc/addressmap.h>
19 #include <soc/clock.h>
23 static struct rockchip_vop_regs
* const vop_regs
[] = {
24 (struct rockchip_vop_regs
*)VOP_BIG_BASE
,
25 (struct rockchip_vop_regs
*)VOP_LIT_BASE
28 void rkvop_enable(u32 vop_id
, u32 fbbase
)
30 struct rockchip_vop_regs
*preg
= vop_regs
[vop_id
];
32 write32(&preg
->win0_yrgb_mst
, fbbase
);
34 /* On RK3288, the reg_cfg_done[1:31] is reserved and read-only,
35 * but it's fine to write to it
37 write32(&preg
->reg_cfg_done
, 0xffff); /* enable reg config */
40 void rkvop_prepare(u32 vop_id
, const struct edid
*edid
)
44 u32 hactive
= edid
->mode
.ha
;
45 u32 vactive
= edid
->mode
.va
;
46 u32 hsync_len
= edid
->mode
.hspw
;
47 u32 hback_porch
= edid
->mode
.hbl
- edid
->mode
.hso
- edid
->mode
.hspw
;
48 u32 vsync_len
= edid
->mode
.vspw
;
49 u32 vback_porch
= edid
->mode
.vbl
- edid
->mode
.vso
- edid
->mode
.vspw
;
50 u32 xpos
= 0, ypos
= 0;
51 struct rockchip_vop_regs
*preg
= vop_regs
[vop_id
];
53 write32(&preg
->win0_act_info
,
54 V_ACT_WIDTH(hactive
- 1) | V_ACT_HEIGHT(vactive
- 1));
56 write32(&preg
->win0_dsp_st
, V_DSP_XST(xpos
+ hsync_len
+ hback_porch
) |
57 V_DSP_YST(ypos
+ vsync_len
+ vback_porch
));
59 write32(&preg
->win0_dsp_info
, V_DSP_WIDTH(hactive
- 1) |
60 V_DSP_HEIGHT(vactive
- 1));
62 clrsetbits32(&preg
->win0_color_key
, M_WIN0_KEY_EN
| M_WIN0_KEY_COLOR
,
66 switch (edid
->framebuffer_bits_per_pixel
) {
69 write32(&preg
->win0_vir
, V_RGB565_VIRWIDTH(hactive
));
73 write32(&preg
->win0_vir
, V_RGB888_VIRWIDTH(hactive
));
78 write32(&preg
->win0_vir
, V_ARGB888_VIRWIDTH(hactive
));
83 lb_mode
= LB_RGB_3840X2
;
84 else if (hactive
> 1920)
85 lb_mode
= LB_RGB_2560X4
;
86 else if (hactive
> 1280)
87 lb_mode
= LB_RGB_1920X5
;
89 lb_mode
= LB_RGB_1280X8
;
91 clrsetbits32(&preg
->win0_ctrl0
,
92 M_WIN0_LB_MODE
| M_WIN0_DATA_FMT
| M_WIN0_EN
,
93 V_WIN0_LB_MODE(lb_mode
) |
94 V_WIN0_DATA_FMT(rgb_mode
) | V_WIN0_EN(1));
97 void rkvop_mode_set(u32 vop_id
, const struct edid
*edid
, u32 mode
)
99 u32 hactive
= edid
->mode
.ha
;
100 u32 vactive
= edid
->mode
.va
;
101 u32 hfront_porch
= edid
->mode
.hso
;
102 u32 hsync_len
= edid
->mode
.hspw
;
103 u32 hback_porch
= edid
->mode
.hbl
- edid
->mode
.hso
- edid
->mode
.hspw
;
104 u32 vfront_porch
= edid
->mode
.vso
;
105 u32 vsync_len
= edid
->mode
.vspw
;
106 u32 vback_porch
= edid
->mode
.vbl
- edid
->mode
.vso
- edid
->mode
.vspw
;
108 struct rockchip_vop_regs
*preg
= vop_regs
[vop_id
];
113 clrsetbits32(&preg
->sys_ctrl
,
114 M_ALL_OUT_EN
, V_HDMI_OUT_EN(1));
118 clrsetbits32(&preg
->sys_ctrl
, M_ALL_OUT_EN
,
122 case VOP_MODE_DUAL_MIPI
:
123 clrsetbits32(&preg
->sys_ctrl
, M_ALL_OUT_EN
,
124 V_MIPI_OUT_EN(1) | V_DUAL_MIPI_EN(1));
129 clrsetbits32(&preg
->sys_ctrl
,
130 M_ALL_OUT_EN
, V_EDP_OUT_EN(1));
135 clrsetbits32(&preg
->dsp_ctrl0
,
136 M_DSP_OUT_MODE
| M_DSP_VSYNC_POL
|
138 V_DSP_OUT_MODE(dsp_out_mode
) |
139 V_DSP_HSYNC_POL(edid
->mode
.phsync
== '+') |
140 V_DSP_VSYNC_POL(edid
->mode
.pvsync
== '+'));
142 write32(&preg
->dsp_htotal_hs_end
, V_HSYNC(hsync_len
) |
143 V_HORPRD(hsync_len
+ hback_porch
+ hactive
+ hfront_porch
));
145 write32(&preg
->dsp_hact_st_end
,
146 V_HEAP(hsync_len
+ hback_porch
+ hactive
) |
147 V_HASP(hsync_len
+ hback_porch
));
149 write32(&preg
->dsp_vtotal_vs_end
, V_VSYNC(vsync_len
) |
150 V_VERPRD(vsync_len
+ vback_porch
+ vactive
+ vfront_porch
));
152 write32(&preg
->dsp_vact_st_end
,
153 V_VAEP(vsync_len
+ vback_porch
+ vactive
) |
154 V_VASP(vsync_len
+ vback_porch
));
156 write32(&preg
->post_dsp_hact_info
,
157 V_HEAP(hsync_len
+ hback_porch
+ hactive
) |
158 V_HASP(hsync_len
+ hback_porch
));
160 write32(&preg
->post_dsp_vact_info
,
161 V_VAEP(vsync_len
+ vback_porch
+ vactive
) |
162 V_VASP(vsync_len
+ vback_porch
));
164 /* On RK3288, the reg_cfg_done[1:31] is reserved and read-only,
165 * but it's fine to write to it
167 write32(&preg
->reg_cfg_done
, 0xffff); /* enable reg config */