src/soc/rockchip/common/pwm.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright 2014 Rockchip Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <device/mmio.h>
  17 #include <soc/addressmap.h>
  18 #include <soc/grf.h>
  19 #include <soc/soc.h>
  20 #include <soc/pwm.h>
  21 #include <soc/clock.h>
  22 #include <timer.h>
  23
  24 struct pwm_ctl {
  25         u32     pwm_cnt;
  26         u32     pwm_period_hpr;
  27         u32     pwm_duty_lpr;
  28         u32     pwm_ctrl;
  29 };
  30
  31 struct rk_pwm_regs {
  32         struct pwm_ctl pwm[4];
  33         u32     intsts;
  34         u32     int_en;
  35 };
  36 check_member(rk_pwm_regs, int_en, 0x44);
  37
  38 #define RK_PWM_DISABLE                  (0 << 0)
  39 #define RK_PWM_ENABLE                   (1 << 0)
  40
  41
  42 #define PWM_ONE_SHOT                    (0 << 1)
  43 #define PWM_CONTINUOUS                  (1 << 1)
  44 #define RK_PWM_CAPTURE                  (1 << 2)
  45
  46 #define PWM_DUTY_POSTIVE                (1 << 3)
  47 #define PWM_DUTY_NEGATIVE               (0 << 3)
  48
  49 #define PWM_INACTIVE_POSTIVE            (1 << 4)
  50 #define PWM_INACTIVE_NEGATIVE           (0 << 4)
  51
  52 #define PWM_OUTPUT_LEFT                 (0 << 5)
  53 #define PWM_OUTPUT_CENTER               (1 << 5)
  54
  55 #define PWM_LP_ENABLE                   (1 << 8)
  56 #define PWM_LP_DISABLE                  (0 << 8)
  57
  58 #define PWM_SEL_SCALE_CLK                       (1 << 9)
  59 #define PWM_SEL_SRC_CLK                         (0 << 9)
  60
  61 struct rk_pwm_regs *rk_pwm = (void *)RK_PWM_BASE;
  62
  63 void pwm_init(u32 id, u32 period_ns, u32 duty_ns)
  64 {
  65         unsigned long period, duty;
  66
  67 #if CONFIG(SOC_ROCKCHIP_RK3288)
  68         /*use rk pwm*/
  69         write32(&rk3288_grf->soc_con2, RK_SETBITS(1 << 0));
  70 #endif
  71
  72         write32(&rk_pwm->pwm[id].pwm_ctrl, PWM_SEL_SRC_CLK |
  73                 PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_CONTINUOUS |
  74                 PWM_DUTY_POSTIVE | PWM_INACTIVE_POSTIVE | RK_PWM_DISABLE);
  75
  76         period = (PWM_CLOCK_HZ / 1000) * period_ns / USECS_PER_SEC;
  77         duty = (PWM_CLOCK_HZ / 1000) * duty_ns / USECS_PER_SEC;
  78
  79         write32(&rk_pwm->pwm[id].pwm_period_hpr, period);
  80         write32(&rk_pwm->pwm[id].pwm_duty_lpr, duty);
  81         setbits32(&rk_pwm->pwm[id].pwm_ctrl, RK_PWM_ENABLE);
  82 }