src/northbridge/intel/pineview/northbridge.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007-2009 coresystems GmbH
   5  * Copyright (C) 2015  Damien Zammit <damien@zamaudio.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <console/console.h>
  18 #include <arch/io.h>
  19 #include <stdint.h>
  20 #include <device/device.h>
  21 #include <device/pci.h>
  22 #include <device/pci_ids.h>
  23 #include <stdlib.h>
  24 #include <string.h>
  25 #include <cpu/cpu.h>
  26 #include <boot/tables.h>
  27 #include <arch/acpi.h>
  28 #include <northbridge/intel/pineview/pineview.h>
  29
  30 /* Reserve everything between A segment and 1MB:
  31  *
  32  * 0xa0000 - 0xbffff: legacy VGA
  33  * 0xc0000 - 0xcffff: VGA OPROM (needed by kernel)
  34  * 0xe0000 - 0xfffff: SeaBIOS, if used, otherwise DMI
  35  */
  36 static const int legacy_hole_base_k = 0xa0000 / 1024;
  37
  38 static void add_fixed_resources(struct device *dev, int index)
  39 {
  40         struct resource *resource;
  41
  42         resource = new_resource(dev, index++);
  43         resource->base = (resource_t) 0xfed00000;
  44         resource->size = (resource_t) 0x00100000;
  45         resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
  46                 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
  47
  48         mmio_resource(dev, index++, legacy_hole_base_k,
  49                         (0xc0000 >> 10) - legacy_hole_base_k);
  50         reserved_ram_resource(dev, index++, 0xc0000 >> 10,
  51                         (0x100000 - 0xc0000) >> 10);
  52 }
  53
  54 static void mch_domain_read_resources(struct device *dev)
  55 {
  56         u64 tom, touud;
  57         u32 tomk, tolud, tseg_sizek;
  58         u32 pcie_config_base, pcie_config_size;
  59         u16 index;
  60         const u32 top32memk = 4 * (GiB / KiB);
  61
  62         index = 3;
  63
  64         pci_domain_read_resources(dev);
  65
  66         /* Top of Upper Usable DRAM, including remap */
  67         touud = pci_read_config16(dev, TOUUD);
  68         touud <<= 20;
  69
  70         /* Top of Lower Usable DRAM */
  71         tolud = pci_read_config16(dev, TOLUD) & 0xfff0;
  72         tolud <<= 16;
  73
  74         /* Top of Memory - does not account for any UMA */
  75         tom = pci_read_config16(dev, TOM) & 0x1ff;
  76         tom <<= 27;
  77
  78         printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx ",
  79                touud, tolud, tom);
  80
  81         tomk = tolud >> 10;
  82
  83         /* Graphics memory */
  84         const u16 ggc = pci_read_config16(dev, GGC);
  85         const u32 gms_sizek = decode_igd_memory_size((ggc >> 4) & 0xf);
  86         printk(BIOS_DEBUG, "%uM UMA", gms_sizek >> 10);
  87         tomk -= gms_sizek;
  88
  89         /* GTT Graphics Stolen Memory Size (GGMS) */
  90         const u32 gsm_sizek = decode_igd_gtt_size((ggc >> 8) & 0xf);
  91         printk(BIOS_DEBUG, " and %uM GTT\n", gsm_sizek >> 10);
  92         tomk -= gsm_sizek;
  93
  94         const u32 tseg_basek = pci_read_config32(dev, TSEG) >> 10;
  95         const u32 igd_basek = pci_read_config32(dev, GBSM) >> 10;
  96         const u32 gtt_basek = pci_read_config32(dev, BGSM) >> 10;
  97
  98         /* Subtract TSEG size */
  99         tseg_sizek = gtt_basek - tseg_basek;
 100         tomk -= tseg_sizek;
 101
 102         /* Report the memory regions */
 103         ram_resource(dev, index++, 0, 640);
 104         ram_resource(dev, index++, 768, tomk - 768);
 105         reserved_ram_resource(dev, index++, tseg_basek, tseg_sizek);
 106         reserved_ram_resource(dev, index++, gtt_basek, gsm_sizek);
 107         reserved_ram_resource(dev, index++, igd_basek, gms_sizek);
 108
 109         /*
 110          * If > 4GB installed then memory from TOLUD to 4GB
 111          * is remapped above TOM, TOUUD will account for both
 112          */
 113         touud >>= 10; /* Convert to KB */
 114         if (touud > top32memk) {
 115                 ram_resource(dev, index++, top32memk, touud - top32memk);
 116                 printk(BIOS_INFO, "Available memory above 4GB: %lluM\n",
 117                        (touud - top32memk) >> 10);
 118         }
 119
 120         if (decode_pciebar(&pcie_config_base, &pcie_config_size)) {
 121                 printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x "
 122                         "size=0x%x\n", pcie_config_base, pcie_config_size);
 123                 fixed_mem_resource(dev, index++, pcie_config_base >> 10,
 124                         pcie_config_size >> 10, IORESOURCE_RESERVE);
 125         }
 126
 127         add_fixed_resources(dev, index);
 128 }
 129
 130 static void mch_domain_set_resources(struct device *dev)
 131 {
 132         struct resource *res;
 133
 134         for (res = dev->resource_list; res; res = res->next)
 135                 report_resource_stored(dev, res, "");
 136
 137         assign_resources(dev->link_list);
 138 }
 139
 140 static void mch_domain_init(struct device *dev)
 141 {
 142         u32 reg32;
 143
 144         /* Enable SERR */
 145         reg32 = pci_read_config32(dev, PCI_COMMAND);
 146         reg32 |= PCI_COMMAND_SERR;
 147         pci_write_config32(dev, PCI_COMMAND, reg32);
 148 }
 149
 150 static struct device_operations pci_domain_ops = {
 151         .read_resources   = mch_domain_read_resources,
 152         .set_resources    = mch_domain_set_resources,
 153         .init             = mch_domain_init,
 154         .scan_bus         = pci_domain_scan_bus,
 155         .acpi_fill_ssdt_generator = generate_cpu_entries,
 156 };
 157
 158 static void cpu_bus_init(struct device *dev)
 159 {
 160         initialize_cpus(dev->link_list);
 161 }
 162
 163 static struct device_operations cpu_bus_ops = {
 164         .read_resources   = DEVICE_NOOP,
 165         .set_resources    = DEVICE_NOOP,
 166         .enable_resources = DEVICE_NOOP,
 167         .init             = cpu_bus_init,
 168 };
 169
 170
 171 static void enable_dev(struct device *dev)
 172 {
 173         /* Set the operations if it is a special bus type */
 174         if (dev->path.type == DEVICE_PATH_DOMAIN) {
 175                 dev->ops = &pci_domain_ops;
 176         } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
 177                 dev->ops = &cpu_bus_ops;
 178         }
 179 }
 180
 181 struct chip_operations northbridge_intel_pineview_ops = {
 182         CHIP_NAME("Intel Pineview Northbridge")
 183         .enable_dev = enable_dev,
 184 };