src/southbridge/intel/i82371eb/early_pm.c

   1 /* This file is part of the coreboot project. */
   2 /*
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <stdint.h>
  16 #include <device/pci_ops.h>
  17 #include <device/pci.h>
  18 #include <device/pci_def.h>
  19 #include <device/pci_ids.h>
  20 #include "i82371eb.h"
  21
  22 void enable_pm(void)
  23 {
  24         pci_devfn_t dev;
  25         u8 reg8;
  26         u16 reg16;
  27
  28         /* Get the SMBus/PM device of the 82371AB/EB/MB. */
  29         dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL,
  30                                 PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI), 0);
  31
  32         /* Set the PM I/O base. */
  33         pci_write_config32(dev, PMBA, DEFAULT_PMBASE | 1);
  34
  35         /* Enable access to the PM I/O space. */
  36         reg16 = pci_read_config16(dev, PCI_COMMAND);
  37         reg16 |= PCI_COMMAND_IO;
  38         pci_write_config16(dev, PCI_COMMAND, reg16);
  39
  40         /* PM I/O Space Enable (PMIOSE). */
  41         reg8 = pci_read_config8(dev, PMREGMISC);
  42         reg8 |= PMIOSE;
  43         pci_write_config8(dev, PMREGMISC, reg8);
  44 }