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[cor.git] / drivers / rtc / rtc-davinci.c
blob390b7351e0fe62cda4c0ba1ff90b4e16a8d70b7f
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * DaVinci Power Management and Real Time Clock Driver for TI platforms
4 *
5 * Copyright (C) 2009 Texas Instruments, Inc
6 *
7 * Author: Miguel Aguilar <miguel.aguilar@ridgerun.com>
8 */
9 #include <linux/kernel.h>
10 #include <linux/init.h>
11 #include <linux/module.h>
12 #include <linux/ioport.h>
13 #include <linux/delay.h>
14 #include <linux/spinlock.h>
15 #include <linux/rtc.h>
16 #include <linux/bcd.h>
17 #include <linux/platform_device.h>
18 #include <linux/io.h>
19 #include <linux/slab.h>
20
21 /*
22 * The DaVinci RTC is a simple RTC with the following
23 * Sec: 0 - 59 : BCD count
24 * Min: 0 - 59 : BCD count
25 * Hour: 0 - 23 : BCD count
26 * Day: 0 - 0x7FFF(32767) : Binary count ( Over 89 years )
27 */
28
29 /* PRTC interface registers */
30 #define DAVINCI_PRTCIF_PID 0x00
31 #define PRTCIF_CTLR 0x04
32 #define PRTCIF_LDATA 0x08
33 #define PRTCIF_UDATA 0x0C
34 #define PRTCIF_INTEN 0x10
35 #define PRTCIF_INTFLG 0x14
36
37 /* PRTCIF_CTLR bit fields */
38 #define PRTCIF_CTLR_BUSY BIT(31)
39 #define PRTCIF_CTLR_SIZE BIT(25)
40 #define PRTCIF_CTLR_DIR BIT(24)
41 #define PRTCIF_CTLR_BENU_MSB BIT(23)
42 #define PRTCIF_CTLR_BENU_3RD_BYTE BIT(22)
43 #define PRTCIF_CTLR_BENU_2ND_BYTE BIT(21)
44 #define PRTCIF_CTLR_BENU_LSB BIT(20)
45 #define PRTCIF_CTLR_BENU_MASK (0x00F00000)
46 #define PRTCIF_CTLR_BENL_MSB BIT(19)
47 #define PRTCIF_CTLR_BENL_3RD_BYTE BIT(18)
48 #define PRTCIF_CTLR_BENL_2ND_BYTE BIT(17)
49 #define PRTCIF_CTLR_BENL_LSB BIT(16)
50 #define PRTCIF_CTLR_BENL_MASK (0x000F0000)
51
52 /* PRTCIF_INTEN bit fields */
53 #define PRTCIF_INTEN_RTCSS BIT(1)
54 #define PRTCIF_INTEN_RTCIF BIT(0)
55 #define PRTCIF_INTEN_MASK (PRTCIF_INTEN_RTCSS \
56 | PRTCIF_INTEN_RTCIF)
57
58 /* PRTCIF_INTFLG bit fields */
59 #define PRTCIF_INTFLG_RTCSS BIT(1)
60 #define PRTCIF_INTFLG_RTCIF BIT(0)
61 #define PRTCIF_INTFLG_MASK (PRTCIF_INTFLG_RTCSS \
62 | PRTCIF_INTFLG_RTCIF)
63
64 /* PRTC subsystem registers */
65 #define PRTCSS_RTC_INTC_EXTENA1 (0x0C)
66 #define PRTCSS_RTC_CTRL (0x10)
67 #define PRTCSS_RTC_WDT (0x11)
68 #define PRTCSS_RTC_TMR0 (0x12)
69 #define PRTCSS_RTC_TMR1 (0x13)
70 #define PRTCSS_RTC_CCTRL (0x14)
71 #define PRTCSS_RTC_SEC (0x15)
72 #define PRTCSS_RTC_MIN (0x16)
73 #define PRTCSS_RTC_HOUR (0x17)
74 #define PRTCSS_RTC_DAY0 (0x18)
75 #define PRTCSS_RTC_DAY1 (0x19)
76 #define PRTCSS_RTC_AMIN (0x1A)
77 #define PRTCSS_RTC_AHOUR (0x1B)
78 #define PRTCSS_RTC_ADAY0 (0x1C)
79 #define PRTCSS_RTC_ADAY1 (0x1D)
80 #define PRTCSS_RTC_CLKC_CNT (0x20)
81
82 /* PRTCSS_RTC_INTC_EXTENA1 */
83 #define PRTCSS_RTC_INTC_EXTENA1_MASK (0x07)
84
85 /* PRTCSS_RTC_CTRL bit fields */
86 #define PRTCSS_RTC_CTRL_WDTBUS BIT(7)
87 #define PRTCSS_RTC_CTRL_WEN BIT(6)
88 #define PRTCSS_RTC_CTRL_WDRT BIT(5)
89 #define PRTCSS_RTC_CTRL_WDTFLG BIT(4)
90 #define PRTCSS_RTC_CTRL_TE BIT(3)
91 #define PRTCSS_RTC_CTRL_TIEN BIT(2)
92 #define PRTCSS_RTC_CTRL_TMRFLG BIT(1)
93 #define PRTCSS_RTC_CTRL_TMMD BIT(0)
94
95 /* PRTCSS_RTC_CCTRL bit fields */
96 #define PRTCSS_RTC_CCTRL_CALBUSY BIT(7)
97 #define PRTCSS_RTC_CCTRL_DAEN BIT(5)
98 #define PRTCSS_RTC_CCTRL_HAEN BIT(4)
99 #define PRTCSS_RTC_CCTRL_MAEN BIT(3)
100 #define PRTCSS_RTC_CCTRL_ALMFLG BIT(2)
101 #define PRTCSS_RTC_CCTRL_AIEN BIT(1)
102 #define PRTCSS_RTC_CCTRL_CAEN BIT(0)
103
104 static DEFINE_SPINLOCK(davinci_rtc_lock);
105
106 struct davinci_rtc {
107 struct rtc_device *rtc;
108 void __iomem *base;
109 int irq;
110 };
111
112 static inline void rtcif_write(struct davinci_rtc *davinci_rtc,
113 u32 val, u32 addr)
114 {
115 writel(val, davinci_rtc->base + addr);
116 }
117
118 static inline u32 rtcif_read(struct davinci_rtc *davinci_rtc, u32 addr)
119 {
120 return readl(davinci_rtc->base + addr);
121 }
122
123 static inline void rtcif_wait(struct davinci_rtc *davinci_rtc)
124 {
125 while (rtcif_read(davinci_rtc, PRTCIF_CTLR) & PRTCIF_CTLR_BUSY)
126 cpu_relax();
127 }
128
129 static inline void rtcss_write(struct davinci_rtc *davinci_rtc,
130 unsigned long val, u8 addr)
131 {
132 rtcif_wait(davinci_rtc);
133
134 rtcif_write(davinci_rtc, PRTCIF_CTLR_BENL_LSB | addr, PRTCIF_CTLR);
135 rtcif_write(davinci_rtc, val, PRTCIF_LDATA);
136
137 rtcif_wait(davinci_rtc);
138 }
139
140 static inline u8 rtcss_read(struct davinci_rtc *davinci_rtc, u8 addr)
141 {
142 rtcif_wait(davinci_rtc);
143
144 rtcif_write(davinci_rtc, PRTCIF_CTLR_DIR | PRTCIF_CTLR_BENL_LSB | addr,
145 PRTCIF_CTLR);
146
147 rtcif_wait(davinci_rtc);
148
149 return rtcif_read(davinci_rtc, PRTCIF_LDATA);
150 }
151
152 static inline void davinci_rtcss_calendar_wait(struct davinci_rtc *davinci_rtc)
153 {
154 while (rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL) &
155 PRTCSS_RTC_CCTRL_CALBUSY)
156 cpu_relax();
157 }
158
159 static irqreturn_t davinci_rtc_interrupt(int irq, void *class_dev)
160 {
161 struct davinci_rtc *davinci_rtc = class_dev;
162 unsigned long events = 0;
163 u32 irq_flg;
164 u8 alm_irq, tmr_irq;
165 u8 rtc_ctrl, rtc_cctrl;
166 int ret = IRQ_NONE;
167
168 irq_flg = rtcif_read(davinci_rtc, PRTCIF_INTFLG) &
169 PRTCIF_INTFLG_RTCSS;
170
171 alm_irq = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL) &
172 PRTCSS_RTC_CCTRL_ALMFLG;
173
174 tmr_irq = rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL) &
175 PRTCSS_RTC_CTRL_TMRFLG;
176
177 if (irq_flg) {
178 if (alm_irq) {
179 events |= RTC_IRQF | RTC_AF;
180 rtc_cctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL);
181 rtc_cctrl |= PRTCSS_RTC_CCTRL_ALMFLG;
182 rtcss_write(davinci_rtc, rtc_cctrl, PRTCSS_RTC_CCTRL);
183 } else if (tmr_irq) {
184 events |= RTC_IRQF | RTC_PF;
185 rtc_ctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL);
186 rtc_ctrl |= PRTCSS_RTC_CTRL_TMRFLG;
187 rtcss_write(davinci_rtc, rtc_ctrl, PRTCSS_RTC_CTRL);
188 }
189
190 rtcif_write(davinci_rtc, PRTCIF_INTFLG_RTCSS,
191 PRTCIF_INTFLG);
192 rtc_update_irq(davinci_rtc->rtc, 1, events);
193
194 ret = IRQ_HANDLED;
195 }
196
197 return ret;
198 }
199
200 static int
201 davinci_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
202 {
203 struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
204 u8 rtc_ctrl;
205 unsigned long flags;
206 int ret = 0;
207
208 spin_lock_irqsave(&davinci_rtc_lock, flags);
209
210 rtc_ctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL);
211
212 switch (cmd) {
213 case RTC_WIE_ON:
214 rtc_ctrl |= PRTCSS_RTC_CTRL_WEN | PRTCSS_RTC_CTRL_WDTFLG;
215 break;
216 case RTC_WIE_OFF:
217 rtc_ctrl &= ~PRTCSS_RTC_CTRL_WEN;
218 break;
219 default:
220 ret = -ENOIOCTLCMD;
221 }
222
223 rtcss_write(davinci_rtc, rtc_ctrl, PRTCSS_RTC_CTRL);
224
225 spin_unlock_irqrestore(&davinci_rtc_lock, flags);
226
227 return ret;
228 }
229
230 static int convertfromdays(u16 days, struct rtc_time *tm)
231 {
232 int tmp_days, year, mon;
233
234 for (year = 2000;; year++) {
235 tmp_days = rtc_year_days(1, 12, year);
236 if (days >= tmp_days)
237 days -= tmp_days;
238 else {
239 for (mon = 0;; mon++) {
240 tmp_days = rtc_month_days(mon, year);
241 if (days >= tmp_days) {
242 days -= tmp_days;
243 } else {
244 tm->tm_year = year - 1900;
245 tm->tm_mon = mon;
246 tm->tm_mday = days + 1;
247 break;
248 }
249 }
250 break;
251 }
252 }
253 return 0;
254 }
255
256 static int convert2days(u16 *days, struct rtc_time *tm)
257 {
258 int i;
259 *days = 0;
260
261 /* epoch == 1900 */
262 if (tm->tm_year < 100 || tm->tm_year > 199)
263 return -EINVAL;
264
265 for (i = 2000; i < 1900 + tm->tm_year; i++)
266 *days += rtc_year_days(1, 12, i);
267
268 *days += rtc_year_days(tm->tm_mday, tm->tm_mon, 1900 + tm->tm_year);
269
270 return 0;
271 }
272
273 static int davinci_rtc_read_time(struct device *dev, struct rtc_time *tm)
274 {
275 struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
276 u16 days = 0;
277 u8 day0, day1;
278 unsigned long flags;
279
280 spin_lock_irqsave(&davinci_rtc_lock, flags);
281
282 davinci_rtcss_calendar_wait(davinci_rtc);
283 tm->tm_sec = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_SEC));
284
285 davinci_rtcss_calendar_wait(davinci_rtc);
286 tm->tm_min = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_MIN));
287
288 davinci_rtcss_calendar_wait(davinci_rtc);
289 tm->tm_hour = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_HOUR));
290
291 davinci_rtcss_calendar_wait(davinci_rtc);
292 day0 = rtcss_read(davinci_rtc, PRTCSS_RTC_DAY0);
293
294 davinci_rtcss_calendar_wait(davinci_rtc);
295 day1 = rtcss_read(davinci_rtc, PRTCSS_RTC_DAY1);
296
297 spin_unlock_irqrestore(&davinci_rtc_lock, flags);
298
299 days |= day1;
300 days <<= 8;
301 days |= day0;
302
303 if (convertfromdays(days, tm) < 0)
304 return -EINVAL;
305
306 return 0;
307 }
308
309 static int davinci_rtc_set_time(struct device *dev, struct rtc_time *tm)
310 {
311 struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
312 u16 days;
313 u8 rtc_cctrl;
314 unsigned long flags;
315
316 if (convert2days(&days, tm) < 0)
317 return -EINVAL;
318
319 spin_lock_irqsave(&davinci_rtc_lock, flags);
320
321 davinci_rtcss_calendar_wait(davinci_rtc);
322 rtcss_write(davinci_rtc, bin2bcd(tm->tm_sec), PRTCSS_RTC_SEC);
323
324 davinci_rtcss_calendar_wait(davinci_rtc);
325 rtcss_write(davinci_rtc, bin2bcd(tm->tm_min), PRTCSS_RTC_MIN);
326
327 davinci_rtcss_calendar_wait(davinci_rtc);
328 rtcss_write(davinci_rtc, bin2bcd(tm->tm_hour), PRTCSS_RTC_HOUR);
329
330 davinci_rtcss_calendar_wait(davinci_rtc);
331 rtcss_write(davinci_rtc, days & 0xFF, PRTCSS_RTC_DAY0);
332
333 davinci_rtcss_calendar_wait(davinci_rtc);
334 rtcss_write(davinci_rtc, (days & 0xFF00) >> 8, PRTCSS_RTC_DAY1);
335
336 rtc_cctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL);
337 rtc_cctrl |= PRTCSS_RTC_CCTRL_CAEN;
338 rtcss_write(davinci_rtc, rtc_cctrl, PRTCSS_RTC_CCTRL);
339
340 spin_unlock_irqrestore(&davinci_rtc_lock, flags);
341
342 return 0;
343 }
344
345 static int davinci_rtc_alarm_irq_enable(struct device *dev,
346 unsigned int enabled)
347 {
348 struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
349 unsigned long flags;
350 u8 rtc_cctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL);
351
352 spin_lock_irqsave(&davinci_rtc_lock, flags);
353
354 if (enabled)
355 rtc_cctrl |= PRTCSS_RTC_CCTRL_DAEN |
356 PRTCSS_RTC_CCTRL_HAEN |
357 PRTCSS_RTC_CCTRL_MAEN |
358 PRTCSS_RTC_CCTRL_ALMFLG |
359 PRTCSS_RTC_CCTRL_AIEN;
360 else
361 rtc_cctrl &= ~PRTCSS_RTC_CCTRL_AIEN;
362
363 davinci_rtcss_calendar_wait(davinci_rtc);
364 rtcss_write(davinci_rtc, rtc_cctrl, PRTCSS_RTC_CCTRL);
365
366 spin_unlock_irqrestore(&davinci_rtc_lock, flags);
367
368 return 0;
369 }
370
371 static int davinci_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
372 {
373 struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
374 u16 days = 0;
375 u8 day0, day1;
376 unsigned long flags;
377
378 alm->time.tm_sec = 0;
379
380 spin_lock_irqsave(&davinci_rtc_lock, flags);
381
382 davinci_rtcss_calendar_wait(davinci_rtc);
383 alm->time.tm_min = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_AMIN));
384
385 davinci_rtcss_calendar_wait(davinci_rtc);
386 alm->time.tm_hour = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_AHOUR));
387
388 davinci_rtcss_calendar_wait(davinci_rtc);
389 day0 = rtcss_read(davinci_rtc, PRTCSS_RTC_ADAY0);
390
391 davinci_rtcss_calendar_wait(davinci_rtc);
392 day1 = rtcss_read(davinci_rtc, PRTCSS_RTC_ADAY1);
393
394 spin_unlock_irqrestore(&davinci_rtc_lock, flags);
395 days |= day1;
396 days <<= 8;
397 days |= day0;
398
399 if (convertfromdays(days, &alm->time) < 0)
400 return -EINVAL;
401
402 alm->pending = !!(rtcss_read(davinci_rtc,
403 PRTCSS_RTC_CCTRL) &
404 PRTCSS_RTC_CCTRL_AIEN);
405 alm->enabled = alm->pending && device_may_wakeup(dev);
406
407 return 0;
408 }
409
410 static int davinci_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
411 {
412 struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
413 unsigned long flags;
414 u16 days;
415
416 if (alm->time.tm_mday <= 0 && alm->time.tm_mon < 0
417 && alm->time.tm_year < 0) {
418 struct rtc_time tm;
419 unsigned long now, then;
420
421 davinci_rtc_read_time(dev, &tm);
422 rtc_tm_to_time(&tm, &now);
423
424 alm->time.tm_mday = tm.tm_mday;
425 alm->time.tm_mon = tm.tm_mon;
426 alm->time.tm_year = tm.tm_year;
427 rtc_tm_to_time(&alm->time, &then);
428
429 if (then < now) {
430 rtc_time_to_tm(now + 24 * 60 * 60, &tm);
431 alm->time.tm_mday = tm.tm_mday;
432 alm->time.tm_mon = tm.tm_mon;
433 alm->time.tm_year = tm.tm_year;
434 }
435 }
436
437 if (convert2days(&days, &alm->time) < 0)
438 return -EINVAL;
439
440 spin_lock_irqsave(&davinci_rtc_lock, flags);
441
442 davinci_rtcss_calendar_wait(davinci_rtc);
443 rtcss_write(davinci_rtc, bin2bcd(alm->time.tm_min), PRTCSS_RTC_AMIN);
444
445 davinci_rtcss_calendar_wait(davinci_rtc);
446 rtcss_write(davinci_rtc, bin2bcd(alm->time.tm_hour), PRTCSS_RTC_AHOUR);
447
448 davinci_rtcss_calendar_wait(davinci_rtc);
449 rtcss_write(davinci_rtc, days & 0xFF, PRTCSS_RTC_ADAY0);
450
451 davinci_rtcss_calendar_wait(davinci_rtc);
452 rtcss_write(davinci_rtc, (days & 0xFF00) >> 8, PRTCSS_RTC_ADAY1);
453
454 spin_unlock_irqrestore(&davinci_rtc_lock, flags);
455
456 return 0;
457 }
458
459 static const struct rtc_class_ops davinci_rtc_ops = {
460 .ioctl = davinci_rtc_ioctl,
461 .read_time = davinci_rtc_read_time,
462 .set_time = davinci_rtc_set_time,
463 .alarm_irq_enable = davinci_rtc_alarm_irq_enable,
464 .read_alarm = davinci_rtc_read_alarm,
465 .set_alarm = davinci_rtc_set_alarm,
466 };
467
468 static int __init davinci_rtc_probe(struct platform_device *pdev)
469 {
470 struct device *dev = &pdev->dev;
471 struct davinci_rtc *davinci_rtc;
472 int ret = 0;
473
474 davinci_rtc = devm_kzalloc(&pdev->dev, sizeof(struct davinci_rtc), GFP_KERNEL);
475 if (!davinci_rtc)
476 return -ENOMEM;
477
478 davinci_rtc->irq = platform_get_irq(pdev, 0);
479 if (davinci_rtc->irq < 0)
480 return davinci_rtc->irq;
481
482 davinci_rtc->base = devm_platform_ioremap_resource(pdev, 0);
483 if (IS_ERR(davinci_rtc->base))
484 return PTR_ERR(davinci_rtc->base);
485
486 platform_set_drvdata(pdev, davinci_rtc);
487
488 davinci_rtc->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
489 &davinci_rtc_ops, THIS_MODULE);
490 if (IS_ERR(davinci_rtc->rtc)) {
491 dev_err(dev, "unable to register RTC device, err %d\n",
492 ret);
493 return PTR_ERR(davinci_rtc->rtc);
494 }
495
496 rtcif_write(davinci_rtc, PRTCIF_INTFLG_RTCSS, PRTCIF_INTFLG);
497 rtcif_write(davinci_rtc, 0, PRTCIF_INTEN);
498 rtcss_write(davinci_rtc, 0, PRTCSS_RTC_INTC_EXTENA1);
499
500 rtcss_write(davinci_rtc, 0, PRTCSS_RTC_CTRL);
501 rtcss_write(davinci_rtc, 0, PRTCSS_RTC_CCTRL);
502
503 ret = devm_request_irq(dev, davinci_rtc->irq, davinci_rtc_interrupt,
504 0, "davinci_rtc", davinci_rtc);
505 if (ret < 0) {
506 dev_err(dev, "unable to register davinci RTC interrupt\n");
507 return ret;
508 }
509
510 /* Enable interrupts */
511 rtcif_write(davinci_rtc, PRTCIF_INTEN_RTCSS, PRTCIF_INTEN);
512 rtcss_write(davinci_rtc, PRTCSS_RTC_INTC_EXTENA1_MASK,
513 PRTCSS_RTC_INTC_EXTENA1);
514
515 rtcss_write(davinci_rtc, PRTCSS_RTC_CCTRL_CAEN, PRTCSS_RTC_CCTRL);
516
517 device_init_wakeup(&pdev->dev, 0);
518
519 return 0;
520 }
521
522 static int __exit davinci_rtc_remove(struct platform_device *pdev)
523 {
524 struct davinci_rtc *davinci_rtc = platform_get_drvdata(pdev);
525
526 device_init_wakeup(&pdev->dev, 0);
527
528 rtcif_write(davinci_rtc, 0, PRTCIF_INTEN);
529
530 return 0;
531 }
532
533 static struct platform_driver davinci_rtc_driver = {
534 .remove = __exit_p(davinci_rtc_remove),
535 .driver = {
536 .name = "rtc_davinci",
537 },
538 };
539
540 module_platform_driver_probe(davinci_rtc_driver, davinci_rtc_probe);
541
542 MODULE_AUTHOR("Miguel Aguilar <miguel.aguilar@ridgerun.com>");
543 MODULE_DESCRIPTION("Texas Instruments DaVinci PRTC Driver");
544 MODULE_LICENSE("GPL");
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