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[cor.git] / drivers / crypto / ixp4xx_crypto.c
blob391e3b4df364f124eb5b2afef2ba1488e4e036e1
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Intel IXP4xx NPE-C crypto driver
4 *
5 * Copyright (C) 2008 Christian Hohnstaedt <chohnstaedt@innominate.com>
6 */
7
8 #include <linux/platform_device.h>
9 #include <linux/dma-mapping.h>
10 #include <linux/dmapool.h>
11 #include <linux/crypto.h>
12 #include <linux/kernel.h>
13 #include <linux/rtnetlink.h>
14 #include <linux/interrupt.h>
15 #include <linux/spinlock.h>
16 #include <linux/gfp.h>
17 #include <linux/module.h>
18
19 #include <crypto/ctr.h>
20 #include <crypto/internal/des.h>
21 #include <crypto/aes.h>
22 #include <crypto/hmac.h>
23 #include <crypto/sha.h>
24 #include <crypto/algapi.h>
25 #include <crypto/internal/aead.h>
26 #include <crypto/internal/skcipher.h>
27 #include <crypto/authenc.h>
28 #include <crypto/scatterwalk.h>
29
30 #include <linux/soc/ixp4xx/npe.h>
31 #include <linux/soc/ixp4xx/qmgr.h>
32
33 #define MAX_KEYLEN 32
34
35 /* hash: cfgword + 2 * digestlen; crypt: keylen + cfgword */
36 #define NPE_CTX_LEN 80
37 #define AES_BLOCK128 16
38
39 #define NPE_OP_HASH_VERIFY 0x01
40 #define NPE_OP_CCM_ENABLE 0x04
41 #define NPE_OP_CRYPT_ENABLE 0x08
42 #define NPE_OP_HASH_ENABLE 0x10
43 #define NPE_OP_NOT_IN_PLACE 0x20
44 #define NPE_OP_HMAC_DISABLE 0x40
45 #define NPE_OP_CRYPT_ENCRYPT 0x80
46
47 #define NPE_OP_CCM_GEN_MIC 0xcc
48 #define NPE_OP_HASH_GEN_ICV 0x50
49 #define NPE_OP_ENC_GEN_KEY 0xc9
50
51 #define MOD_ECB 0x0000
52 #define MOD_CTR 0x1000
53 #define MOD_CBC_ENC 0x2000
54 #define MOD_CBC_DEC 0x3000
55 #define MOD_CCM_ENC 0x4000
56 #define MOD_CCM_DEC 0x5000
57
58 #define KEYLEN_128 4
59 #define KEYLEN_192 6
60 #define KEYLEN_256 8
61
62 #define CIPH_DECR 0x0000
63 #define CIPH_ENCR 0x0400
64
65 #define MOD_DES 0x0000
66 #define MOD_TDEA2 0x0100
67 #define MOD_3DES 0x0200
68 #define MOD_AES 0x0800
69 #define MOD_AES128 (0x0800 | KEYLEN_128)
70 #define MOD_AES192 (0x0900 | KEYLEN_192)
71 #define MOD_AES256 (0x0a00 | KEYLEN_256)
72
73 #define MAX_IVLEN 16
74 #define NPE_ID 2 /* NPE C */
75 #define NPE_QLEN 16
76 /* Space for registering when the first
77 * NPE_QLEN crypt_ctl are busy */
78 #define NPE_QLEN_TOTAL 64
79
80 #define SEND_QID 29
81 #define RECV_QID 30
82
83 #define CTL_FLAG_UNUSED 0x0000
84 #define CTL_FLAG_USED 0x1000
85 #define CTL_FLAG_PERFORM_ABLK 0x0001
86 #define CTL_FLAG_GEN_ICV 0x0002
87 #define CTL_FLAG_GEN_REVAES 0x0004
88 #define CTL_FLAG_PERFORM_AEAD 0x0008
89 #define CTL_FLAG_MASK 0x000f
90
91 #define HMAC_PAD_BLOCKLEN SHA1_BLOCK_SIZE
92
93 #define MD5_DIGEST_SIZE 16
94
95 struct buffer_desc {
96 u32 phys_next;
97 #ifdef __ARMEB__
98 u16 buf_len;
99 u16 pkt_len;
100 #else
101 u16 pkt_len;
102 u16 buf_len;
103 #endif
104 dma_addr_t phys_addr;
105 u32 __reserved[4];
106 struct buffer_desc *next;
107 enum dma_data_direction dir;
108 };
109
110 struct crypt_ctl {
111 #ifdef __ARMEB__
112 u8 mode; /* NPE_OP_* operation mode */
113 u8 init_len;
114 u16 reserved;
115 #else
116 u16 reserved;
117 u8 init_len;
118 u8 mode; /* NPE_OP_* operation mode */
119 #endif
120 u8 iv[MAX_IVLEN]; /* IV for CBC mode or CTR IV for CTR mode */
121 dma_addr_t icv_rev_aes; /* icv or rev aes */
122 dma_addr_t src_buf;
123 dma_addr_t dst_buf;
124 #ifdef __ARMEB__
125 u16 auth_offs; /* Authentication start offset */
126 u16 auth_len; /* Authentication data length */
127 u16 crypt_offs; /* Cryption start offset */
128 u16 crypt_len; /* Cryption data length */
129 #else
130 u16 auth_len; /* Authentication data length */
131 u16 auth_offs; /* Authentication start offset */
132 u16 crypt_len; /* Cryption data length */
133 u16 crypt_offs; /* Cryption start offset */
134 #endif
135 u32 aadAddr; /* Additional Auth Data Addr for CCM mode */
136 u32 crypto_ctx; /* NPE Crypto Param structure address */
137
138 /* Used by Host: 4*4 bytes*/
139 unsigned ctl_flags;
140 union {
141 struct skcipher_request *ablk_req;
142 struct aead_request *aead_req;
143 struct crypto_tfm *tfm;
144 } data;
145 struct buffer_desc *regist_buf;
146 u8 *regist_ptr;
147 };
148
149 struct ablk_ctx {
150 struct buffer_desc *src;
151 struct buffer_desc *dst;
152 };
153
154 struct aead_ctx {
155 struct buffer_desc *src;
156 struct buffer_desc *dst;
157 struct scatterlist ivlist;
158 /* used when the hmac is not on one sg entry */
159 u8 *hmac_virt;
160 int encrypt;
161 };
162
163 struct ix_hash_algo {
164 u32 cfgword;
165 unsigned char *icv;
166 };
167
168 struct ix_sa_dir {
169 unsigned char *npe_ctx;
170 dma_addr_t npe_ctx_phys;
171 int npe_ctx_idx;
172 u8 npe_mode;
173 };
174
175 struct ixp_ctx {
176 struct ix_sa_dir encrypt;
177 struct ix_sa_dir decrypt;
178 int authkey_len;
179 u8 authkey[MAX_KEYLEN];
180 int enckey_len;
181 u8 enckey[MAX_KEYLEN];
182 u8 salt[MAX_IVLEN];
183 u8 nonce[CTR_RFC3686_NONCE_SIZE];
184 unsigned salted;
185 atomic_t configuring;
186 struct completion completion;
187 };
188
189 struct ixp_alg {
190 struct skcipher_alg crypto;
191 const struct ix_hash_algo *hash;
192 u32 cfg_enc;
193 u32 cfg_dec;
194
195 int registered;
196 };
197
198 struct ixp_aead_alg {
199 struct aead_alg crypto;
200 const struct ix_hash_algo *hash;
201 u32 cfg_enc;
202 u32 cfg_dec;
203
204 int registered;
205 };
206
207 static const struct ix_hash_algo hash_alg_md5 = {
208 .cfgword = 0xAA010004,
209 .icv = "\x01\x23\x45\x67\x89\xAB\xCD\xEF"
210 "\xFE\xDC\xBA\x98\x76\x54\x32\x10",
211 };
212 static const struct ix_hash_algo hash_alg_sha1 = {
213 .cfgword = 0x00000005,
214 .icv = "\x67\x45\x23\x01\xEF\xCD\xAB\x89\x98\xBA"
215 "\xDC\xFE\x10\x32\x54\x76\xC3\xD2\xE1\xF0",
216 };
217
218 static struct npe *npe_c;
219 static struct dma_pool *buffer_pool = NULL;
220 static struct dma_pool *ctx_pool = NULL;
221
222 static struct crypt_ctl *crypt_virt = NULL;
223 static dma_addr_t crypt_phys;
224
225 static int support_aes = 1;
226
227 #define DRIVER_NAME "ixp4xx_crypto"
228
229 static struct platform_device *pdev;
230
231 static inline dma_addr_t crypt_virt2phys(struct crypt_ctl *virt)
232 {
233 return crypt_phys + (virt - crypt_virt) * sizeof(struct crypt_ctl);
234 }
235
236 static inline struct crypt_ctl *crypt_phys2virt(dma_addr_t phys)
237 {
238 return crypt_virt + (phys - crypt_phys) / sizeof(struct crypt_ctl);
239 }
240
241 static inline u32 cipher_cfg_enc(struct crypto_tfm *tfm)
242 {
243 return container_of(tfm->__crt_alg, struct ixp_alg,crypto.base)->cfg_enc;
244 }
245
246 static inline u32 cipher_cfg_dec(struct crypto_tfm *tfm)
247 {
248 return container_of(tfm->__crt_alg, struct ixp_alg,crypto.base)->cfg_dec;
249 }
250
251 static inline const struct ix_hash_algo *ix_hash(struct crypto_tfm *tfm)
252 {
253 return container_of(tfm->__crt_alg, struct ixp_alg, crypto.base)->hash;
254 }
255
256 static int setup_crypt_desc(void)
257 {
258 struct device *dev = &pdev->dev;
259 BUILD_BUG_ON(sizeof(struct crypt_ctl) != 64);
260 crypt_virt = dma_alloc_coherent(dev,
261 NPE_QLEN * sizeof(struct crypt_ctl),
262 &crypt_phys, GFP_ATOMIC);
263 if (!crypt_virt)
264 return -ENOMEM;
265 return 0;
266 }
267
268 static spinlock_t desc_lock;
269 static struct crypt_ctl *get_crypt_desc(void)
270 {
271 int i;
272 static int idx = 0;
273 unsigned long flags;
274
275 spin_lock_irqsave(&desc_lock, flags);
276
277 if (unlikely(!crypt_virt))
278 setup_crypt_desc();
279 if (unlikely(!crypt_virt)) {
280 spin_unlock_irqrestore(&desc_lock, flags);
281 return NULL;
282 }
283 i = idx;
284 if (crypt_virt[i].ctl_flags == CTL_FLAG_UNUSED) {
285 if (++idx >= NPE_QLEN)
286 idx = 0;
287 crypt_virt[i].ctl_flags = CTL_FLAG_USED;
288 spin_unlock_irqrestore(&desc_lock, flags);
289 return crypt_virt +i;
290 } else {
291 spin_unlock_irqrestore(&desc_lock, flags);
292 return NULL;
293 }
294 }
295
296 static spinlock_t emerg_lock;
297 static struct crypt_ctl *get_crypt_desc_emerg(void)
298 {
299 int i;
300 static int idx = NPE_QLEN;
301 struct crypt_ctl *desc;
302 unsigned long flags;
303
304 desc = get_crypt_desc();
305 if (desc)
306 return desc;
307 if (unlikely(!crypt_virt))
308 return NULL;
309
310 spin_lock_irqsave(&emerg_lock, flags);
311 i = idx;
312 if (crypt_virt[i].ctl_flags == CTL_FLAG_UNUSED) {
313 if (++idx >= NPE_QLEN_TOTAL)
314 idx = NPE_QLEN;
315 crypt_virt[i].ctl_flags = CTL_FLAG_USED;
316 spin_unlock_irqrestore(&emerg_lock, flags);
317 return crypt_virt +i;
318 } else {
319 spin_unlock_irqrestore(&emerg_lock, flags);
320 return NULL;
321 }
322 }
323
324 static void free_buf_chain(struct device *dev, struct buffer_desc *buf,
325 dma_addr_t phys)
326 {
327 while (buf) {
328 struct buffer_desc *buf1;
329 u32 phys1;
330
331 buf1 = buf->next;
332 phys1 = buf->phys_next;
333 dma_unmap_single(dev, buf->phys_next, buf->buf_len, buf->dir);
334 dma_pool_free(buffer_pool, buf, phys);
335 buf = buf1;
336 phys = phys1;
337 }
338 }
339
340 static struct tasklet_struct crypto_done_tasklet;
341
342 static void finish_scattered_hmac(struct crypt_ctl *crypt)
343 {
344 struct aead_request *req = crypt->data.aead_req;
345 struct aead_ctx *req_ctx = aead_request_ctx(req);
346 struct crypto_aead *tfm = crypto_aead_reqtfm(req);
347 int authsize = crypto_aead_authsize(tfm);
348 int decryptlen = req->assoclen + req->cryptlen - authsize;
349
350 if (req_ctx->encrypt) {
351 scatterwalk_map_and_copy(req_ctx->hmac_virt,
352 req->dst, decryptlen, authsize, 1);
353 }
354 dma_pool_free(buffer_pool, req_ctx->hmac_virt, crypt->icv_rev_aes);
355 }
356
357 static void one_packet(dma_addr_t phys)
358 {
359 struct device *dev = &pdev->dev;
360 struct crypt_ctl *crypt;
361 struct ixp_ctx *ctx;
362 int failed;
363
364 failed = phys & 0x1 ? -EBADMSG : 0;
365 phys &= ~0x3;
366 crypt = crypt_phys2virt(phys);
367
368 switch (crypt->ctl_flags & CTL_FLAG_MASK) {
369 case CTL_FLAG_PERFORM_AEAD: {
370 struct aead_request *req = crypt->data.aead_req;
371 struct aead_ctx *req_ctx = aead_request_ctx(req);
372
373 free_buf_chain(dev, req_ctx->src, crypt->src_buf);
374 free_buf_chain(dev, req_ctx->dst, crypt->dst_buf);
375 if (req_ctx->hmac_virt) {
376 finish_scattered_hmac(crypt);
377 }
378 req->base.complete(&req->base, failed);
379 break;
380 }
381 case CTL_FLAG_PERFORM_ABLK: {
382 struct skcipher_request *req = crypt->data.ablk_req;
383 struct ablk_ctx *req_ctx = skcipher_request_ctx(req);
384
385 if (req_ctx->dst) {
386 free_buf_chain(dev, req_ctx->dst, crypt->dst_buf);
387 }
388 free_buf_chain(dev, req_ctx->src, crypt->src_buf);
389 req->base.complete(&req->base, failed);
390 break;
391 }
392 case CTL_FLAG_GEN_ICV:
393 ctx = crypto_tfm_ctx(crypt->data.tfm);
394 dma_pool_free(ctx_pool, crypt->regist_ptr,
395 crypt->regist_buf->phys_addr);
396 dma_pool_free(buffer_pool, crypt->regist_buf, crypt->src_buf);
397 if (atomic_dec_and_test(&ctx->configuring))
398 complete(&ctx->completion);
399 break;
400 case CTL_FLAG_GEN_REVAES:
401 ctx = crypto_tfm_ctx(crypt->data.tfm);
402 *(u32*)ctx->decrypt.npe_ctx &= cpu_to_be32(~CIPH_ENCR);
403 if (atomic_dec_and_test(&ctx->configuring))
404 complete(&ctx->completion);
405 break;
406 default:
407 BUG();
408 }
409 crypt->ctl_flags = CTL_FLAG_UNUSED;
410 }
411
412 static void irqhandler(void *_unused)
413 {
414 tasklet_schedule(&crypto_done_tasklet);
415 }
416
417 static void crypto_done_action(unsigned long arg)
418 {
419 int i;
420
421 for(i=0; i<4; i++) {
422 dma_addr_t phys = qmgr_get_entry(RECV_QID);
423 if (!phys)
424 return;
425 one_packet(phys);
426 }
427 tasklet_schedule(&crypto_done_tasklet);
428 }
429
430 static int init_ixp_crypto(struct device *dev)
431 {
432 int ret = -ENODEV;
433 u32 msg[2] = { 0, 0 };
434
435 if (! ( ~(*IXP4XX_EXP_CFG2) & (IXP4XX_FEATURE_HASH |
436 IXP4XX_FEATURE_AES | IXP4XX_FEATURE_DES))) {
437 printk(KERN_ERR "ixp_crypto: No HW crypto available\n");
438 return ret;
439 }
440 npe_c = npe_request(NPE_ID);
441 if (!npe_c)
442 return ret;
443
444 if (!npe_running(npe_c)) {
445 ret = npe_load_firmware(npe_c, npe_name(npe_c), dev);
446 if (ret)
447 goto npe_release;
448 if (npe_recv_message(npe_c, msg, "STATUS_MSG"))
449 goto npe_error;
450 } else {
451 if (npe_send_message(npe_c, msg, "STATUS_MSG"))
452 goto npe_error;
453
454 if (npe_recv_message(npe_c, msg, "STATUS_MSG"))
455 goto npe_error;
456 }
457
458 switch ((msg[1]>>16) & 0xff) {
459 case 3:
460 printk(KERN_WARNING "Firmware of %s lacks AES support\n",
461 npe_name(npe_c));
462 support_aes = 0;
463 break;
464 case 4:
465 case 5:
466 support_aes = 1;
467 break;
468 default:
469 printk(KERN_ERR "Firmware of %s lacks crypto support\n",
470 npe_name(npe_c));
471 ret = -ENODEV;
472 goto npe_release;
473 }
474 /* buffer_pool will also be used to sometimes store the hmac,
475 * so assure it is large enough
476 */
477 BUILD_BUG_ON(SHA1_DIGEST_SIZE > sizeof(struct buffer_desc));
478 buffer_pool = dma_pool_create("buffer", dev,
479 sizeof(struct buffer_desc), 32, 0);
480 ret = -ENOMEM;
481 if (!buffer_pool) {
482 goto err;
483 }
484 ctx_pool = dma_pool_create("context", dev,
485 NPE_CTX_LEN, 16, 0);
486 if (!ctx_pool) {
487 goto err;
488 }
489 ret = qmgr_request_queue(SEND_QID, NPE_QLEN_TOTAL, 0, 0,
490 "ixp_crypto:out", NULL);
491 if (ret)
492 goto err;
493 ret = qmgr_request_queue(RECV_QID, NPE_QLEN, 0, 0,
494 "ixp_crypto:in", NULL);
495 if (ret) {
496 qmgr_release_queue(SEND_QID);
497 goto err;
498 }
499 qmgr_set_irq(RECV_QID, QUEUE_IRQ_SRC_NOT_EMPTY, irqhandler, NULL);
500 tasklet_init(&crypto_done_tasklet, crypto_done_action, 0);
501
502 qmgr_enable_irq(RECV_QID);
503 return 0;
504
505 npe_error:
506 printk(KERN_ERR "%s not responding\n", npe_name(npe_c));
507 ret = -EIO;
508 err:
509 dma_pool_destroy(ctx_pool);
510 dma_pool_destroy(buffer_pool);
511 npe_release:
512 npe_release(npe_c);
513 return ret;
514 }
515
516 static void release_ixp_crypto(struct device *dev)
517 {
518 qmgr_disable_irq(RECV_QID);
519 tasklet_kill(&crypto_done_tasklet);
520
521 qmgr_release_queue(SEND_QID);
522 qmgr_release_queue(RECV_QID);
523
524 dma_pool_destroy(ctx_pool);
525 dma_pool_destroy(buffer_pool);
526
527 npe_release(npe_c);
528
529 if (crypt_virt) {
530 dma_free_coherent(dev,
531 NPE_QLEN_TOTAL * sizeof( struct crypt_ctl),
532 crypt_virt, crypt_phys);
533 }
534 }
535
536 static void reset_sa_dir(struct ix_sa_dir *dir)
537 {
538 memset(dir->npe_ctx, 0, NPE_CTX_LEN);
539 dir->npe_ctx_idx = 0;
540 dir->npe_mode = 0;
541 }
542
543 static int init_sa_dir(struct ix_sa_dir *dir)
544 {
545 dir->npe_ctx = dma_pool_alloc(ctx_pool, GFP_KERNEL, &dir->npe_ctx_phys);
546 if (!dir->npe_ctx) {
547 return -ENOMEM;
548 }
549 reset_sa_dir(dir);
550 return 0;
551 }
552
553 static void free_sa_dir(struct ix_sa_dir *dir)
554 {
555 memset(dir->npe_ctx, 0, NPE_CTX_LEN);
556 dma_pool_free(ctx_pool, dir->npe_ctx, dir->npe_ctx_phys);
557 }
558
559 static int init_tfm(struct crypto_tfm *tfm)
560 {
561 struct ixp_ctx *ctx = crypto_tfm_ctx(tfm);
562 int ret;
563
564 atomic_set(&ctx->configuring, 0);
565 ret = init_sa_dir(&ctx->encrypt);
566 if (ret)
567 return ret;
568 ret = init_sa_dir(&ctx->decrypt);
569 if (ret) {
570 free_sa_dir(&ctx->encrypt);
571 }
572 return ret;
573 }
574
575 static int init_tfm_ablk(struct crypto_skcipher *tfm)
576 {
577 crypto_skcipher_set_reqsize(tfm, sizeof(struct ablk_ctx));
578 return init_tfm(crypto_skcipher_tfm(tfm));
579 }
580
581 static int init_tfm_aead(struct crypto_aead *tfm)
582 {
583 crypto_aead_set_reqsize(tfm, sizeof(struct aead_ctx));
584 return init_tfm(crypto_aead_tfm(tfm));
585 }
586
587 static void exit_tfm(struct crypto_tfm *tfm)
588 {
589 struct ixp_ctx *ctx = crypto_tfm_ctx(tfm);
590 free_sa_dir(&ctx->encrypt);
591 free_sa_dir(&ctx->decrypt);
592 }
593
594 static void exit_tfm_ablk(struct crypto_skcipher *tfm)
595 {
596 exit_tfm(crypto_skcipher_tfm(tfm));
597 }
598
599 static void exit_tfm_aead(struct crypto_aead *tfm)
600 {
601 exit_tfm(crypto_aead_tfm(tfm));
602 }
603
604 static int register_chain_var(struct crypto_tfm *tfm, u8 xpad, u32 target,
605 int init_len, u32 ctx_addr, const u8 *key, int key_len)
606 {
607 struct ixp_ctx *ctx = crypto_tfm_ctx(tfm);
608 struct crypt_ctl *crypt;
609 struct buffer_desc *buf;
610 int i;
611 u8 *pad;
612 dma_addr_t pad_phys, buf_phys;
613
614 BUILD_BUG_ON(NPE_CTX_LEN < HMAC_PAD_BLOCKLEN);
615 pad = dma_pool_alloc(ctx_pool, GFP_KERNEL, &pad_phys);
616 if (!pad)
617 return -ENOMEM;
618 buf = dma_pool_alloc(buffer_pool, GFP_KERNEL, &buf_phys);
619 if (!buf) {
620 dma_pool_free(ctx_pool, pad, pad_phys);
621 return -ENOMEM;
622 }
623 crypt = get_crypt_desc_emerg();
624 if (!crypt) {
625 dma_pool_free(ctx_pool, pad, pad_phys);
626 dma_pool_free(buffer_pool, buf, buf_phys);
627 return -EAGAIN;
628 }
629
630 memcpy(pad, key, key_len);
631 memset(pad + key_len, 0, HMAC_PAD_BLOCKLEN - key_len);
632 for (i = 0; i < HMAC_PAD_BLOCKLEN; i++) {
633 pad[i] ^= xpad;
634 }
635
636 crypt->data.tfm = tfm;
637 crypt->regist_ptr = pad;
638 crypt->regist_buf = buf;
639
640 crypt->auth_offs = 0;
641 crypt->auth_len = HMAC_PAD_BLOCKLEN;
642 crypt->crypto_ctx = ctx_addr;
643 crypt->src_buf = buf_phys;
644 crypt->icv_rev_aes = target;
645 crypt->mode = NPE_OP_HASH_GEN_ICV;
646 crypt->init_len = init_len;
647 crypt->ctl_flags |= CTL_FLAG_GEN_ICV;
648
649 buf->next = 0;
650 buf->buf_len = HMAC_PAD_BLOCKLEN;
651 buf->pkt_len = 0;
652 buf->phys_addr = pad_phys;
653
654 atomic_inc(&ctx->configuring);
655 qmgr_put_entry(SEND_QID, crypt_virt2phys(crypt));
656 BUG_ON(qmgr_stat_overflow(SEND_QID));
657 return 0;
658 }
659
660 static int setup_auth(struct crypto_tfm *tfm, int encrypt, unsigned authsize,
661 const u8 *key, int key_len, unsigned digest_len)
662 {
663 u32 itarget, otarget, npe_ctx_addr;
664 unsigned char *cinfo;
665 int init_len, ret = 0;
666 u32 cfgword;
667 struct ix_sa_dir *dir;
668 struct ixp_ctx *ctx = crypto_tfm_ctx(tfm);
669 const struct ix_hash_algo *algo;
670
671 dir = encrypt ? &ctx->encrypt : &ctx->decrypt;
672 cinfo = dir->npe_ctx + dir->npe_ctx_idx;
673 algo = ix_hash(tfm);
674
675 /* write cfg word to cryptinfo */
676 cfgword = algo->cfgword | ( authsize << 6); /* (authsize/4) << 8 */
677 #ifndef __ARMEB__
678 cfgword ^= 0xAA000000; /* change the "byte swap" flags */
679 #endif
680 *(u32*)cinfo = cpu_to_be32(cfgword);
681 cinfo += sizeof(cfgword);
682
683 /* write ICV to cryptinfo */
684 memcpy(cinfo, algo->icv, digest_len);
685 cinfo += digest_len;
686
687 itarget = dir->npe_ctx_phys + dir->npe_ctx_idx
688 + sizeof(algo->cfgword);
689 otarget = itarget + digest_len;
690 init_len = cinfo - (dir->npe_ctx + dir->npe_ctx_idx);
691 npe_ctx_addr = dir->npe_ctx_phys + dir->npe_ctx_idx;
692
693 dir->npe_ctx_idx += init_len;
694 dir->npe_mode |= NPE_OP_HASH_ENABLE;
695
696 if (!encrypt)
697 dir->npe_mode |= NPE_OP_HASH_VERIFY;
698
699 ret = register_chain_var(tfm, HMAC_OPAD_VALUE, otarget,
700 init_len, npe_ctx_addr, key, key_len);
701 if (ret)
702 return ret;
703 return register_chain_var(tfm, HMAC_IPAD_VALUE, itarget,
704 init_len, npe_ctx_addr, key, key_len);
705 }
706
707 static int gen_rev_aes_key(struct crypto_tfm *tfm)
708 {
709 struct crypt_ctl *crypt;
710 struct ixp_ctx *ctx = crypto_tfm_ctx(tfm);
711 struct ix_sa_dir *dir = &ctx->decrypt;
712
713 crypt = get_crypt_desc_emerg();
714 if (!crypt) {
715 return -EAGAIN;
716 }
717 *(u32*)dir->npe_ctx |= cpu_to_be32(CIPH_ENCR);
718
719 crypt->data.tfm = tfm;
720 crypt->crypt_offs = 0;
721 crypt->crypt_len = AES_BLOCK128;
722 crypt->src_buf = 0;
723 crypt->crypto_ctx = dir->npe_ctx_phys;
724 crypt->icv_rev_aes = dir->npe_ctx_phys + sizeof(u32);
725 crypt->mode = NPE_OP_ENC_GEN_KEY;
726 crypt->init_len = dir->npe_ctx_idx;
727 crypt->ctl_flags |= CTL_FLAG_GEN_REVAES;
728
729 atomic_inc(&ctx->configuring);
730 qmgr_put_entry(SEND_QID, crypt_virt2phys(crypt));
731 BUG_ON(qmgr_stat_overflow(SEND_QID));
732 return 0;
733 }
734
735 static int setup_cipher(struct crypto_tfm *tfm, int encrypt,
736 const u8 *key, int key_len)
737 {
738 u8 *cinfo;
739 u32 cipher_cfg;
740 u32 keylen_cfg = 0;
741 struct ix_sa_dir *dir;
742 struct ixp_ctx *ctx = crypto_tfm_ctx(tfm);
743 u32 *flags = &tfm->crt_flags;
744
745 dir = encrypt ? &ctx->encrypt : &ctx->decrypt;
746 cinfo = dir->npe_ctx;
747
748 if (encrypt) {
749 cipher_cfg = cipher_cfg_enc(tfm);
750 dir->npe_mode |= NPE_OP_CRYPT_ENCRYPT;
751 } else {
752 cipher_cfg = cipher_cfg_dec(tfm);
753 }
754 if (cipher_cfg & MOD_AES) {
755 switch (key_len) {
756 case 16: keylen_cfg = MOD_AES128; break;
757 case 24: keylen_cfg = MOD_AES192; break;
758 case 32: keylen_cfg = MOD_AES256; break;
759 default:
760 *flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;
761 return -EINVAL;
762 }
763 cipher_cfg |= keylen_cfg;
764 } else {
765 crypto_des_verify_key(tfm, key);
766 }
767 /* write cfg word to cryptinfo */
768 *(u32*)cinfo = cpu_to_be32(cipher_cfg);
769 cinfo += sizeof(cipher_cfg);
770
771 /* write cipher key to cryptinfo */
772 memcpy(cinfo, key, key_len);
773 /* NPE wants keylen set to DES3_EDE_KEY_SIZE even for single DES */
774 if (key_len < DES3_EDE_KEY_SIZE && !(cipher_cfg & MOD_AES)) {
775 memset(cinfo + key_len, 0, DES3_EDE_KEY_SIZE -key_len);
776 key_len = DES3_EDE_KEY_SIZE;
777 }
778 dir->npe_ctx_idx = sizeof(cipher_cfg) + key_len;
779 dir->npe_mode |= NPE_OP_CRYPT_ENABLE;
780 if ((cipher_cfg & MOD_AES) && !encrypt) {
781 return gen_rev_aes_key(tfm);
782 }
783 return 0;
784 }
785
786 static struct buffer_desc *chainup_buffers(struct device *dev,
787 struct scatterlist *sg, unsigned nbytes,
788 struct buffer_desc *buf, gfp_t flags,
789 enum dma_data_direction dir)
790 {
791 for (; nbytes > 0; sg = sg_next(sg)) {
792 unsigned len = min(nbytes, sg->length);
793 struct buffer_desc *next_buf;
794 dma_addr_t next_buf_phys;
795 void *ptr;
796
797 nbytes -= len;
798 ptr = sg_virt(sg);
799 next_buf = dma_pool_alloc(buffer_pool, flags, &next_buf_phys);
800 if (!next_buf) {
801 buf = NULL;
802 break;
803 }
804 sg_dma_address(sg) = dma_map_single(dev, ptr, len, dir);
805 buf->next = next_buf;
806 buf->phys_next = next_buf_phys;
807 buf = next_buf;
808
809 buf->phys_addr = sg_dma_address(sg);
810 buf->buf_len = len;
811 buf->dir = dir;
812 }
813 buf->next = NULL;
814 buf->phys_next = 0;
815 return buf;
816 }
817
818 static int ablk_setkey(struct crypto_skcipher *tfm, const u8 *key,
819 unsigned int key_len)
820 {
821 struct ixp_ctx *ctx = crypto_skcipher_ctx(tfm);
822 u32 *flags = &tfm->base.crt_flags;
823 int ret;
824
825 init_completion(&ctx->completion);
826 atomic_inc(&ctx->configuring);
827
828 reset_sa_dir(&ctx->encrypt);
829 reset_sa_dir(&ctx->decrypt);
830
831 ctx->encrypt.npe_mode = NPE_OP_HMAC_DISABLE;
832 ctx->decrypt.npe_mode = NPE_OP_HMAC_DISABLE;
833
834 ret = setup_cipher(&tfm->base, 0, key, key_len);
835 if (ret)
836 goto out;
837 ret = setup_cipher(&tfm->base, 1, key, key_len);
838 if (ret)
839 goto out;
840
841 if (*flags & CRYPTO_TFM_RES_WEAK_KEY) {
842 if (*flags & CRYPTO_TFM_REQ_FORBID_WEAK_KEYS) {
843 ret = -EINVAL;
844 } else {
845 *flags &= ~CRYPTO_TFM_RES_WEAK_KEY;
846 }
847 }
848 out:
849 if (!atomic_dec_and_test(&ctx->configuring))
850 wait_for_completion(&ctx->completion);
851 return ret;
852 }
853
854 static int ablk_des3_setkey(struct crypto_skcipher *tfm, const u8 *key,
855 unsigned int key_len)
856 {
857 return verify_skcipher_des3_key(tfm, key) ?:
858 ablk_setkey(tfm, key, key_len);
859 }
860
861 static int ablk_rfc3686_setkey(struct crypto_skcipher *tfm, const u8 *key,
862 unsigned int key_len)
863 {
864 struct ixp_ctx *ctx = crypto_skcipher_ctx(tfm);
865
866 /* the nonce is stored in bytes at end of key */
867 if (key_len < CTR_RFC3686_NONCE_SIZE)
868 return -EINVAL;
869
870 memcpy(ctx->nonce, key + (key_len - CTR_RFC3686_NONCE_SIZE),
871 CTR_RFC3686_NONCE_SIZE);
872
873 key_len -= CTR_RFC3686_NONCE_SIZE;
874 return ablk_setkey(tfm, key, key_len);
875 }
876
877 static int ablk_perform(struct skcipher_request *req, int encrypt)
878 {
879 struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
880 struct ixp_ctx *ctx = crypto_skcipher_ctx(tfm);
881 unsigned ivsize = crypto_skcipher_ivsize(tfm);
882 struct ix_sa_dir *dir;
883 struct crypt_ctl *crypt;
884 unsigned int nbytes = req->cryptlen;
885 enum dma_data_direction src_direction = DMA_BIDIRECTIONAL;
886 struct ablk_ctx *req_ctx = skcipher_request_ctx(req);
887 struct buffer_desc src_hook;
888 struct device *dev = &pdev->dev;
889 gfp_t flags = req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP ?
890 GFP_KERNEL : GFP_ATOMIC;
891
892 if (qmgr_stat_full(SEND_QID))
893 return -EAGAIN;
894 if (atomic_read(&ctx->configuring))
895 return -EAGAIN;
896
897 dir = encrypt ? &ctx->encrypt : &ctx->decrypt;
898
899 crypt = get_crypt_desc();
900 if (!crypt)
901 return -ENOMEM;
902
903 crypt->data.ablk_req = req;
904 crypt->crypto_ctx = dir->npe_ctx_phys;
905 crypt->mode = dir->npe_mode;
906 crypt->init_len = dir->npe_ctx_idx;
907
908 crypt->crypt_offs = 0;
909 crypt->crypt_len = nbytes;
910
911 BUG_ON(ivsize && !req->iv);
912 memcpy(crypt->iv, req->iv, ivsize);
913 if (req->src != req->dst) {
914 struct buffer_desc dst_hook;
915 crypt->mode |= NPE_OP_NOT_IN_PLACE;
916 /* This was never tested by Intel
917 * for more than one dst buffer, I think. */
918 req_ctx->dst = NULL;
919 if (!chainup_buffers(dev, req->dst, nbytes, &dst_hook,
920 flags, DMA_FROM_DEVICE))
921 goto free_buf_dest;
922 src_direction = DMA_TO_DEVICE;
923 req_ctx->dst = dst_hook.next;
924 crypt->dst_buf = dst_hook.phys_next;
925 } else {
926 req_ctx->dst = NULL;
927 }
928 req_ctx->src = NULL;
929 if (!chainup_buffers(dev, req->src, nbytes, &src_hook,
930 flags, src_direction))
931 goto free_buf_src;
932
933 req_ctx->src = src_hook.next;
934 crypt->src_buf = src_hook.phys_next;
935 crypt->ctl_flags |= CTL_FLAG_PERFORM_ABLK;
936 qmgr_put_entry(SEND_QID, crypt_virt2phys(crypt));
937 BUG_ON(qmgr_stat_overflow(SEND_QID));
938 return -EINPROGRESS;
939
940 free_buf_src:
941 free_buf_chain(dev, req_ctx->src, crypt->src_buf);
942 free_buf_dest:
943 if (req->src != req->dst) {
944 free_buf_chain(dev, req_ctx->dst, crypt->dst_buf);
945 }
946 crypt->ctl_flags = CTL_FLAG_UNUSED;
947 return -ENOMEM;
948 }
949
950 static int ablk_encrypt(struct skcipher_request *req)
951 {
952 return ablk_perform(req, 1);
953 }
954
955 static int ablk_decrypt(struct skcipher_request *req)
956 {
957 return ablk_perform(req, 0);
958 }
959
960 static int ablk_rfc3686_crypt(struct skcipher_request *req)
961 {
962 struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
963 struct ixp_ctx *ctx = crypto_skcipher_ctx(tfm);
964 u8 iv[CTR_RFC3686_BLOCK_SIZE];
965 u8 *info = req->iv;
966 int ret;
967
968 /* set up counter block */
969 memcpy(iv, ctx->nonce, CTR_RFC3686_NONCE_SIZE);
970 memcpy(iv + CTR_RFC3686_NONCE_SIZE, info, CTR_RFC3686_IV_SIZE);
971
972 /* initialize counter portion of counter block */
973 *(__be32 *)(iv + CTR_RFC3686_NONCE_SIZE + CTR_RFC3686_IV_SIZE) =
974 cpu_to_be32(1);
975
976 req->iv = iv;
977 ret = ablk_perform(req, 1);
978 req->iv = info;
979 return ret;
980 }
981
982 static int aead_perform(struct aead_request *req, int encrypt,
983 int cryptoffset, int eff_cryptlen, u8 *iv)
984 {
985 struct crypto_aead *tfm = crypto_aead_reqtfm(req);
986 struct ixp_ctx *ctx = crypto_aead_ctx(tfm);
987 unsigned ivsize = crypto_aead_ivsize(tfm);
988 unsigned authsize = crypto_aead_authsize(tfm);
989 struct ix_sa_dir *dir;
990 struct crypt_ctl *crypt;
991 unsigned int cryptlen;
992 struct buffer_desc *buf, src_hook;
993 struct aead_ctx *req_ctx = aead_request_ctx(req);
994 struct device *dev = &pdev->dev;
995 gfp_t flags = req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP ?
996 GFP_KERNEL : GFP_ATOMIC;
997 enum dma_data_direction src_direction = DMA_BIDIRECTIONAL;
998 unsigned int lastlen;
999
1000 if (qmgr_stat_full(SEND_QID))
1001 return -EAGAIN;
1002 if (atomic_read(&ctx->configuring))
1003 return -EAGAIN;
1004
1005 if (encrypt) {
1006 dir = &ctx->encrypt;
1007 cryptlen = req->cryptlen;
1008 } else {
1009 dir = &ctx->decrypt;
1010 /* req->cryptlen includes the authsize when decrypting */
1011 cryptlen = req->cryptlen -authsize;
1012 eff_cryptlen -= authsize;
1013 }
1014 crypt = get_crypt_desc();
1015 if (!crypt)
1016 return -ENOMEM;
1017
1018 crypt->data.aead_req = req;
1019 crypt->crypto_ctx = dir->npe_ctx_phys;
1020 crypt->mode = dir->npe_mode;
1021 crypt->init_len = dir->npe_ctx_idx;
1022
1023 crypt->crypt_offs = cryptoffset;
1024 crypt->crypt_len = eff_cryptlen;
1025
1026 crypt->auth_offs = 0;
1027 crypt->auth_len = req->assoclen + cryptlen;
1028 BUG_ON(ivsize && !req->iv);
1029 memcpy(crypt->iv, req->iv, ivsize);
1030
1031 buf = chainup_buffers(dev, req->src, crypt->auth_len,
1032 &src_hook, flags, src_direction);
1033 req_ctx->src = src_hook.next;
1034 crypt->src_buf = src_hook.phys_next;
1035 if (!buf)
1036 goto free_buf_src;
1037
1038 lastlen = buf->buf_len;
1039 if (lastlen >= authsize)
1040 crypt->icv_rev_aes = buf->phys_addr +
1041 buf->buf_len - authsize;
1042
1043 req_ctx->dst = NULL;
1044
1045 if (req->src != req->dst) {
1046 struct buffer_desc dst_hook;
1047
1048 crypt->mode |= NPE_OP_NOT_IN_PLACE;
1049 src_direction = DMA_TO_DEVICE;
1050
1051 buf = chainup_buffers(dev, req->dst, crypt->auth_len,
1052 &dst_hook, flags, DMA_FROM_DEVICE);
1053 req_ctx->dst = dst_hook.next;
1054 crypt->dst_buf = dst_hook.phys_next;
1055
1056 if (!buf)
1057 goto free_buf_dst;
1058
1059 if (encrypt) {
1060 lastlen = buf->buf_len;
1061 if (lastlen >= authsize)
1062 crypt->icv_rev_aes = buf->phys_addr +
1063 buf->buf_len - authsize;
1064 }
1065 }
1066
1067 if (unlikely(lastlen < authsize)) {
1068 /* The 12 hmac bytes are scattered,
1069 * we need to copy them into a safe buffer */
1070 req_ctx->hmac_virt = dma_pool_alloc(buffer_pool, flags,
1071 &crypt->icv_rev_aes);
1072 if (unlikely(!req_ctx->hmac_virt))
1073 goto free_buf_dst;
1074 if (!encrypt) {
1075 scatterwalk_map_and_copy(req_ctx->hmac_virt,
1076 req->src, cryptlen, authsize, 0);
1077 }
1078 req_ctx->encrypt = encrypt;
1079 } else {
1080 req_ctx->hmac_virt = NULL;
1081 }
1082
1083 crypt->ctl_flags |= CTL_FLAG_PERFORM_AEAD;
1084 qmgr_put_entry(SEND_QID, crypt_virt2phys(crypt));
1085 BUG_ON(qmgr_stat_overflow(SEND_QID));
1086 return -EINPROGRESS;
1087
1088 free_buf_dst:
1089 free_buf_chain(dev, req_ctx->dst, crypt->dst_buf);
1090 free_buf_src:
1091 free_buf_chain(dev, req_ctx->src, crypt->src_buf);
1092 crypt->ctl_flags = CTL_FLAG_UNUSED;
1093 return -ENOMEM;
1094 }
1095
1096 static int aead_setup(struct crypto_aead *tfm, unsigned int authsize)
1097 {
1098 struct ixp_ctx *ctx = crypto_aead_ctx(tfm);
1099 u32 *flags = &tfm->base.crt_flags;
1100 unsigned digest_len = crypto_aead_maxauthsize(tfm);
1101 int ret;
1102
1103 if (!ctx->enckey_len && !ctx->authkey_len)
1104 return 0;
1105 init_completion(&ctx->completion);
1106 atomic_inc(&ctx->configuring);
1107
1108 reset_sa_dir(&ctx->encrypt);
1109 reset_sa_dir(&ctx->decrypt);
1110
1111 ret = setup_cipher(&tfm->base, 0, ctx->enckey, ctx->enckey_len);
1112 if (ret)
1113 goto out;
1114 ret = setup_cipher(&tfm->base, 1, ctx->enckey, ctx->enckey_len);
1115 if (ret)
1116 goto out;
1117 ret = setup_auth(&tfm->base, 0, authsize, ctx->authkey,
1118 ctx->authkey_len, digest_len);
1119 if (ret)
1120 goto out;
1121 ret = setup_auth(&tfm->base, 1, authsize, ctx->authkey,
1122 ctx->authkey_len, digest_len);
1123 if (ret)
1124 goto out;
1125
1126 if (*flags & CRYPTO_TFM_RES_WEAK_KEY) {
1127 if (*flags & CRYPTO_TFM_REQ_FORBID_WEAK_KEYS) {
1128 ret = -EINVAL;
1129 goto out;
1130 } else {
1131 *flags &= ~CRYPTO_TFM_RES_WEAK_KEY;
1132 }
1133 }
1134 out:
1135 if (!atomic_dec_and_test(&ctx->configuring))
1136 wait_for_completion(&ctx->completion);
1137 return ret;
1138 }
1139
1140 static int aead_setauthsize(struct crypto_aead *tfm, unsigned int authsize)
1141 {
1142 int max = crypto_aead_maxauthsize(tfm) >> 2;
1143
1144 if ((authsize>>2) < 1 || (authsize>>2) > max || (authsize & 3))
1145 return -EINVAL;
1146 return aead_setup(tfm, authsize);
1147 }
1148
1149 static int aead_setkey(struct crypto_aead *tfm, const u8 *key,
1150 unsigned int keylen)
1151 {
1152 struct ixp_ctx *ctx = crypto_aead_ctx(tfm);
1153 struct crypto_authenc_keys keys;
1154
1155 if (crypto_authenc_extractkeys(&keys, key, keylen) != 0)
1156 goto badkey;
1157
1158 if (keys.authkeylen > sizeof(ctx->authkey))
1159 goto badkey;
1160
1161 if (keys.enckeylen > sizeof(ctx->enckey))
1162 goto badkey;
1163
1164 memcpy(ctx->authkey, keys.authkey, keys.authkeylen);
1165 memcpy(ctx->enckey, keys.enckey, keys.enckeylen);
1166 ctx->authkey_len = keys.authkeylen;
1167 ctx->enckey_len = keys.enckeylen;
1168
1169 memzero_explicit(&keys, sizeof(keys));
1170 return aead_setup(tfm, crypto_aead_authsize(tfm));
1171 badkey:
1172 crypto_aead_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
1173 memzero_explicit(&keys, sizeof(keys));
1174 return -EINVAL;
1175 }
1176
1177 static int des3_aead_setkey(struct crypto_aead *tfm, const u8 *key,
1178 unsigned int keylen)
1179 {
1180 struct ixp_ctx *ctx = crypto_aead_ctx(tfm);
1181 struct crypto_authenc_keys keys;
1182 int err;
1183
1184 err = crypto_authenc_extractkeys(&keys, key, keylen);
1185 if (unlikely(err))
1186 goto badkey;
1187
1188 err = -EINVAL;
1189 if (keys.authkeylen > sizeof(ctx->authkey))
1190 goto badkey;
1191
1192 err = verify_aead_des3_key(tfm, keys.enckey, keys.enckeylen);
1193 if (err)
1194 goto badkey;
1195
1196 memcpy(ctx->authkey, keys.authkey, keys.authkeylen);
1197 memcpy(ctx->enckey, keys.enckey, keys.enckeylen);
1198 ctx->authkey_len = keys.authkeylen;
1199 ctx->enckey_len = keys.enckeylen;
1200
1201 memzero_explicit(&keys, sizeof(keys));
1202 return aead_setup(tfm, crypto_aead_authsize(tfm));
1203 badkey:
1204 memzero_explicit(&keys, sizeof(keys));
1205 return err;
1206 }
1207
1208 static int aead_encrypt(struct aead_request *req)
1209 {
1210 return aead_perform(req, 1, req->assoclen, req->cryptlen, req->iv);
1211 }
1212
1213 static int aead_decrypt(struct aead_request *req)
1214 {
1215 return aead_perform(req, 0, req->assoclen, req->cryptlen, req->iv);
1216 }
1217
1218 static struct ixp_alg ixp4xx_algos[] = {
1219 {
1220 .crypto = {
1221 .base.cra_name = "cbc(des)",
1222 .base.cra_blocksize = DES_BLOCK_SIZE,
1223
1224 .min_keysize = DES_KEY_SIZE,
1225 .max_keysize = DES_KEY_SIZE,
1226 .ivsize = DES_BLOCK_SIZE,
1227 },
1228 .cfg_enc = CIPH_ENCR | MOD_DES | MOD_CBC_ENC | KEYLEN_192,
1229 .cfg_dec = CIPH_DECR | MOD_DES | MOD_CBC_DEC | KEYLEN_192,
1230
1231 }, {
1232 .crypto = {
1233 .base.cra_name = "ecb(des)",
1234 .base.cra_blocksize = DES_BLOCK_SIZE,
1235 .min_keysize = DES_KEY_SIZE,
1236 .max_keysize = DES_KEY_SIZE,
1237 },
1238 .cfg_enc = CIPH_ENCR | MOD_DES | MOD_ECB | KEYLEN_192,
1239 .cfg_dec = CIPH_DECR | MOD_DES | MOD_ECB | KEYLEN_192,
1240 }, {
1241 .crypto = {
1242 .base.cra_name = "cbc(des3_ede)",
1243 .base.cra_blocksize = DES3_EDE_BLOCK_SIZE,
1244
1245 .min_keysize = DES3_EDE_KEY_SIZE,
1246 .max_keysize = DES3_EDE_KEY_SIZE,
1247 .ivsize = DES3_EDE_BLOCK_SIZE,
1248 .setkey = ablk_des3_setkey,
1249 },
1250 .cfg_enc = CIPH_ENCR | MOD_3DES | MOD_CBC_ENC | KEYLEN_192,
1251 .cfg_dec = CIPH_DECR | MOD_3DES | MOD_CBC_DEC | KEYLEN_192,
1252 }, {
1253 .crypto = {
1254 .base.cra_name = "ecb(des3_ede)",
1255 .base.cra_blocksize = DES3_EDE_BLOCK_SIZE,
1256
1257 .min_keysize = DES3_EDE_KEY_SIZE,
1258 .max_keysize = DES3_EDE_KEY_SIZE,
1259 .setkey = ablk_des3_setkey,
1260 },
1261 .cfg_enc = CIPH_ENCR | MOD_3DES | MOD_ECB | KEYLEN_192,
1262 .cfg_dec = CIPH_DECR | MOD_3DES | MOD_ECB | KEYLEN_192,
1263 }, {
1264 .crypto = {
1265 .base.cra_name = "cbc(aes)",
1266 .base.cra_blocksize = AES_BLOCK_SIZE,
1267
1268 .min_keysize = AES_MIN_KEY_SIZE,
1269 .max_keysize = AES_MAX_KEY_SIZE,
1270 .ivsize = AES_BLOCK_SIZE,
1271 },
1272 .cfg_enc = CIPH_ENCR | MOD_AES | MOD_CBC_ENC,
1273 .cfg_dec = CIPH_DECR | MOD_AES | MOD_CBC_DEC,
1274 }, {
1275 .crypto = {
1276 .base.cra_name = "ecb(aes)",
1277 .base.cra_blocksize = AES_BLOCK_SIZE,
1278
1279 .min_keysize = AES_MIN_KEY_SIZE,
1280 .max_keysize = AES_MAX_KEY_SIZE,
1281 },
1282 .cfg_enc = CIPH_ENCR | MOD_AES | MOD_ECB,
1283 .cfg_dec = CIPH_DECR | MOD_AES | MOD_ECB,
1284 }, {
1285 .crypto = {
1286 .base.cra_name = "ctr(aes)",
1287 .base.cra_blocksize = 1,
1288
1289 .min_keysize = AES_MIN_KEY_SIZE,
1290 .max_keysize = AES_MAX_KEY_SIZE,
1291 .ivsize = AES_BLOCK_SIZE,
1292 },
1293 .cfg_enc = CIPH_ENCR | MOD_AES | MOD_CTR,
1294 .cfg_dec = CIPH_ENCR | MOD_AES | MOD_CTR,
1295 }, {
1296 .crypto = {
1297 .base.cra_name = "rfc3686(ctr(aes))",
1298 .base.cra_blocksize = 1,
1299
1300 .min_keysize = AES_MIN_KEY_SIZE,
1301 .max_keysize = AES_MAX_KEY_SIZE,
1302 .ivsize = AES_BLOCK_SIZE,
1303 .setkey = ablk_rfc3686_setkey,
1304 .encrypt = ablk_rfc3686_crypt,
1305 .decrypt = ablk_rfc3686_crypt,
1306 },
1307 .cfg_enc = CIPH_ENCR | MOD_AES | MOD_CTR,
1308 .cfg_dec = CIPH_ENCR | MOD_AES | MOD_CTR,
1309 } };
1310
1311 static struct ixp_aead_alg ixp4xx_aeads[] = {
1312 {
1313 .crypto = {
1314 .base = {
1315 .cra_name = "authenc(hmac(md5),cbc(des))",
1316 .cra_blocksize = DES_BLOCK_SIZE,
1317 },
1318 .ivsize = DES_BLOCK_SIZE,
1319 .maxauthsize = MD5_DIGEST_SIZE,
1320 },
1321 .hash = &hash_alg_md5,
1322 .cfg_enc = CIPH_ENCR | MOD_DES | MOD_CBC_ENC | KEYLEN_192,
1323 .cfg_dec = CIPH_DECR | MOD_DES | MOD_CBC_DEC | KEYLEN_192,
1324 }, {
1325 .crypto = {
1326 .base = {
1327 .cra_name = "authenc(hmac(md5),cbc(des3_ede))",
1328 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1329 },
1330 .ivsize = DES3_EDE_BLOCK_SIZE,
1331 .maxauthsize = MD5_DIGEST_SIZE,
1332 .setkey = des3_aead_setkey,
1333 },
1334 .hash = &hash_alg_md5,
1335 .cfg_enc = CIPH_ENCR | MOD_3DES | MOD_CBC_ENC | KEYLEN_192,
1336 .cfg_dec = CIPH_DECR | MOD_3DES | MOD_CBC_DEC | KEYLEN_192,
1337 }, {
1338 .crypto = {
1339 .base = {
1340 .cra_name = "authenc(hmac(sha1),cbc(des))",
1341 .cra_blocksize = DES_BLOCK_SIZE,
1342 },
1343 .ivsize = DES_BLOCK_SIZE,
1344 .maxauthsize = SHA1_DIGEST_SIZE,
1345 },
1346 .hash = &hash_alg_sha1,
1347 .cfg_enc = CIPH_ENCR | MOD_DES | MOD_CBC_ENC | KEYLEN_192,
1348 .cfg_dec = CIPH_DECR | MOD_DES | MOD_CBC_DEC | KEYLEN_192,
1349 }, {
1350 .crypto = {
1351 .base = {
1352 .cra_name = "authenc(hmac(sha1),cbc(des3_ede))",
1353 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1354 },
1355 .ivsize = DES3_EDE_BLOCK_SIZE,
1356 .maxauthsize = SHA1_DIGEST_SIZE,
1357 .setkey = des3_aead_setkey,
1358 },
1359 .hash = &hash_alg_sha1,
1360 .cfg_enc = CIPH_ENCR | MOD_3DES | MOD_CBC_ENC | KEYLEN_192,
1361 .cfg_dec = CIPH_DECR | MOD_3DES | MOD_CBC_DEC | KEYLEN_192,
1362 }, {
1363 .crypto = {
1364 .base = {
1365 .cra_name = "authenc(hmac(md5),cbc(aes))",
1366 .cra_blocksize = AES_BLOCK_SIZE,
1367 },
1368 .ivsize = AES_BLOCK_SIZE,
1369 .maxauthsize = MD5_DIGEST_SIZE,
1370 },
1371 .hash = &hash_alg_md5,
1372 .cfg_enc = CIPH_ENCR | MOD_AES | MOD_CBC_ENC,
1373 .cfg_dec = CIPH_DECR | MOD_AES | MOD_CBC_DEC,
1374 }, {
1375 .crypto = {
1376 .base = {
1377 .cra_name = "authenc(hmac(sha1),cbc(aes))",
1378 .cra_blocksize = AES_BLOCK_SIZE,
1379 },
1380 .ivsize = AES_BLOCK_SIZE,
1381 .maxauthsize = SHA1_DIGEST_SIZE,
1382 },
1383 .hash = &hash_alg_sha1,
1384 .cfg_enc = CIPH_ENCR | MOD_AES | MOD_CBC_ENC,
1385 .cfg_dec = CIPH_DECR | MOD_AES | MOD_CBC_DEC,
1386 } };
1387
1388 #define IXP_POSTFIX "-ixp4xx"
1389
1390 static const struct platform_device_info ixp_dev_info __initdata = {
1391 .name = DRIVER_NAME,
1392 .id = 0,
1393 .dma_mask = DMA_BIT_MASK(32),
1394 };
1395
1396 static int __init ixp_module_init(void)
1397 {
1398 int num = ARRAY_SIZE(ixp4xx_algos);
1399 int i, err;
1400
1401 pdev = platform_device_register_full(&ixp_dev_info);
1402 if (IS_ERR(pdev))
1403 return PTR_ERR(pdev);
1404
1405 spin_lock_init(&desc_lock);
1406 spin_lock_init(&emerg_lock);
1407
1408 err = init_ixp_crypto(&pdev->dev);
1409 if (err) {
1410 platform_device_unregister(pdev);
1411 return err;
1412 }
1413 for (i=0; i< num; i++) {
1414 struct skcipher_alg *cra = &ixp4xx_algos[i].crypto;
1415
1416 if (snprintf(cra->base.cra_driver_name, CRYPTO_MAX_ALG_NAME,
1417 "%s"IXP_POSTFIX, cra->base.cra_name) >=
1418 CRYPTO_MAX_ALG_NAME)
1419 {
1420 continue;
1421 }
1422 if (!support_aes && (ixp4xx_algos[i].cfg_enc & MOD_AES)) {
1423 continue;
1424 }
1425
1426 /* block ciphers */
1427 cra->base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
1428 CRYPTO_ALG_ASYNC;
1429 if (!cra->setkey)
1430 cra->setkey = ablk_setkey;
1431 if (!cra->encrypt)
1432 cra->encrypt = ablk_encrypt;
1433 if (!cra->decrypt)
1434 cra->decrypt = ablk_decrypt;
1435 cra->init = init_tfm_ablk;
1436 cra->exit = exit_tfm_ablk;
1437
1438 cra->base.cra_ctxsize = sizeof(struct ixp_ctx);
1439 cra->base.cra_module = THIS_MODULE;
1440 cra->base.cra_alignmask = 3;
1441 cra->base.cra_priority = 300;
1442 if (crypto_register_skcipher(cra))
1443 printk(KERN_ERR "Failed to register '%s'\n",
1444 cra->base.cra_name);
1445 else
1446 ixp4xx_algos[i].registered = 1;
1447 }
1448
1449 for (i = 0; i < ARRAY_SIZE(ixp4xx_aeads); i++) {
1450 struct aead_alg *cra = &ixp4xx_aeads[i].crypto;
1451
1452 if (snprintf(cra->base.cra_driver_name, CRYPTO_MAX_ALG_NAME,
1453 "%s"IXP_POSTFIX, cra->base.cra_name) >=
1454 CRYPTO_MAX_ALG_NAME)
1455 continue;
1456 if (!support_aes && (ixp4xx_algos[i].cfg_enc & MOD_AES))
1457 continue;
1458
1459 /* authenc */
1460 cra->base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
1461 CRYPTO_ALG_ASYNC;
1462 cra->setkey = cra->setkey ?: aead_setkey;
1463 cra->setauthsize = aead_setauthsize;
1464 cra->encrypt = aead_encrypt;
1465 cra->decrypt = aead_decrypt;
1466 cra->init = init_tfm_aead;
1467 cra->exit = exit_tfm_aead;
1468
1469 cra->base.cra_ctxsize = sizeof(struct ixp_ctx);
1470 cra->base.cra_module = THIS_MODULE;
1471 cra->base.cra_alignmask = 3;
1472 cra->base.cra_priority = 300;
1473
1474 if (crypto_register_aead(cra))
1475 printk(KERN_ERR "Failed to register '%s'\n",
1476 cra->base.cra_driver_name);
1477 else
1478 ixp4xx_aeads[i].registered = 1;
1479 }
1480 return 0;
1481 }
1482
1483 static void __exit ixp_module_exit(void)
1484 {
1485 int num = ARRAY_SIZE(ixp4xx_algos);
1486 int i;
1487
1488 for (i = 0; i < ARRAY_SIZE(ixp4xx_aeads); i++) {
1489 if (ixp4xx_aeads[i].registered)
1490 crypto_unregister_aead(&ixp4xx_aeads[i].crypto);
1491 }
1492
1493 for (i=0; i< num; i++) {
1494 if (ixp4xx_algos[i].registered)
1495 crypto_unregister_skcipher(&ixp4xx_algos[i].crypto);
1496 }
1497 release_ixp_crypto(&pdev->dev);
1498 platform_device_unregister(pdev);
1499 }
1500
1501 module_init(ixp_module_init);
1502 module_exit(ixp_module_exit);
1503
1504 MODULE_LICENSE("GPL");
1505 MODULE_AUTHOR("Christian Hohnstaedt <chohnstaedt@innominate.com>");
1506 MODULE_DESCRIPTION("IXP4xx hardware crypto");
1507
connection oriented routing