6 config BR2_KERNEL_64_USERLAND_32
13 prompt "Target Architecture"
16 Select the target architecture family to build for.
19 bool "ARC (little endian)"
21 Synopsys' DesignWare ARC Processor Cores are a family of 32-bit CPUs
22 that can be used from deeply embedded to high performance host
23 applications. Little endian.
26 bool "ARC (big endian)"
28 Synopsys' DesignWare ARC Processor Cores are a family of 32-bit CPUs
29 that can be used from deeply embedded to high performance host
30 applications. Big endian.
33 bool "ARM (little endian)"
35 ARM is a 32-bit reduced instruction set computer (RISC) instruction
36 set architecture (ISA) developed by ARM Holdings. Little endian.
38 http://en.wikipedia.org/wiki/ARM
41 bool "ARM (big endian)"
43 ARM is a 32-bit reduced instruction set computer (RISC) instruction
44 set architecture (ISA) developed by ARM Holdings. Big endian.
46 http://en.wikipedia.org/wiki/ARM
52 Aarch64 is a 64-bit architecture developed by ARM Holdings.
53 http://www.arm.com/products/processors/instruction-set-architectures/armv8-architecture.php
54 http://en.wikipedia.org/wiki/ARM
59 # This architecture is obsolete and complicated to maintain to
60 # do the lack of upstream support in the major toolchain
61 # components. If you're interested by AVR32, contact the
62 # Buildroot community. Otherwise, its support will be removed
63 # by the 2015.02 release.
64 depends on BR2_DEPRECATED_SINCE_2014_08
66 The AVR32 is a 32-bit RISC microprocessor architecture designed by
69 http://en.wikipedia.org/wiki/Avr32
74 The Blackfin is a family of 16 or 32-bit microprocessors developed,
75 manufactured and marketed by Analog Devices.
76 http://www.analog.com/
77 http://en.wikipedia.org/wiki/Blackfin
82 Intel i386 architecture compatible microprocessor
83 http://en.wikipedia.org/wiki/I386
87 depends on BROKEN # ice in uclibc / inet_ntoa_r
89 Motorola 68000 family microprocessor
90 http://en.wikipedia.org/wiki/M68k
92 config BR2_microblazeel
93 bool "Microblaze AXI (little endian)"
95 Soft processor core designed for Xilinx FPGAs from Xilinx. AXI bus
96 based architecture (little endian)
98 http://en.wikipedia.org/wiki/Microblaze
100 config BR2_microblazebe
101 bool "Microblaze non-AXI (big endian)"
103 Soft processor core designed for Xilinx FPGAs from Xilinx. PLB bus
104 based architecture (non-AXI, big endian)
105 http://www.xilinx.com
106 http://en.wikipedia.org/wiki/Microblaze
109 bool "MIPS (big endian)"
111 MIPS is a RISC microprocessor from MIPS Technologies. Big endian.
113 http://en.wikipedia.org/wiki/MIPS_Technologies
116 bool "MIPS (little endian)"
118 MIPS is a RISC microprocessor from MIPS Technologies. Little endian.
120 http://en.wikipedia.org/wiki/MIPS_Technologies
123 bool "MIPS64 (big endian)"
124 select BR2_ARCH_IS_64
126 MIPS is a RISC microprocessor from MIPS Technologies. Big endian.
128 http://en.wikipedia.org/wiki/MIPS_Technologies
131 bool "MIPS64 (little endian)"
132 select BR2_ARCH_IS_64
134 MIPS is a RISC microprocessor from MIPS Technologies. Little endian.
136 http://en.wikipedia.org/wiki/MIPS_Technologies
141 Nios II is a soft core processor from Altera Corporation.
142 http://www.altera.com/
143 http://en.wikipedia.org/wiki/Nios_II
148 PowerPC is a RISC architecture created by Apple-IBM-Motorola alliance.
150 http://www.power.org/
151 http://en.wikipedia.org/wiki/Powerpc
154 bool "PowerPC64 (big endian)"
155 select BR2_ARCH_IS_64
157 PowerPC is a RISC architecture created by Apple-IBM-Motorola alliance.
159 http://www.power.org/
160 http://en.wikipedia.org/wiki/Powerpc
162 config BR2_powerpc64le
163 bool "PowerPC64 (little endian)"
164 select BR2_ARCH_IS_64
166 PowerPC is a RISC architecture created by Apple-IBM-Motorola alliance.
168 http://www.power.org/
169 http://en.wikipedia.org/wiki/Powerpc
174 SuperH (or SH) is a 32-bit reduced instruction set computer (RISC)
175 instruction set architecture (ISA) developed by Hitachi.
176 http://www.hitachi.com/
177 http://en.wikipedia.org/wiki/SuperH
182 SuperH64 (or SH) is a 64-bit reduced instruction set computer (RISC)
183 instruction set architecture (ISA) developed by Hitachi.
184 http://www.hitachi.com/
185 http://en.wikipedia.org/wiki/SuperH
190 SPARC (from Scalable Processor Architecture) is a RISC instruction
191 set architecture (ISA) developed by Sun Microsystems.
192 http://www.oracle.com/sun
193 http://en.wikipedia.org/wiki/Sparc
197 select BR2_ARCH_IS_64
199 x86-64 is an extension of the x86 instruction set (Intel i386
200 architecture compatible microprocessor).
201 http://en.wikipedia.org/wiki/X86_64
206 Xtensa is a Tensilica processor IP architecture.
207 http://en.wikipedia.org/wiki/Xtensa
208 http://www.tensilica.com/
212 # The following string values are defined by the individual
213 # Config.in.$ARCH files
220 config BR2_GCC_TARGET_TUNE
223 config BR2_GCC_TARGET_ARCH
226 config BR2_GCC_TARGET_ABI
229 config BR2_GCC_TARGET_CPU
232 config BR2_GCC_TARGET_CPU_REVISION
235 # The value of this option will be passed as --with-fpu=<value> when
236 # building gcc (internal backend) or -mfpu=<value> in the toolchain
237 # wrapper (external toolchain)
238 config BR2_GCC_TARGET_FPU
241 # The value of this option will be passed as --with-float=<value> when
242 # building gcc (internal backend) or -mfloat-abi=<value> in the toolchain
243 # wrapper (external toolchain)
244 config BR2_GCC_TARGET_FLOAT_ABI
247 # The value of this option will be passed as --with-mode=<value> when
248 # building gcc (internal backend) or -m<value> in the toolchain
249 # wrapper (external toolchain)
250 config BR2_GCC_TARGET_MODE
253 # If the architecture has atomic operations, select this:
254 config BR2_ARCH_HAS_ATOMICS
257 # Set up target binary format
259 prompt "Target Binary Format"
260 depends on BR2_bfin || BR2_m68k
261 default BR2_BINFMT_FDPIC
263 config BR2_BINFMT_ELF
265 depends on !BR2_bfin && !BR2_m68k
267 ELF (Executable and Linkable Format) is a format for libraries and
268 executables used across different architectures and operating
271 config BR2_BINFMT_FDPIC
273 depends on BR2_bfin || BR2_m68k
275 ELF FDPIC binaries are based on ELF, but allow the individual load
276 segments of a binary to be located in memory independently of each
277 other. This makes this format ideal for use in environments where no
280 config BR2_BINFMT_FLAT
282 depends on BR2_bfin || BR2_m68k
283 select BR2_PREFER_STATIC_LIB
285 FLAT binary is a relatively simple and lightweight executable format
286 based on the original a.out format. It is widely used in environment
287 where no MMU is available.
291 # Set up flat binary type
293 prompt "FLAT Binary type"
294 depends on BR2_BINFMT_FLAT
295 default BR2_BINFMT_FLAT_ONE
297 config BR2_BINFMT_FLAT_ONE
298 bool "One memory region"
300 All segments are linked into one memory region.
302 config BR2_BINFMT_FLAT_SEP_DATA
303 bool "Separate data and code region"
304 depends on BR2_bfin || BR2_m68k
306 Allow for the data and text segments to be separated and placed in
307 different regions of memory.
309 config BR2_BINFMT_FLAT_SHARED
311 depends on BR2_bfin || BR2_m68k
313 Allow to load and link indiviual FLAT binaries at run time.
317 if BR2_arcle || BR2_arceb
318 source "arch/Config.in.arc"
321 if BR2_arm || BR2_armeb
322 source "arch/Config.in.arm"
326 source "arch/Config.in.aarch64"
330 source "arch/Config.in.avr32"
334 source "arch/Config.in.bfin"
338 source "arch/Config.in.m68k"
341 if BR2_microblazeel || BR2_microblazebe
342 source "arch/Config.in.microblaze"
345 if BR2_mips || BR2_mips64 || BR2_mipsel || BR2_mips64el
346 source "arch/Config.in.mips"
350 source "arch/Config.in.nios2"
353 if BR2_powerpc || BR2_powerpc64 || BR2_powerpc64le
354 source "arch/Config.in.powerpc"
357 if BR2_sh || BR2_sh64
358 source "arch/Config.in.sh"
362 source "arch/Config.in.sparc"
365 if BR2_i386 || BR2_x86_64
366 source "arch/Config.in.x86"
370 source "arch/Config.in.xtensa"
373 endmenu # Target options