1 /* Print mips instructions for GDB, the GNU debugger, or for objdump.
2 Copyright (c) 1989, 91-97, 1998 Free Software Foundation, Inc.
3 Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
5 This file is part of GDB, GAS, and the GNU binutils.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
23 #include "opcode/mips.h"
26 /* FIXME: These are needed to figure out if the code is mips16 or
27 not. The low bit of the address is often a good indicator. No
28 symbol table is available when this code runs out in an embedded
29 system as when it is used for disassembler support in a monitor. */
31 #if !defined(EMBEDDED_ENV)
32 #define SYMTAB_AVAILABLE 1
37 static int print_insn_mips16
PARAMS ((bfd_vma
, struct disassemble_info
*));
38 static void print_mips16_insn_arg
39 PARAMS ((int, const struct mips_opcode
*, int, boolean
, int, bfd_vma
,
40 struct disassemble_info
*));
42 /* Mips instructions are never longer than this many bytes. */
45 static void print_insn_arg
PARAMS ((const char *, unsigned long, bfd_vma
,
46 struct disassemble_info
*));
47 static int _print_insn_mips
PARAMS ((bfd_vma
, unsigned long int,
48 struct disassemble_info
*));
51 /* FIXME: This should be shared with gdb somehow. */
52 #define REGISTER_NAMES \
53 { "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
54 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \
55 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
56 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", \
57 "sr", "lo", "hi", "bad", "cause","pc", \
58 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
59 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \
60 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",\
61 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",\
62 "fsr", "fir", "fp", "inx", "rand", "tlblo","ctxt", "tlbhi",\
66 static CONST
char * CONST reg_names
[] = REGISTER_NAMES
;
68 /* The mips16 register names. */
69 static const char * const mips16_reg_names
[] =
71 "s0", "s1", "v0", "v1", "a0", "a1", "a2", "a3"
76 print_insn_arg (d
, l
, pc
, info
)
78 register unsigned long int l
;
80 struct disassemble_info
*info
;
89 (*info
->fprintf_func
) (info
->stream
, "%c", *d
);
96 (*info
->fprintf_func
) (info
->stream
, "$%s",
97 reg_names
[(l
>> OP_SH_RS
) & OP_MASK_RS
]);
102 (*info
->fprintf_func
) (info
->stream
, "$%s",
103 reg_names
[(l
>> OP_SH_RT
) & OP_MASK_RT
]);
108 (*info
->fprintf_func
) (info
->stream
, "0x%x",
109 (l
>> OP_SH_IMMEDIATE
) & OP_MASK_IMMEDIATE
);
112 case 'j': /* same as i, but sign-extended */
114 delta
= (l
>> OP_SH_DELTA
) & OP_MASK_DELTA
;
117 (*info
->fprintf_func
) (info
->stream
, "%d",
122 (*info
->fprintf_func
) (info
->stream
, "0x%x",
123 (unsigned int) ((l
>> OP_SH_PREFX
)
128 (*info
->fprintf_func
) (info
->stream
, "0x%x",
129 (unsigned int) ((l
>> OP_SH_CACHE
)
134 (*info
->print_address_func
)
135 (((pc
& 0xF0000000) | (((l
>> OP_SH_TARGET
) & OP_MASK_TARGET
) << 2)),
140 /* sign extend the displacement */
141 delta
= (l
>> OP_SH_DELTA
) & OP_MASK_DELTA
;
144 (*info
->print_address_func
)
145 ((delta
<< 2) + pc
+ 4,
150 (*info
->fprintf_func
) (info
->stream
, "$%s",
151 reg_names
[(l
>> OP_SH_RD
) & OP_MASK_RD
]);
155 (*info
->fprintf_func
) (info
->stream
, "$%s", reg_names
[0]);
159 (*info
->fprintf_func
) (info
->stream
, "0x%x",
160 (l
>> OP_SH_SHAMT
) & OP_MASK_SHAMT
);
164 (*info
->fprintf_func
) (info
->stream
, "0x%x",
165 (l
>> OP_SH_CODE
) & OP_MASK_CODE
);
170 (*info
->fprintf_func
) (info
->stream
, "0x%x",
171 (l
>> OP_SH_CODE2
) & OP_MASK_CODE2
);
175 (*info
->fprintf_func
) (info
->stream
, "0x%x",
176 (l
>> OP_SH_COPZ
) & OP_MASK_COPZ
);
180 (*info
->fprintf_func
) (info
->stream
, "0x%x",
181 (l
>> OP_SH_SYSCALL
) & OP_MASK_SYSCALL
);
186 (*info
->fprintf_func
) (info
->stream
, "$f%d",
187 (l
>> OP_SH_FS
) & OP_MASK_FS
);
193 (*info
->fprintf_func
) (info
->stream
, "$f%d",
194 (l
>> OP_SH_FT
) & OP_MASK_FT
);
198 (*info
->fprintf_func
) (info
->stream
, "$f%d",
199 (l
>> OP_SH_FD
) & OP_MASK_FD
);
203 (*info
->fprintf_func
) (info
->stream
, "$f%d",
204 (l
>> OP_SH_FR
) & OP_MASK_FR
);
208 (*info
->fprintf_func
) (info
->stream
, "$%d",
209 (l
>> OP_SH_RT
) & OP_MASK_RT
);
213 (*info
->fprintf_func
) (info
->stream
, "$%d",
214 (l
>> OP_SH_RD
) & OP_MASK_RD
);
218 (*info
->fprintf_func
) (info
->stream
, "$fcc%d",
219 (l
>> OP_SH_BCC
) & OP_MASK_BCC
);
223 (*info
->fprintf_func
) (info
->stream
, "$fcc%d",
224 (l
>> OP_SH_CCC
) & OP_MASK_CCC
);
228 (*info
->fprintf_func
) (info
->stream
, "%d",
229 (l
>> OP_SH_PERFREG
) & OP_MASK_PERFREG
);
234 /* xgettext:c-format */
235 (*info
->fprintf_func
) (info
->stream
,
236 _("# internal error, undefined modifier(%c)"),
244 /* Figure out the MIPS ISA and CPU based on the machine number.
245 FIXME: What does this have to do with SYMTAB_AVAILABLE? */
248 set_mips_isa_type (mach
, isa
, cputype
)
253 int target_processor
= 0;
258 case bfd_mach_mips3000
:
259 target_processor
= 3000;
262 case bfd_mach_mips3900
:
263 target_processor
= 3900;
266 case bfd_mach_mips4000
:
267 target_processor
= 4000;
270 case bfd_mach_mips4010
:
271 target_processor
= 4010;
274 case bfd_mach_mips4100
:
275 target_processor
= 4100;
278 case bfd_mach_mips4111
:
279 target_processor
= 4100;
282 case bfd_mach_mips4300
:
283 target_processor
= 4300;
286 case bfd_mach_mips4400
:
287 target_processor
= 4400;
290 case bfd_mach_mips4600
:
291 target_processor
= 4600;
294 case bfd_mach_mips4650
:
295 target_processor
= 4650;
298 case bfd_mach_mips5000
:
299 target_processor
= 5000;
302 case bfd_mach_mips6000
:
303 target_processor
= 6000;
306 case bfd_mach_mips8000
:
307 target_processor
= 8000;
310 case bfd_mach_mips10000
:
311 target_processor
= 10000;
314 case bfd_mach_mips16
:
315 target_processor
= 16;
319 target_processor
= 3000;
326 *cputype
= target_processor
;
329 #endif /* SYMTAB_AVAILABLE */
331 /* Print the mips instruction at address MEMADDR in debugged memory,
332 on using INFO. Returns length of the instruction, in bytes, which is
333 always 4. BIGENDIAN must be 1 if this is big-endian code, 0 if
334 this is little-endian code. */
337 _print_insn_mips (memaddr
, word
, info
)
339 unsigned long int word
;
340 struct disassemble_info
*info
;
342 register const struct mips_opcode
*op
;
343 int target_processor
, mips_isa
;
344 static boolean init
= 0;
345 static const struct mips_opcode
*mips_hash
[OP_MASK_OP
+ 1];
347 /* Build a hash table to shorten the search time. */
352 for (i
= 0; i
<= OP_MASK_OP
; i
++)
354 for (op
= mips_opcodes
; op
< &mips_opcodes
[NUMOPCODES
]; op
++)
356 if (op
->pinfo
== INSN_MACRO
)
358 if (i
== ((op
->match
>> OP_SH_OP
) & OP_MASK_OP
))
369 #if ! SYMTAB_AVAILABLE
370 /* This is running out on a target machine, not in a host tool.
371 FIXME: Where does mips_target_info come from? */
372 target_processor
= mips_target_info
.processor
;
373 mips_isa
= mips_target_info
.isa
;
375 set_mips_isa_type (info
->mach
, &mips_isa
, &target_processor
);
378 info
->bytes_per_chunk
= 4;
379 info
->display_endian
= info
->endian
;
381 op
= mips_hash
[(word
>> OP_SH_OP
) & OP_MASK_OP
];
384 for (; op
< &mips_opcodes
[NUMOPCODES
]; op
++)
386 if (op
->pinfo
!= INSN_MACRO
&& (word
& op
->mask
) == op
->match
)
388 register const char *d
;
390 if (! OPCODE_IS_MEMBER (op
, mips_isa
, target_processor
, 0))
393 (*info
->fprintf_func
) (info
->stream
, "%s", op
->name
);
396 if (d
!= NULL
&& *d
!= '\0')
398 (*info
->fprintf_func
) (info
->stream
, "\t");
399 for (; *d
!= '\0'; d
++)
400 print_insn_arg (d
, word
, memaddr
, info
);
408 /* Handle undefined instructions. */
409 (*info
->fprintf_func
) (info
->stream
, "0x%x", word
);
414 /* In an environment where we do not know the symbol type of the
415 instruction we are forced to assume that the low order bit of the
416 instructions' address may mark it as a mips16 instruction. If we
417 are single stepping, or the pc is within the disassembled function,
418 this works. Otherwise, we need a clue. Sometimes. */
421 print_insn_big_mips (memaddr
, info
)
423 struct disassemble_info
*info
;
429 /* FIXME: If odd address, this is CLEARLY a mips 16 instruction. */
430 /* Only a few tools will work this way. */
432 return print_insn_mips16 (memaddr
, info
);
437 || (info
->flavour
== bfd_target_elf_flavour
438 && info
->symbols
!= NULL
439 && ((*(elf_symbol_type
**) info
->symbols
)->internal_elf_sym
.st_other
441 return print_insn_mips16 (memaddr
, info
);
444 status
= (*info
->read_memory_func
) (memaddr
, buffer
, 4, info
);
446 return _print_insn_mips (memaddr
, (unsigned long) bfd_getb32 (buffer
),
450 (*info
->memory_error_func
) (status
, memaddr
, info
);
456 print_insn_little_mips (memaddr
, info
)
458 struct disassemble_info
*info
;
466 return print_insn_mips16 (memaddr
, info
);
471 || (info
->flavour
== bfd_target_elf_flavour
472 && info
->symbols
!= NULL
473 && ((*(elf_symbol_type
**) info
->symbols
)->internal_elf_sym
.st_other
475 return print_insn_mips16 (memaddr
, info
);
478 status
= (*info
->read_memory_func
) (memaddr
, buffer
, 4, info
);
480 return _print_insn_mips (memaddr
, (unsigned long) bfd_getl32 (buffer
),
484 (*info
->memory_error_func
) (status
, memaddr
, info
);
489 /* Disassemble mips16 instructions. */
492 print_insn_mips16 (memaddr
, info
)
494 struct disassemble_info
*info
;
502 const struct mips_opcode
*op
, *opend
;
504 info
->bytes_per_chunk
= 2;
505 info
->display_endian
= info
->endian
;
507 info
->insn_info_valid
= 1;
508 info
->branch_delay_insns
= 0;
510 info
->insn_type
= dis_nonbranch
;
514 status
= (*info
->read_memory_func
) (memaddr
, buffer
, 2, info
);
517 (*info
->memory_error_func
) (status
, memaddr
, info
);
523 if (info
->endian
== BFD_ENDIAN_BIG
)
524 insn
= bfd_getb16 (buffer
);
526 insn
= bfd_getl16 (buffer
);
528 /* Handle the extend opcode specially. */
530 if ((insn
& 0xf800) == 0xf000)
533 extend
= insn
& 0x7ff;
537 status
= (*info
->read_memory_func
) (memaddr
, buffer
, 2, info
);
540 (*info
->fprintf_func
) (info
->stream
, "extend 0x%x",
541 (unsigned int) extend
);
542 (*info
->memory_error_func
) (status
, memaddr
, info
);
546 if (info
->endian
== BFD_ENDIAN_BIG
)
547 insn
= bfd_getb16 (buffer
);
549 insn
= bfd_getl16 (buffer
);
551 /* Check for an extend opcode followed by an extend opcode. */
552 if ((insn
& 0xf800) == 0xf000)
554 (*info
->fprintf_func
) (info
->stream
, "extend 0x%x",
555 (unsigned int) extend
);
556 info
->insn_type
= dis_noninsn
;
563 /* FIXME: Should probably use a hash table on the major opcode here. */
565 opend
= mips16_opcodes
+ bfd_mips16_num_opcodes
;
566 for (op
= mips16_opcodes
; op
< opend
; op
++)
568 if (op
->pinfo
!= INSN_MACRO
&& (insn
& op
->mask
) == op
->match
)
572 if (strchr (op
->args
, 'a') != NULL
)
576 (*info
->fprintf_func
) (info
->stream
, "extend 0x%x",
577 (unsigned int) extend
);
578 info
->insn_type
= dis_noninsn
;
586 status
= (*info
->read_memory_func
) (memaddr
, buffer
, 2,
591 if (info
->endian
== BFD_ENDIAN_BIG
)
592 extend
= bfd_getb16 (buffer
);
594 extend
= bfd_getl16 (buffer
);
599 (*info
->fprintf_func
) (info
->stream
, "%s", op
->name
);
600 if (op
->args
[0] != '\0')
601 (*info
->fprintf_func
) (info
->stream
, "\t");
603 for (s
= op
->args
; *s
!= '\0'; s
++)
607 && (((insn
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
)
608 == ((insn
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
)))
610 /* Skip the register and the comma. */
616 && (((insn
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
)
617 == ((insn
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
)))
619 /* Skip the register and the comma. */
623 print_mips16_insn_arg (*s
, op
, insn
, use_extend
, extend
, memaddr
,
627 if ((op
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
629 info
->branch_delay_insns
= 1;
630 if (info
->insn_type
!= dis_jsr
)
631 info
->insn_type
= dis_branch
;
639 (*info
->fprintf_func
) (info
->stream
, "0x%x", extend
| 0xf000);
640 (*info
->fprintf_func
) (info
->stream
, "0x%x", insn
);
641 info
->insn_type
= dis_noninsn
;
646 /* Disassemble an operand for a mips16 instruction. */
649 print_mips16_insn_arg (type
, op
, l
, use_extend
, extend
, memaddr
, info
)
651 const struct mips_opcode
*op
;
656 struct disassemble_info
*info
;
663 (*info
->fprintf_func
) (info
->stream
, "%c", type
);
668 (*info
->fprintf_func
) (info
->stream
, "$%s",
669 mips16_reg_names
[((l
>> MIPS16OP_SH_RY
)
670 & MIPS16OP_MASK_RY
)]);
675 (*info
->fprintf_func
) (info
->stream
, "$%s",
676 mips16_reg_names
[((l
>> MIPS16OP_SH_RX
)
677 & MIPS16OP_MASK_RX
)]);
681 (*info
->fprintf_func
) (info
->stream
, "$%s",
682 mips16_reg_names
[((l
>> MIPS16OP_SH_RZ
)
683 & MIPS16OP_MASK_RZ
)]);
687 (*info
->fprintf_func
) (info
->stream
, "$%s",
688 mips16_reg_names
[((l
>> MIPS16OP_SH_MOVE32Z
)
689 & MIPS16OP_MASK_MOVE32Z
)]);
693 (*info
->fprintf_func
) (info
->stream
, "$%s", reg_names
[0]);
697 (*info
->fprintf_func
) (info
->stream
, "$%s", reg_names
[29]);
701 (*info
->fprintf_func
) (info
->stream
, "$pc");
705 (*info
->fprintf_func
) (info
->stream
, "$%s", reg_names
[31]);
709 (*info
->fprintf_func
) (info
->stream
, "$%s",
710 reg_names
[((l
>> MIPS16OP_SH_REGR32
)
711 & MIPS16OP_MASK_REGR32
)]);
715 (*info
->fprintf_func
) (info
->stream
, "$%s",
716 reg_names
[MIPS16OP_EXTRACT_REG32R (l
)]);
742 int immed
, nbits
, shift
, signedp
, extbits
, pcrel
, extu
, branch
;
754 immed
= (l
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
760 immed
= (l
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
766 immed
= (l
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
772 immed
= (l
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
778 immed
= (l
>> MIPS16OP_SH_IMM4
) & MIPS16OP_MASK_IMM4
;
784 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
785 info
->insn_type
= dis_dref
;
791 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
792 info
->insn_type
= dis_dref
;
798 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
799 if ((op
->pinfo
& MIPS16_INSN_READ_PC
) == 0
800 && (op
->pinfo
& MIPS16_INSN_READ_SP
) == 0)
802 info
->insn_type
= dis_dref
;
809 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
810 info
->insn_type
= dis_dref
;
815 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
820 immed
= (l
>> MIPS16OP_SH_IMM6
) & MIPS16OP_MASK_IMM6
;
824 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
829 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
830 /* FIXME: This might be lw, or it might be addiu to $sp or
831 $pc. We assume it's load. */
832 info
->insn_type
= dis_dref
;
838 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
839 info
->insn_type
= dis_dref
;
844 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
849 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
855 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
860 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
864 info
->insn_type
= dis_condbranch
;
868 immed
= (l
>> MIPS16OP_SH_IMM11
) & MIPS16OP_MASK_IMM11
;
872 info
->insn_type
= dis_branch
;
877 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
879 /* FIXME: This can be lw or la. We assume it is lw. */
880 info
->insn_type
= dis_dref
;
886 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
888 info
->insn_type
= dis_dref
;
894 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
903 if (signedp
&& immed
>= (1 << (nbits
- 1)))
906 if ((type
== '<' || type
== '>' || type
== '[' || type
== ']')
913 immed
|= ((extend
& 0x1f) << 11) | (extend
& 0x7e0);
914 else if (extbits
== 15)
915 immed
|= ((extend
& 0xf) << 11) | (extend
& 0x7f0);
917 immed
= ((extend
>> 6) & 0x1f) | (extend
& 0x20);
918 immed
&= (1 << extbits
) - 1;
919 if (! extu
&& immed
>= (1 << (extbits
- 1)))
920 immed
-= 1 << extbits
;
924 (*info
->fprintf_func
) (info
->stream
, "%d", immed
);
933 baseaddr
= memaddr
+ 2;
936 baseaddr
= memaddr
- 2;
944 /* If this instruction is in the delay slot of a jr
945 instruction, the base address is the address of the
946 jr instruction. If it is in the delay slot of jalr
947 instruction, the base address is the address of the
948 jalr instruction. This test is unreliable: we have
949 no way of knowing whether the previous word is
950 instruction or data. */
951 status
= (*info
->read_memory_func
) (memaddr
- 4, buffer
, 2,
954 && (((info
->endian
== BFD_ENDIAN_BIG
955 ? bfd_getb16 (buffer
)
956 : bfd_getl16 (buffer
))
957 & 0xf800) == 0x1800))
958 baseaddr
= memaddr
- 4;
961 status
= (*info
->read_memory_func
) (memaddr
- 2, buffer
,
964 && (((info
->endian
== BFD_ENDIAN_BIG
965 ? bfd_getb16 (buffer
)
966 : bfd_getl16 (buffer
))
967 & 0xf81f) == 0xe800))
968 baseaddr
= memaddr
- 2;
971 val
= (baseaddr
& ~ ((1 << shift
) - 1)) + immed
;
972 (*info
->print_address_func
) (val
, info
);
981 l
= ((l
& 0x1f) << 23) | ((l
& 0x3e0) << 13) | (extend
<< 2);
982 (*info
->print_address_func
) ((memaddr
& 0xf0000000) | l
, info
);
983 info
->insn_type
= dis_jsr
;
984 info
->target
= (memaddr
& 0xf0000000) | l
;
985 info
->branch_delay_insns
= 1;
991 int need_comma
, amask
, smask
;
995 l
= (l
>> MIPS16OP_SH_IMM6
) & MIPS16OP_MASK_IMM6
;
997 amask
= (l
>> 3) & 7;
999 if (amask
> 0 && amask
< 5)
1001 (*info
->fprintf_func
) (info
->stream
, "$%s", reg_names
[4]);
1003 (*info
->fprintf_func
) (info
->stream
, "-$%s",
1004 reg_names
[amask
+ 3]);
1008 smask
= (l
>> 1) & 3;
1011 (*info
->fprintf_func
) (info
->stream
, "%s??",
1012 need_comma
? "," : "");
1017 (*info
->fprintf_func
) (info
->stream
, "%s$%s",
1018 need_comma
? "," : "",
1021 (*info
->fprintf_func
) (info
->stream
, "-$%s",
1022 reg_names
[smask
+ 15]);
1028 (*info
->fprintf_func
) (info
->stream
, "%s$%s",
1029 need_comma
? "," : "",
1034 if (amask
== 5 || amask
== 6)
1036 (*info
->fprintf_func
) (info
->stream
, "%s$f0",
1037 need_comma
? "," : "");
1039 (*info
->fprintf_func
) (info
->stream
, "-$f1");