1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "opcode/i386.h"
36 #include "elf/x86-64.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
46 #ifndef SCALE1_WHEN_NO_INDEX
47 /* Specifying a scale factor besides 1 when there is no index is
48 futile. eg. `mov (%ebx,2),%al' does exactly the same as
49 `mov (%ebx),%al'. To slavishly follow what the programmer
50 specified, set SCALE1_WHEN_NO_INDEX to 0. */
51 #define SCALE1_WHEN_NO_INDEX 1
55 #define DEFAULT_ARCH "i386"
60 #define INLINE __inline__
66 static INLINE
unsigned int mode_from_disp_size
PARAMS ((unsigned int));
67 static INLINE
int fits_in_signed_byte
PARAMS ((offsetT
));
68 static INLINE
int fits_in_unsigned_byte
PARAMS ((offsetT
));
69 static INLINE
int fits_in_unsigned_word
PARAMS ((offsetT
));
70 static INLINE
int fits_in_signed_word
PARAMS ((offsetT
));
71 static INLINE
int fits_in_unsigned_long
PARAMS ((offsetT
));
72 static INLINE
int fits_in_signed_long
PARAMS ((offsetT
));
73 static int smallest_imm_type
PARAMS ((offsetT
));
74 static offsetT offset_in_range
PARAMS ((offsetT
, int));
75 static int add_prefix
PARAMS ((unsigned int));
76 static void set_code_flag
PARAMS ((int));
77 static void set_16bit_gcc_code_flag
PARAMS ((int));
78 static void set_intel_syntax
PARAMS ((int));
79 static void set_cpu_arch
PARAMS ((int));
81 static void pe_directive_secrel
PARAMS ((int));
83 static char *output_invalid
PARAMS ((int c
));
84 static int i386_operand
PARAMS ((char *operand_string
));
85 static int i386_intel_operand
PARAMS ((char *operand_string
, int got_a_float
));
86 static const reg_entry
*parse_register
PARAMS ((char *reg_string
,
88 static char *parse_insn
PARAMS ((char *, char *));
89 static char *parse_operands
PARAMS ((char *, const char *));
90 static void swap_operands
PARAMS ((void));
91 static void optimize_imm
PARAMS ((void));
92 static void optimize_disp
PARAMS ((void));
93 static int match_template
PARAMS ((void));
94 static int check_string
PARAMS ((void));
95 static int process_suffix
PARAMS ((void));
96 static int check_byte_reg
PARAMS ((void));
97 static int check_long_reg
PARAMS ((void));
98 static int check_qword_reg
PARAMS ((void));
99 static int check_word_reg
PARAMS ((void));
100 static int finalize_imm
PARAMS ((void));
101 static int process_operands
PARAMS ((void));
102 static const seg_entry
*build_modrm_byte
PARAMS ((void));
103 static void output_insn
PARAMS ((void));
104 static void output_branch
PARAMS ((void));
105 static void output_jump
PARAMS ((void));
106 static void output_interseg_jump
PARAMS ((void));
107 static void output_imm
PARAMS ((fragS
*insn_start_frag
,
108 offsetT insn_start_off
));
109 static void output_disp
PARAMS ((fragS
*insn_start_frag
,
110 offsetT insn_start_off
));
112 static void s_bss
PARAMS ((int));
115 static const char *default_arch
= DEFAULT_ARCH
;
117 /* 'md_assemble ()' gathers together information and puts it into a
124 const reg_entry
*regs
;
129 /* TM holds the template for the insn were currently assembling. */
132 /* SUFFIX holds the instruction mnemonic suffix if given.
133 (e.g. 'l' for 'movl') */
136 /* OPERANDS gives the number of given operands. */
137 unsigned int operands
;
139 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
140 of given register, displacement, memory operands and immediate
142 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
144 /* TYPES [i] is the type (see above #defines) which tells us how to
145 use OP[i] for the corresponding operand. */
146 unsigned int types
[MAX_OPERANDS
];
148 /* Displacement expression, immediate expression, or register for each
150 union i386_op op
[MAX_OPERANDS
];
152 /* Flags for operands. */
153 unsigned int flags
[MAX_OPERANDS
];
154 #define Operand_PCrel 1
156 /* Relocation type for operand */
157 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
159 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
160 the base index byte below. */
161 const reg_entry
*base_reg
;
162 const reg_entry
*index_reg
;
163 unsigned int log2_scale_factor
;
165 /* SEG gives the seg_entries of this insn. They are zero unless
166 explicit segment overrides are given. */
167 const seg_entry
*seg
[2];
169 /* PREFIX holds all the given prefix opcodes (usually null).
170 PREFIXES is the number of prefix opcodes. */
171 unsigned int prefixes
;
172 unsigned char prefix
[MAX_PREFIXES
];
174 /* RM and SIB are the modrm byte and the sib byte where the
175 addressing modes of this insn are encoded. */
182 typedef struct _i386_insn i386_insn
;
184 /* List of chars besides those in app.c:symbol_chars that can start an
185 operand. Used to prevent the scrubber eating vital white-space. */
186 const char extra_symbol_chars
[] = "*%-(["
195 #if (defined (TE_I386AIX) \
196 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
197 && !defined (TE_LINUX) \
198 && !defined (TE_NETWARE) \
199 && !defined (TE_FreeBSD) \
200 && !defined (TE_NetBSD)))
201 /* This array holds the chars that always start a comment. If the
202 pre-processor is disabled, these aren't very useful. */
203 const char comment_chars
[] = "#/";
204 #define PREFIX_SEPARATOR '\\'
206 /* This array holds the chars that only start a comment at the beginning of
207 a line. If the line seems to have the form '# 123 filename'
208 .line and .file directives will appear in the pre-processed output.
209 Note that input_file.c hand checks for '#' at the beginning of the
210 first line of the input file. This is because the compiler outputs
211 #NO_APP at the beginning of its output.
212 Also note that comments started like this one will always work if
213 '/' isn't otherwise defined. */
214 const char line_comment_chars
[] = "#";
217 /* Putting '/' here makes it impossible to use the divide operator.
218 However, we need it for compatibility with SVR4 systems. */
219 const char comment_chars
[] = "#";
220 #define PREFIX_SEPARATOR '/'
222 const char line_comment_chars
[] = "/#";
225 const char line_separator_chars
[] = ";";
227 /* Chars that can be used to separate mant from exp in floating point
229 const char EXP_CHARS
[] = "eE";
231 /* Chars that mean this number is a floating point constant
234 const char FLT_CHARS
[] = "fFdDxX";
236 /* Tables for lexical analysis. */
237 static char mnemonic_chars
[256];
238 static char register_chars
[256];
239 static char operand_chars
[256];
240 static char identifier_chars
[256];
241 static char digit_chars
[256];
243 /* Lexical macros. */
244 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
245 #define is_operand_char(x) (operand_chars[(unsigned char) x])
246 #define is_register_char(x) (register_chars[(unsigned char) x])
247 #define is_space_char(x) ((x) == ' ')
248 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
249 #define is_digit_char(x) (digit_chars[(unsigned char) x])
251 /* All non-digit non-letter characters that may occur in an operand. */
252 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
254 /* md_assemble() always leaves the strings it's passed unaltered. To
255 effect this we maintain a stack of saved characters that we've smashed
256 with '\0's (indicating end of strings for various sub-fields of the
257 assembler instruction). */
258 static char save_stack
[32];
259 static char *save_stack_p
;
260 #define END_STRING_AND_SAVE(s) \
261 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
262 #define RESTORE_END_STRING(s) \
263 do { *(s) = *--save_stack_p; } while (0)
265 /* The instruction we're assembling. */
268 /* Possible templates for current insn. */
269 static const templates
*current_templates
;
271 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
272 static expressionS disp_expressions
[2], im_expressions
[2];
274 /* Current operand we are working on. */
275 static int this_operand
;
277 /* We support four different modes. FLAG_CODE variable is used to distinguish
284 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
286 static enum flag_code flag_code
;
287 static int use_rela_relocations
= 0;
289 /* The names used to print error messages. */
290 static const char *flag_code_names
[] =
297 /* 1 for intel syntax,
299 static int intel_syntax
= 0;
301 /* 1 if register prefix % not required. */
302 static int allow_naked_reg
= 0;
304 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
305 leave, push, and pop instructions so that gcc has the same stack
306 frame as in 32 bit mode. */
307 static char stackop_size
= '\0';
309 /* Non-zero to optimize code alignment. */
310 int optimize_align_code
= 1;
312 /* Non-zero to quieten some warnings. */
313 static int quiet_warnings
= 0;
316 static const char *cpu_arch_name
= NULL
;
317 static const char *cpu_sub_arch_name
= NULL
;
319 /* CPU feature flags. */
320 static unsigned int cpu_arch_flags
= CpuUnknownFlags
| CpuNo64
;
322 /* If set, conditional jumps are not automatically promoted to handle
323 larger than a byte offset. */
324 static unsigned int no_cond_jump_promotion
= 0;
326 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
329 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
330 unsigned int x86_dwarf2_return_column
;
332 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
333 int x86_cie_data_alignment
;
335 /* Interface to relax_segment.
336 There are 3 major relax states for 386 jump insns because the
337 different types of jumps add different sizes to frags when we're
338 figuring out what sort of jump to choose to reach a given label. */
341 #define UNCOND_JUMP 0
343 #define COND_JUMP86 2
348 #define SMALL16 (SMALL | CODE16)
350 #define BIG16 (BIG | CODE16)
354 #define INLINE __inline__
360 #define ENCODE_RELAX_STATE(type, size) \
361 ((relax_substateT) (((type) << 2) | (size)))
362 #define TYPE_FROM_RELAX_STATE(s) \
364 #define DISP_SIZE_FROM_RELAX_STATE(s) \
365 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
367 /* This table is used by relax_frag to promote short jumps to long
368 ones where necessary. SMALL (short) jumps may be promoted to BIG
369 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
370 don't allow a short jump in a 32 bit code segment to be promoted to
371 a 16 bit offset jump because it's slower (requires data size
372 prefix), and doesn't work, unless the destination is in the bottom
373 64k of the code segment (The top 16 bits of eip are zeroed). */
375 const relax_typeS md_relax_table
[] =
378 1) most positive reach of this state,
379 2) most negative reach of this state,
380 3) how many bytes this mode will have in the variable part of the frag
381 4) which index into the table to try if we can't fit into this one. */
383 /* UNCOND_JUMP states. */
384 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
385 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
386 /* dword jmp adds 4 bytes to frag:
387 0 extra opcode bytes, 4 displacement bytes. */
389 /* word jmp adds 2 byte2 to frag:
390 0 extra opcode bytes, 2 displacement bytes. */
393 /* COND_JUMP states. */
394 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
395 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
396 /* dword conditionals adds 5 bytes to frag:
397 1 extra opcode byte, 4 displacement bytes. */
399 /* word conditionals add 3 bytes to frag:
400 1 extra opcode byte, 2 displacement bytes. */
403 /* COND_JUMP86 states. */
404 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
405 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
406 /* dword conditionals adds 5 bytes to frag:
407 1 extra opcode byte, 4 displacement bytes. */
409 /* word conditionals add 4 bytes to frag:
410 1 displacement byte and a 3 byte long branch insn. */
414 static const arch_entry cpu_arch
[] = {
416 {"i186", Cpu086
|Cpu186
},
417 {"i286", Cpu086
|Cpu186
|Cpu286
},
418 {"i386", Cpu086
|Cpu186
|Cpu286
|Cpu386
},
419 {"i486", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
},
420 {"i586", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
},
421 {"i686", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
},
422 {"pentium", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
},
423 {"pentiumpro",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
},
424 {"pentiumii", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
},
425 {"pentiumiii",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuMMX2
|CpuSSE
},
426 {"pentium4", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
},
427 {"prescott", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
|CpuPNI
},
428 {"k6", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
},
429 {"k6_2", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
|Cpu3dnow
},
430 {"athlon", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
},
431 {"sledgehammer",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuSledgehammer
|CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
|CpuSSE
|CpuSSE2
},
433 {".sse", CpuMMX
|CpuMMX2
|CpuSSE
},
434 {".sse2", CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
},
435 {".3dnow", CpuMMX
|Cpu3dnow
},
436 {".3dnowa", CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
},
437 {".padlock", CpuPadLock
},
441 const pseudo_typeS md_pseudo_table
[] =
443 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
444 {"align", s_align_bytes
, 0},
446 {"align", s_align_ptwo
, 0},
448 {"arch", set_cpu_arch
, 0},
452 {"ffloat", float_cons
, 'f'},
453 {"dfloat", float_cons
, 'd'},
454 {"tfloat", float_cons
, 'x'},
456 {"noopt", s_ignore
, 0},
457 {"optim", s_ignore
, 0},
458 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
459 {"code16", set_code_flag
, CODE_16BIT
},
460 {"code32", set_code_flag
, CODE_32BIT
},
461 {"code64", set_code_flag
, CODE_64BIT
},
462 {"intel_syntax", set_intel_syntax
, 1},
463 {"att_syntax", set_intel_syntax
, 0},
464 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file
, 0},
465 {"loc", dwarf2_directive_loc
, 0},
467 {"secrel32", pe_directive_secrel
, 0},
472 /* For interface with expression (). */
473 extern char *input_line_pointer
;
475 /* Hash table for instruction mnemonic lookup. */
476 static struct hash_control
*op_hash
;
478 /* Hash table for register lookup. */
479 static struct hash_control
*reg_hash
;
482 i386_align_code (fragP
, count
)
486 /* Various efficient no-op patterns for aligning code labels.
487 Note: Don't try to assemble the instructions in the comments.
488 0L and 0w are not legal. */
489 static const char f32_1
[] =
491 static const char f32_2
[] =
492 {0x89,0xf6}; /* movl %esi,%esi */
493 static const char f32_3
[] =
494 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
495 static const char f32_4
[] =
496 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
497 static const char f32_5
[] =
499 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
500 static const char f32_6
[] =
501 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
502 static const char f32_7
[] =
503 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
504 static const char f32_8
[] =
506 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
507 static const char f32_9
[] =
508 {0x89,0xf6, /* movl %esi,%esi */
509 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
510 static const char f32_10
[] =
511 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
512 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
513 static const char f32_11
[] =
514 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
515 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
516 static const char f32_12
[] =
517 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
518 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
519 static const char f32_13
[] =
520 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
521 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
522 static const char f32_14
[] =
523 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
524 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
525 static const char f32_15
[] =
526 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
527 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
528 static const char f16_3
[] =
529 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
530 static const char f16_4
[] =
531 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
532 static const char f16_5
[] =
534 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
535 static const char f16_6
[] =
536 {0x89,0xf6, /* mov %si,%si */
537 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
538 static const char f16_7
[] =
539 {0x8d,0x74,0x00, /* lea 0(%si),%si */
540 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
541 static const char f16_8
[] =
542 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
543 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
544 static const char *const f32_patt
[] = {
545 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
546 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
, f32_15
548 static const char *const f16_patt
[] = {
549 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
,
550 f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
553 if (count
<= 0 || count
> 15)
556 /* The recommended way to pad 64bit code is to use NOPs preceded by
557 maximally four 0x66 prefixes. Balance the size of nops. */
558 if (flag_code
== CODE_64BIT
)
561 int nnops
= (count
+ 3) / 4;
562 int len
= count
/ nnops
;
563 int remains
= count
- nnops
* len
;
566 for (i
= 0; i
< remains
; i
++)
568 memset (fragP
->fr_literal
+ fragP
->fr_fix
+ pos
, 0x66, len
);
569 fragP
->fr_literal
[fragP
->fr_fix
+ pos
+ len
] = 0x90;
572 for (; i
< nnops
; i
++)
574 memset (fragP
->fr_literal
+ fragP
->fr_fix
+ pos
, 0x66, len
- 1);
575 fragP
->fr_literal
[fragP
->fr_fix
+ pos
+ len
- 1] = 0x90;
580 if (flag_code
== CODE_16BIT
)
582 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
583 f16_patt
[count
- 1], count
);
585 /* Adjust jump offset. */
586 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
589 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
590 f32_patt
[count
- 1], count
);
591 fragP
->fr_var
= count
;
594 static INLINE
unsigned int
595 mode_from_disp_size (t
)
598 return (t
& Disp8
) ? 1 : (t
& (Disp16
| Disp32
| Disp32S
)) ? 2 : 0;
602 fits_in_signed_byte (num
)
605 return (num
>= -128) && (num
<= 127);
609 fits_in_unsigned_byte (num
)
612 return (num
& 0xff) == num
;
616 fits_in_unsigned_word (num
)
619 return (num
& 0xffff) == num
;
623 fits_in_signed_word (num
)
626 return (-32768 <= num
) && (num
<= 32767);
629 fits_in_signed_long (num
)
630 offsetT num ATTRIBUTE_UNUSED
;
635 return (!(((offsetT
) -1 << 31) & num
)
636 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
638 } /* fits_in_signed_long() */
640 fits_in_unsigned_long (num
)
641 offsetT num ATTRIBUTE_UNUSED
;
646 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
648 } /* fits_in_unsigned_long() */
651 smallest_imm_type (num
)
654 if (cpu_arch_flags
!= (Cpu086
| Cpu186
| Cpu286
| Cpu386
| Cpu486
| CpuNo64
))
656 /* This code is disabled on the 486 because all the Imm1 forms
657 in the opcode table are slower on the i486. They're the
658 versions with the implicitly specified single-position
659 displacement, which has another syntax if you really want to
662 return Imm1
| Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
;
664 return (fits_in_signed_byte (num
)
665 ? (Imm8S
| Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
666 : fits_in_unsigned_byte (num
)
667 ? (Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
668 : (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
669 ? (Imm16
| Imm32
| Imm32S
| Imm64
)
670 : fits_in_signed_long (num
)
671 ? (Imm32
| Imm32S
| Imm64
)
672 : fits_in_unsigned_long (num
)
678 offset_in_range (val
, size
)
686 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
687 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
688 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
690 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
695 /* If BFD64, sign extend val. */
696 if (!use_rela_relocations
)
697 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
698 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
700 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
702 char buf1
[40], buf2
[40];
704 sprint_value (buf1
, val
);
705 sprint_value (buf2
, val
& mask
);
706 as_warn (_("%s shortened to %s"), buf1
, buf2
);
711 /* Returns 0 if attempting to add a prefix where one from the same
712 class already exists, 1 if non rep/repne added, 2 if rep/repne
721 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
722 && flag_code
== CODE_64BIT
)
730 case CS_PREFIX_OPCODE
:
731 case DS_PREFIX_OPCODE
:
732 case ES_PREFIX_OPCODE
:
733 case FS_PREFIX_OPCODE
:
734 case GS_PREFIX_OPCODE
:
735 case SS_PREFIX_OPCODE
:
739 case REPNE_PREFIX_OPCODE
:
740 case REPE_PREFIX_OPCODE
:
743 case LOCK_PREFIX_OPCODE
:
751 case ADDR_PREFIX_OPCODE
:
755 case DATA_PREFIX_OPCODE
:
760 if (i
.prefix
[q
] != 0)
762 as_bad (_("same type of prefix used twice"));
767 i
.prefix
[q
] = prefix
;
772 set_code_flag (value
)
776 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
777 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
778 if (value
== CODE_64BIT
&& !(cpu_arch_flags
& CpuSledgehammer
))
780 as_bad (_("64bit mode not supported on this CPU."));
782 if (value
== CODE_32BIT
&& !(cpu_arch_flags
& Cpu386
))
784 as_bad (_("32bit mode not supported on this CPU."));
790 set_16bit_gcc_code_flag (new_code_flag
)
793 flag_code
= new_code_flag
;
794 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
795 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
796 stackop_size
= LONG_MNEM_SUFFIX
;
800 set_intel_syntax (syntax_flag
)
803 /* Find out if register prefixing is specified. */
804 int ask_naked_reg
= 0;
807 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
809 char *string
= input_line_pointer
;
810 int e
= get_symbol_end ();
812 if (strcmp (string
, "prefix") == 0)
814 else if (strcmp (string
, "noprefix") == 0)
817 as_bad (_("bad argument to syntax directive."));
818 *input_line_pointer
= e
;
820 demand_empty_rest_of_line ();
822 intel_syntax
= syntax_flag
;
824 if (ask_naked_reg
== 0)
825 allow_naked_reg
= (intel_syntax
826 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
828 allow_naked_reg
= (ask_naked_reg
< 0);
830 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
831 identifier_chars
['$'] = intel_syntax
? '$' : 0;
836 int dummy ATTRIBUTE_UNUSED
;
840 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
842 char *string
= input_line_pointer
;
843 int e
= get_symbol_end ();
846 for (i
= 0; cpu_arch
[i
].name
; i
++)
848 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
852 cpu_arch_name
= cpu_arch
[i
].name
;
853 cpu_sub_arch_name
= NULL
;
854 cpu_arch_flags
= (cpu_arch
[i
].flags
855 | (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
));
858 if ((cpu_arch_flags
| cpu_arch
[i
].flags
) != cpu_arch_flags
)
860 cpu_sub_arch_name
= cpu_arch
[i
].name
;
861 cpu_arch_flags
|= cpu_arch
[i
].flags
;
863 *input_line_pointer
= e
;
864 demand_empty_rest_of_line ();
868 if (!cpu_arch
[i
].name
)
869 as_bad (_("no such architecture: `%s'"), string
);
871 *input_line_pointer
= e
;
874 as_bad (_("missing cpu architecture"));
876 no_cond_jump_promotion
= 0;
877 if (*input_line_pointer
== ','
878 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
880 char *string
= ++input_line_pointer
;
881 int e
= get_symbol_end ();
883 if (strcmp (string
, "nojumps") == 0)
884 no_cond_jump_promotion
= 1;
885 else if (strcmp (string
, "jumps") == 0)
888 as_bad (_("no such architecture modifier: `%s'"), string
);
890 *input_line_pointer
= e
;
893 demand_empty_rest_of_line ();
899 if (!strcmp (default_arch
, "x86_64"))
900 return bfd_mach_x86_64
;
901 else if (!strcmp (default_arch
, "i386"))
902 return bfd_mach_i386_i386
;
904 as_fatal (_("Unknown architecture"));
910 const char *hash_err
;
912 /* Initialize op_hash hash table. */
913 op_hash
= hash_new ();
916 const template *optab
;
917 templates
*core_optab
;
919 /* Setup for loop. */
921 core_optab
= (templates
*) xmalloc (sizeof (templates
));
922 core_optab
->start
= optab
;
927 if (optab
->name
== NULL
928 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
930 /* different name --> ship out current template list;
931 add to hash table; & begin anew. */
932 core_optab
->end
= optab
;
933 hash_err
= hash_insert (op_hash
,
938 as_fatal (_("Internal Error: Can't hash %s: %s"),
942 if (optab
->name
== NULL
)
944 core_optab
= (templates
*) xmalloc (sizeof (templates
));
945 core_optab
->start
= optab
;
950 /* Initialize reg_hash hash table. */
951 reg_hash
= hash_new ();
953 const reg_entry
*regtab
;
955 for (regtab
= i386_regtab
;
956 regtab
< i386_regtab
+ sizeof (i386_regtab
) / sizeof (i386_regtab
[0]);
959 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
961 as_fatal (_("Internal Error: Can't hash %s: %s"),
967 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
972 for (c
= 0; c
< 256; c
++)
977 mnemonic_chars
[c
] = c
;
978 register_chars
[c
] = c
;
979 operand_chars
[c
] = c
;
981 else if (ISLOWER (c
))
983 mnemonic_chars
[c
] = c
;
984 register_chars
[c
] = c
;
985 operand_chars
[c
] = c
;
987 else if (ISUPPER (c
))
989 mnemonic_chars
[c
] = TOLOWER (c
);
990 register_chars
[c
] = mnemonic_chars
[c
];
991 operand_chars
[c
] = c
;
994 if (ISALPHA (c
) || ISDIGIT (c
))
995 identifier_chars
[c
] = c
;
998 identifier_chars
[c
] = c
;
999 operand_chars
[c
] = c
;
1004 identifier_chars
['@'] = '@';
1007 identifier_chars
['?'] = '?';
1008 operand_chars
['?'] = '?';
1010 digit_chars
['-'] = '-';
1011 identifier_chars
['_'] = '_';
1012 identifier_chars
['.'] = '.';
1014 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
1015 operand_chars
[(unsigned char) *p
] = *p
;
1018 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1019 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1021 record_alignment (text_section
, 2);
1022 record_alignment (data_section
, 2);
1023 record_alignment (bss_section
, 2);
1027 if (flag_code
== CODE_64BIT
)
1029 x86_dwarf2_return_column
= 16;
1030 x86_cie_data_alignment
= -8;
1034 x86_dwarf2_return_column
= 8;
1035 x86_cie_data_alignment
= -4;
1040 i386_print_statistics (file
)
1043 hash_print_statistics (file
, "i386 opcode", op_hash
);
1044 hash_print_statistics (file
, "i386 register", reg_hash
);
1049 /* Debugging routines for md_assemble. */
1050 static void pi
PARAMS ((char *, i386_insn
*));
1051 static void pte
PARAMS ((template *));
1052 static void pt
PARAMS ((unsigned int));
1053 static void pe
PARAMS ((expressionS
*));
1054 static void ps
PARAMS ((symbolS
*));
1063 fprintf (stdout
, "%s: template ", line
);
1065 fprintf (stdout
, " address: base %s index %s scale %x\n",
1066 x
->base_reg
? x
->base_reg
->reg_name
: "none",
1067 x
->index_reg
? x
->index_reg
->reg_name
: "none",
1068 x
->log2_scale_factor
);
1069 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
1070 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
1071 fprintf (stdout
, " sib: base %x index %x scale %x\n",
1072 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
1073 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
1074 (x
->rex
& REX_MODE64
) != 0,
1075 (x
->rex
& REX_EXTX
) != 0,
1076 (x
->rex
& REX_EXTY
) != 0,
1077 (x
->rex
& REX_EXTZ
) != 0);
1078 for (i
= 0; i
< x
->operands
; i
++)
1080 fprintf (stdout
, " #%d: ", i
+ 1);
1082 fprintf (stdout
, "\n");
1084 & (Reg
| SReg2
| SReg3
| Control
| Debug
| Test
| RegMMX
| RegXMM
))
1085 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
1086 if (x
->types
[i
] & Imm
)
1088 if (x
->types
[i
] & Disp
)
1089 pe (x
->op
[i
].disps
);
1098 fprintf (stdout
, " %d operands ", t
->operands
);
1099 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
1100 if (t
->extension_opcode
!= None
)
1101 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
1102 if (t
->opcode_modifier
& D
)
1103 fprintf (stdout
, "D");
1104 if (t
->opcode_modifier
& W
)
1105 fprintf (stdout
, "W");
1106 fprintf (stdout
, "\n");
1107 for (i
= 0; i
< t
->operands
; i
++)
1109 fprintf (stdout
, " #%d type ", i
+ 1);
1110 pt (t
->operand_types
[i
]);
1111 fprintf (stdout
, "\n");
1119 fprintf (stdout
, " operation %d\n", e
->X_op
);
1120 fprintf (stdout
, " add_number %ld (%lx)\n",
1121 (long) e
->X_add_number
, (long) e
->X_add_number
);
1122 if (e
->X_add_symbol
)
1124 fprintf (stdout
, " add_symbol ");
1125 ps (e
->X_add_symbol
);
1126 fprintf (stdout
, "\n");
1130 fprintf (stdout
, " op_symbol ");
1131 ps (e
->X_op_symbol
);
1132 fprintf (stdout
, "\n");
1140 fprintf (stdout
, "%s type %s%s",
1142 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
1143 segment_name (S_GET_SEGMENT (s
)));
1152 static const type_names
[] =
1165 { BaseIndex
, "BaseIndex" },
1169 { Disp32S
, "d32s" },
1171 { InOutPortReg
, "InOutPortReg" },
1172 { ShiftCount
, "ShiftCount" },
1173 { Control
, "control reg" },
1174 { Test
, "test reg" },
1175 { Debug
, "debug reg" },
1176 { FloatReg
, "FReg" },
1177 { FloatAcc
, "FAcc" },
1181 { JumpAbsolute
, "Jump Absolute" },
1192 const struct type_name
*ty
;
1194 for (ty
= type_names
; ty
->mask
; ty
++)
1196 fprintf (stdout
, "%s, ", ty
->tname
);
1200 #endif /* DEBUG386 */
1202 static bfd_reloc_code_real_type reloc
1203 PARAMS ((int, int, int, bfd_reloc_code_real_type
));
1205 static bfd_reloc_code_real_type
1206 reloc (size
, pcrel
, sign
, other
)
1210 bfd_reloc_code_real_type other
;
1212 if (other
!= NO_RELOC
)
1218 as_bad (_("There are no unsigned pc-relative relocations"));
1221 case 1: return BFD_RELOC_8_PCREL
;
1222 case 2: return BFD_RELOC_16_PCREL
;
1223 case 4: return BFD_RELOC_32_PCREL
;
1225 as_bad (_("can not do %d byte pc-relative relocation"), size
);
1232 case 4: return BFD_RELOC_X86_64_32S
;
1237 case 1: return BFD_RELOC_8
;
1238 case 2: return BFD_RELOC_16
;
1239 case 4: return BFD_RELOC_32
;
1240 case 8: return BFD_RELOC_64
;
1242 as_bad (_("can not do %s %d byte relocation"),
1243 sign
? "signed" : "unsigned", size
);
1247 return BFD_RELOC_NONE
;
1250 /* Here we decide which fixups can be adjusted to make them relative to
1251 the beginning of the section instead of the symbol. Basically we need
1252 to make sure that the dynamic relocations are done correctly, so in
1253 some cases we force the original symbol to be used. */
1256 tc_i386_fix_adjustable (fixP
)
1257 fixS
*fixP ATTRIBUTE_UNUSED
;
1259 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1260 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
1263 /* Don't adjust pc-relative references to merge sections in 64-bit
1265 if (use_rela_relocations
1266 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
1270 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1271 and changed later by validate_fix. */
1272 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
1273 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
1276 /* adjust_reloc_syms doesn't know about the GOT. */
1277 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
1278 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
1279 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
1280 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
1281 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
1282 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
1283 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
1284 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
1285 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
1286 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
1287 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
1288 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
1289 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
1290 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
1291 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
1292 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
1293 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
1294 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
1295 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
1296 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1297 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1303 static int intel_float_operand
PARAMS ((const char *mnemonic
));
1306 intel_float_operand (mnemonic
)
1307 const char *mnemonic
;
1309 /* Note that the value returned is meaningful only for opcodes with (memory)
1310 operands, hence the code here is free to improperly handle opcodes that
1311 have no operands (for better performance and smaller code). */
1313 if (mnemonic
[0] != 'f')
1314 return 0; /* non-math */
1316 switch (mnemonic
[1])
1318 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1319 the fs segment override prefix not currently handled because no
1320 call path can make opcodes without operands get here */
1322 return 2 /* integer op */;
1324 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
1325 return 3; /* fldcw/fldenv */
1328 if (mnemonic
[2] != 'o' /* fnop */)
1329 return 3; /* non-waiting control op */
1332 if (mnemonic
[2] == 's')
1333 return 3; /* frstor/frstpm */
1336 if (mnemonic
[2] == 'a')
1337 return 3; /* fsave */
1338 if (mnemonic
[2] == 't')
1340 switch (mnemonic
[3])
1342 case 'c': /* fstcw */
1343 case 'd': /* fstdw */
1344 case 'e': /* fstenv */
1345 case 's': /* fsts[gw] */
1351 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
1352 return 0; /* fxsave/fxrstor are not really math ops */
1359 /* This is the guts of the machine-dependent assembler. LINE points to a
1360 machine dependent instruction. This function is supposed to emit
1361 the frags/bytes it assembles to. */
1368 char mnemonic
[MAX_MNEM_SIZE
];
1370 /* Initialize globals. */
1371 memset (&i
, '\0', sizeof (i
));
1372 for (j
= 0; j
< MAX_OPERANDS
; j
++)
1373 i
.reloc
[j
] = NO_RELOC
;
1374 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
1375 memset (im_expressions
, '\0', sizeof (im_expressions
));
1376 save_stack_p
= save_stack
;
1378 /* First parse an instruction mnemonic & call i386_operand for the operands.
1379 We assume that the scrubber has arranged it so that line[0] is the valid
1380 start of a (possibly prefixed) mnemonic. */
1382 line
= parse_insn (line
, mnemonic
);
1386 line
= parse_operands (line
, mnemonic
);
1390 /* Now we've parsed the mnemonic into a set of templates, and have the
1391 operands at hand. */
1393 /* All intel opcodes have reversed operands except for "bound" and
1394 "enter". We also don't reverse intersegment "jmp" and "call"
1395 instructions with 2 immediate operands so that the immediate segment
1396 precedes the offset, as it does when in AT&T mode. "enter" and the
1397 intersegment "jmp" and "call" instructions are the only ones that
1398 have two immediate operands. */
1399 if (intel_syntax
&& i
.operands
> 1
1400 && (strcmp (mnemonic
, "bound") != 0)
1401 && !((i
.types
[0] & Imm
) && (i
.types
[1] & Imm
)))
1407 if (i
.disp_operands
)
1410 /* Next, we find a template that matches the given insn,
1411 making sure the overlap of the given operands types is consistent
1412 with the template operand types. */
1414 if (!match_template ())
1419 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1421 && (i
.tm
.base_opcode
& 0xfffffde0) == 0xdce0)
1422 i
.tm
.base_opcode
^= FloatR
;
1424 /* Zap movzx and movsx suffix. The suffix may have been set from
1425 "word ptr" or "byte ptr" on the source operand, but we'll use
1426 the suffix later to choose the destination register. */
1427 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
1429 if (i
.reg_operands
< 2
1431 && (~i
.tm
.opcode_modifier
1438 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
1444 if (i
.tm
.opcode_modifier
& FWait
)
1445 if (!add_prefix (FWAIT_OPCODE
))
1448 /* Check string instruction segment overrides. */
1449 if ((i
.tm
.opcode_modifier
& IsString
) != 0 && i
.mem_operands
!= 0)
1451 if (!check_string ())
1455 if (!process_suffix ())
1458 /* Make still unresolved immediate matches conform to size of immediate
1459 given in i.suffix. */
1460 if (!finalize_imm ())
1463 if (i
.types
[0] & Imm1
)
1464 i
.imm_operands
= 0; /* kludge for shift insns. */
1465 if (i
.types
[0] & ImplicitRegister
)
1467 if (i
.types
[1] & ImplicitRegister
)
1469 if (i
.types
[2] & ImplicitRegister
)
1472 if (i
.tm
.opcode_modifier
& ImmExt
)
1476 if ((i
.tm
.cpu_flags
& CpuPNI
) && i
.operands
> 0)
1478 /* These Intel Prescott New Instructions have the fixed
1479 operands with an opcode suffix which is coded in the same
1480 place as an 8-bit immediate field would be. Here we check
1481 those operands and remove them afterwards. */
1484 for (x
= 0; x
< i
.operands
; x
++)
1485 if (i
.op
[x
].regs
->reg_num
!= x
)
1486 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
1487 i
.op
[x
].regs
->reg_name
, x
+ 1, i
.tm
.name
);
1491 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1492 opcode suffix which is coded in the same place as an 8-bit
1493 immediate field would be. Here we fake an 8-bit immediate
1494 operand from the opcode suffix stored in tm.extension_opcode. */
1496 assert (i
.imm_operands
== 0 && i
.operands
<= 2 && 2 < MAX_OPERANDS
);
1498 exp
= &im_expressions
[i
.imm_operands
++];
1499 i
.op
[i
.operands
].imms
= exp
;
1500 i
.types
[i
.operands
++] = Imm8
;
1501 exp
->X_op
= O_constant
;
1502 exp
->X_add_number
= i
.tm
.extension_opcode
;
1503 i
.tm
.extension_opcode
= None
;
1506 /* For insns with operands there are more diddles to do to the opcode. */
1509 if (!process_operands ())
1512 else if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
1514 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1515 as_warn (_("translating to `%sp'"), i
.tm
.name
);
1518 /* Handle conversion of 'int $3' --> special int3 insn. */
1519 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
1521 i
.tm
.base_opcode
= INT3_OPCODE
;
1525 if ((i
.tm
.opcode_modifier
& (Jump
| JumpByte
| JumpDword
))
1526 && i
.op
[0].disps
->X_op
== O_constant
)
1528 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1529 the absolute address given by the constant. Since ix86 jumps and
1530 calls are pc relative, we need to generate a reloc. */
1531 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
1532 i
.op
[0].disps
->X_op
= O_symbol
;
1535 if ((i
.tm
.opcode_modifier
& Rex64
) != 0)
1536 i
.rex
|= REX_MODE64
;
1538 /* For 8 bit registers we need an empty rex prefix. Also if the
1539 instruction already has a prefix, we need to convert old
1540 registers to new ones. */
1542 if (((i
.types
[0] & Reg8
) != 0
1543 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
1544 || ((i
.types
[1] & Reg8
) != 0
1545 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
1546 || (((i
.types
[0] & Reg8
) != 0 || (i
.types
[1] & Reg8
) != 0)
1551 i
.rex
|= REX_OPCODE
;
1552 for (x
= 0; x
< 2; x
++)
1554 /* Look for 8 bit operand that uses old registers. */
1555 if ((i
.types
[x
] & Reg8
) != 0
1556 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
1558 /* In case it is "hi" register, give up. */
1559 if (i
.op
[x
].regs
->reg_num
> 3)
1560 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix."),
1561 i
.op
[x
].regs
->reg_name
);
1563 /* Otherwise it is equivalent to the extended register.
1564 Since the encoding doesn't change this is merely
1565 cosmetic cleanup for debug output. */
1567 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
1573 add_prefix (REX_OPCODE
| i
.rex
);
1575 /* We are ready to output the insn. */
1580 parse_insn (line
, mnemonic
)
1585 char *token_start
= l
;
1590 /* Non-zero if we found a prefix only acceptable with string insns. */
1591 const char *expecting_string_instruction
= NULL
;
1596 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
1599 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
1601 as_bad (_("no such instruction: `%s'"), token_start
);
1606 if (!is_space_char (*l
)
1607 && *l
!= END_OF_INSN
1608 && *l
!= PREFIX_SEPARATOR
1611 as_bad (_("invalid character %s in mnemonic"),
1612 output_invalid (*l
));
1615 if (token_start
== l
)
1617 if (*l
== PREFIX_SEPARATOR
)
1618 as_bad (_("expecting prefix; got nothing"));
1620 as_bad (_("expecting mnemonic; got nothing"));
1624 /* Look up instruction (or prefix) via hash table. */
1625 current_templates
= hash_find (op_hash
, mnemonic
);
1627 if (*l
!= END_OF_INSN
1628 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
1629 && current_templates
1630 && (current_templates
->start
->opcode_modifier
& IsPrefix
))
1632 /* If we are in 16-bit mode, do not allow addr16 or data16.
1633 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1634 if ((current_templates
->start
->opcode_modifier
& (Size16
| Size32
))
1635 && flag_code
!= CODE_64BIT
1636 && (((current_templates
->start
->opcode_modifier
& Size32
) != 0)
1637 ^ (flag_code
== CODE_16BIT
)))
1639 as_bad (_("redundant %s prefix"),
1640 current_templates
->start
->name
);
1643 /* Add prefix, checking for repeated prefixes. */
1644 switch (add_prefix (current_templates
->start
->base_opcode
))
1649 expecting_string_instruction
= current_templates
->start
->name
;
1652 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1659 if (!current_templates
)
1661 /* See if we can get a match by trimming off a suffix. */
1664 case WORD_MNEM_SUFFIX
:
1665 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
1666 i
.suffix
= SHORT_MNEM_SUFFIX
;
1668 case BYTE_MNEM_SUFFIX
:
1669 case QWORD_MNEM_SUFFIX
:
1670 i
.suffix
= mnem_p
[-1];
1672 current_templates
= hash_find (op_hash
, mnemonic
);
1674 case SHORT_MNEM_SUFFIX
:
1675 case LONG_MNEM_SUFFIX
:
1678 i
.suffix
= mnem_p
[-1];
1680 current_templates
= hash_find (op_hash
, mnemonic
);
1688 if (intel_float_operand (mnemonic
) == 1)
1689 i
.suffix
= SHORT_MNEM_SUFFIX
;
1691 i
.suffix
= LONG_MNEM_SUFFIX
;
1693 current_templates
= hash_find (op_hash
, mnemonic
);
1697 if (!current_templates
)
1699 as_bad (_("no such instruction: `%s'"), token_start
);
1704 if (current_templates
->start
->opcode_modifier
& (Jump
| JumpByte
))
1706 /* Check for a branch hint. We allow ",pt" and ",pn" for
1707 predict taken and predict not taken respectively.
1708 I'm not sure that branch hints actually do anything on loop
1709 and jcxz insns (JumpByte) for current Pentium4 chips. They
1710 may work in the future and it doesn't hurt to accept them
1712 if (l
[0] == ',' && l
[1] == 'p')
1716 if (!add_prefix (DS_PREFIX_OPCODE
))
1720 else if (l
[2] == 'n')
1722 if (!add_prefix (CS_PREFIX_OPCODE
))
1728 /* Any other comma loses. */
1731 as_bad (_("invalid character %s in mnemonic"),
1732 output_invalid (*l
));
1736 /* Check if instruction is supported on specified architecture. */
1738 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
1740 if (!((t
->cpu_flags
& ~(Cpu64
| CpuNo64
))
1741 & ~(cpu_arch_flags
& ~(Cpu64
| CpuNo64
))))
1743 if (!(t
->cpu_flags
& (flag_code
== CODE_64BIT
? CpuNo64
: Cpu64
)))
1746 if (!(supported
& 2))
1748 as_bad (flag_code
== CODE_64BIT
1749 ? _("`%s' is not supported in 64-bit mode")
1750 : _("`%s' is only supported in 64-bit mode"),
1751 current_templates
->start
->name
);
1754 if (!(supported
& 1))
1756 as_warn (_("`%s' is not supported on `%s%s'"),
1757 current_templates
->start
->name
,
1759 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
1761 else if ((Cpu386
& ~cpu_arch_flags
) && (flag_code
!= CODE_16BIT
))
1763 as_warn (_("use .code16 to ensure correct addressing mode"));
1766 /* Check for rep/repne without a string instruction. */
1767 if (expecting_string_instruction
1768 && !(current_templates
->start
->opcode_modifier
& IsString
))
1770 as_bad (_("expecting string instruction after `%s'"),
1771 expecting_string_instruction
);
1779 parse_operands (l
, mnemonic
)
1781 const char *mnemonic
;
1785 /* 1 if operand is pending after ','. */
1786 unsigned int expecting_operand
= 0;
1788 /* Non-zero if operand parens not balanced. */
1789 unsigned int paren_not_balanced
;
1791 while (*l
!= END_OF_INSN
)
1793 /* Skip optional white space before operand. */
1794 if (is_space_char (*l
))
1796 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
1798 as_bad (_("invalid character %s before operand %d"),
1799 output_invalid (*l
),
1803 token_start
= l
; /* after white space */
1804 paren_not_balanced
= 0;
1805 while (paren_not_balanced
|| *l
!= ',')
1807 if (*l
== END_OF_INSN
)
1809 if (paren_not_balanced
)
1812 as_bad (_("unbalanced parenthesis in operand %d."),
1815 as_bad (_("unbalanced brackets in operand %d."),
1820 break; /* we are done */
1822 else if (!is_operand_char (*l
) && !is_space_char (*l
))
1824 as_bad (_("invalid character %s in operand %d"),
1825 output_invalid (*l
),
1832 ++paren_not_balanced
;
1834 --paren_not_balanced
;
1839 ++paren_not_balanced
;
1841 --paren_not_balanced
;
1845 if (l
!= token_start
)
1846 { /* Yes, we've read in another operand. */
1847 unsigned int operand_ok
;
1848 this_operand
= i
.operands
++;
1849 if (i
.operands
> MAX_OPERANDS
)
1851 as_bad (_("spurious operands; (%d operands/instruction max)"),
1855 /* Now parse operand adding info to 'i' as we go along. */
1856 END_STRING_AND_SAVE (l
);
1860 i386_intel_operand (token_start
,
1861 intel_float_operand (mnemonic
));
1863 operand_ok
= i386_operand (token_start
);
1865 RESTORE_END_STRING (l
);
1871 if (expecting_operand
)
1873 expecting_operand_after_comma
:
1874 as_bad (_("expecting operand after ','; got nothing"));
1879 as_bad (_("expecting operand before ','; got nothing"));
1884 /* Now *l must be either ',' or END_OF_INSN. */
1887 if (*++l
== END_OF_INSN
)
1889 /* Just skip it, if it's \n complain. */
1890 goto expecting_operand_after_comma
;
1892 expecting_operand
= 1;
1901 union i386_op temp_op
;
1902 unsigned int temp_type
;
1903 enum bfd_reloc_code_real temp_reloc
;
1907 if (i
.operands
== 2)
1912 else if (i
.operands
== 3)
1917 temp_type
= i
.types
[xchg2
];
1918 i
.types
[xchg2
] = i
.types
[xchg1
];
1919 i
.types
[xchg1
] = temp_type
;
1920 temp_op
= i
.op
[xchg2
];
1921 i
.op
[xchg2
] = i
.op
[xchg1
];
1922 i
.op
[xchg1
] = temp_op
;
1923 temp_reloc
= i
.reloc
[xchg2
];
1924 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
1925 i
.reloc
[xchg1
] = temp_reloc
;
1927 if (i
.mem_operands
== 2)
1929 const seg_entry
*temp_seg
;
1930 temp_seg
= i
.seg
[0];
1931 i
.seg
[0] = i
.seg
[1];
1932 i
.seg
[1] = temp_seg
;
1936 /* Try to ensure constant immediates are represented in the smallest
1941 char guess_suffix
= 0;
1945 guess_suffix
= i
.suffix
;
1946 else if (i
.reg_operands
)
1948 /* Figure out a suffix from the last register operand specified.
1949 We can't do this properly yet, ie. excluding InOutPortReg,
1950 but the following works for instructions with immediates.
1951 In any case, we can't set i.suffix yet. */
1952 for (op
= i
.operands
; --op
>= 0;)
1953 if (i
.types
[op
] & Reg
)
1955 if (i
.types
[op
] & Reg8
)
1956 guess_suffix
= BYTE_MNEM_SUFFIX
;
1957 else if (i
.types
[op
] & Reg16
)
1958 guess_suffix
= WORD_MNEM_SUFFIX
;
1959 else if (i
.types
[op
] & Reg32
)
1960 guess_suffix
= LONG_MNEM_SUFFIX
;
1961 else if (i
.types
[op
] & Reg64
)
1962 guess_suffix
= QWORD_MNEM_SUFFIX
;
1966 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
1967 guess_suffix
= WORD_MNEM_SUFFIX
;
1969 for (op
= i
.operands
; --op
>= 0;)
1970 if (i
.types
[op
] & Imm
)
1972 switch (i
.op
[op
].imms
->X_op
)
1975 /* If a suffix is given, this operand may be shortened. */
1976 switch (guess_suffix
)
1978 case LONG_MNEM_SUFFIX
:
1979 i
.types
[op
] |= Imm32
| Imm64
;
1981 case WORD_MNEM_SUFFIX
:
1982 i
.types
[op
] |= Imm16
| Imm32S
| Imm32
| Imm64
;
1984 case BYTE_MNEM_SUFFIX
:
1985 i
.types
[op
] |= Imm16
| Imm8
| Imm8S
| Imm32S
| Imm32
| Imm64
;
1989 /* If this operand is at most 16 bits, convert it
1990 to a signed 16 bit number before trying to see
1991 whether it will fit in an even smaller size.
1992 This allows a 16-bit operand such as $0xffe0 to
1993 be recognised as within Imm8S range. */
1994 if ((i
.types
[op
] & Imm16
)
1995 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
1997 i
.op
[op
].imms
->X_add_number
=
1998 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
2000 if ((i
.types
[op
] & Imm32
)
2001 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
2004 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
2005 ^ ((offsetT
) 1 << 31))
2006 - ((offsetT
) 1 << 31));
2008 i
.types
[op
] |= smallest_imm_type (i
.op
[op
].imms
->X_add_number
);
2010 /* We must avoid matching of Imm32 templates when 64bit
2011 only immediate is available. */
2012 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
2013 i
.types
[op
] &= ~Imm32
;
2020 /* Symbols and expressions. */
2022 /* Convert symbolic operand to proper sizes for matching. */
2023 switch (guess_suffix
)
2025 case QWORD_MNEM_SUFFIX
:
2026 i
.types
[op
] = Imm64
| Imm32S
;
2028 case LONG_MNEM_SUFFIX
:
2029 i
.types
[op
] = Imm32
;
2031 case WORD_MNEM_SUFFIX
:
2032 i
.types
[op
] = Imm16
;
2034 case BYTE_MNEM_SUFFIX
:
2035 i
.types
[op
] = Imm8
| Imm8S
;
2043 /* Try to use the smallest displacement type too. */
2049 for (op
= i
.operands
; --op
>= 0;)
2050 if ((i
.types
[op
] & Disp
) && i
.op
[op
].disps
->X_op
== O_constant
)
2052 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
2054 if (i
.types
[op
] & Disp16
)
2056 /* We know this operand is at most 16 bits, so
2057 convert to a signed 16 bit number before trying
2058 to see whether it will fit in an even smaller
2061 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
2063 else if (i
.types
[op
] & Disp32
)
2065 /* We know this operand is at most 32 bits, so convert to a
2066 signed 32 bit number before trying to see whether it will
2067 fit in an even smaller size. */
2068 disp
&= (((offsetT
) 2 << 31) - 1);
2069 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
2071 if (flag_code
== CODE_64BIT
)
2073 if (fits_in_signed_long (disp
))
2074 i
.types
[op
] |= Disp32S
;
2075 if (fits_in_unsigned_long (disp
))
2076 i
.types
[op
] |= Disp32
;
2078 if ((i
.types
[op
] & (Disp32
| Disp32S
| Disp16
))
2079 && fits_in_signed_byte (disp
))
2080 i
.types
[op
] |= Disp8
;
2087 /* Points to template once we've found it. */
2089 unsigned int overlap0
, overlap1
, overlap2
;
2090 unsigned int found_reverse_match
;
2093 #define MATCH(overlap, given, template) \
2094 ((overlap & ~JumpAbsolute) \
2095 && (((given) & (BaseIndex | JumpAbsolute)) \
2096 == ((overlap) & (BaseIndex | JumpAbsolute))))
2098 /* If given types r0 and r1 are registers they must be of the same type
2099 unless the expected operand type register overlap is null.
2100 Note that Acc in a template matches every size of reg. */
2101 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2102 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2103 || ((g0) & Reg) == ((g1) & Reg) \
2104 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2109 found_reverse_match
= 0;
2110 suffix_check
= (i
.suffix
== BYTE_MNEM_SUFFIX
2112 : (i
.suffix
== WORD_MNEM_SUFFIX
2114 : (i
.suffix
== SHORT_MNEM_SUFFIX
2116 : (i
.suffix
== LONG_MNEM_SUFFIX
2118 : (i
.suffix
== QWORD_MNEM_SUFFIX
2120 : (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
2121 ? No_xSuf
: 0))))));
2123 t
= current_templates
->start
;
2124 if (i
.suffix
== QWORD_MNEM_SUFFIX
2125 && flag_code
!= CODE_64BIT
2127 ? !(t
->opcode_modifier
& IgnoreSize
)
2128 && !intel_float_operand (t
->name
)
2129 : intel_float_operand (t
->name
) != 2)
2130 && (!(t
->operand_types
[0] & (RegMMX
| RegXMM
))
2131 || !(t
->operand_types
[t
->operands
> 1] & (RegMMX
| RegXMM
)))
2132 && (t
->base_opcode
!= 0x0fc7
2133 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
2134 t
= current_templates
->end
;
2135 for (; t
< current_templates
->end
; t
++)
2137 /* Must have right number of operands. */
2138 if (i
.operands
!= t
->operands
)
2141 /* Check the suffix, except for some instructions in intel mode. */
2142 if ((t
->opcode_modifier
& suffix_check
)
2144 && (t
->opcode_modifier
& IgnoreSize
)))
2147 /* Do not verify operands when there are none. */
2148 else if (!t
->operands
)
2150 if (t
->cpu_flags
& ~cpu_arch_flags
)
2152 /* We've found a match; break out of loop. */
2156 overlap0
= i
.types
[0] & t
->operand_types
[0];
2157 switch (t
->operands
)
2160 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0]))
2165 overlap1
= i
.types
[1] & t
->operand_types
[1];
2166 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0])
2167 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[1])
2168 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
2169 t
->operand_types
[0],
2170 overlap1
, i
.types
[1],
2171 t
->operand_types
[1]))
2173 /* Check if other direction is valid ... */
2174 if ((t
->opcode_modifier
& (D
| FloatD
)) == 0)
2177 /* Try reversing direction of operands. */
2178 overlap0
= i
.types
[0] & t
->operand_types
[1];
2179 overlap1
= i
.types
[1] & t
->operand_types
[0];
2180 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[1])
2181 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[0])
2182 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
2183 t
->operand_types
[1],
2184 overlap1
, i
.types
[1],
2185 t
->operand_types
[0]))
2187 /* Does not match either direction. */
2190 /* found_reverse_match holds which of D or FloatDR
2192 found_reverse_match
= t
->opcode_modifier
& (D
| FloatDR
);
2194 /* Found a forward 2 operand match here. */
2195 else if (t
->operands
== 3)
2197 /* Here we make use of the fact that there are no
2198 reverse match 3 operand instructions, and all 3
2199 operand instructions only need to be checked for
2200 register consistency between operands 2 and 3. */
2201 overlap2
= i
.types
[2] & t
->operand_types
[2];
2202 if (!MATCH (overlap2
, i
.types
[2], t
->operand_types
[2])
2203 || !CONSISTENT_REGISTER_MATCH (overlap1
, i
.types
[1],
2204 t
->operand_types
[1],
2205 overlap2
, i
.types
[2],
2206 t
->operand_types
[2]))
2210 /* Found either forward/reverse 2 or 3 operand match here:
2211 slip through to break. */
2213 if (t
->cpu_flags
& ~cpu_arch_flags
)
2215 found_reverse_match
= 0;
2218 /* We've found a match; break out of loop. */
2222 if (t
== current_templates
->end
)
2224 /* We found no match. */
2225 as_bad (_("suffix or operands invalid for `%s'"),
2226 current_templates
->start
->name
);
2230 if (!quiet_warnings
)
2233 && ((i
.types
[0] & JumpAbsolute
)
2234 != (t
->operand_types
[0] & JumpAbsolute
)))
2236 as_warn (_("indirect %s without `*'"), t
->name
);
2239 if ((t
->opcode_modifier
& (IsPrefix
| IgnoreSize
))
2240 == (IsPrefix
| IgnoreSize
))
2242 /* Warn them that a data or address size prefix doesn't
2243 affect assembly of the next line of code. */
2244 as_warn (_("stand-alone `%s' prefix"), t
->name
);
2248 /* Copy the template we found. */
2250 if (found_reverse_match
)
2252 /* If we found a reverse match we must alter the opcode
2253 direction bit. found_reverse_match holds bits to change
2254 (different for int & float insns). */
2256 i
.tm
.base_opcode
^= found_reverse_match
;
2258 i
.tm
.operand_types
[0] = t
->operand_types
[1];
2259 i
.tm
.operand_types
[1] = t
->operand_types
[0];
2268 int mem_op
= (i
.types
[0] & AnyMem
) ? 0 : 1;
2269 if ((i
.tm
.operand_types
[mem_op
] & EsSeg
) != 0)
2271 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
2273 as_bad (_("`%s' operand %d must use `%%es' segment"),
2278 /* There's only ever one segment override allowed per instruction.
2279 This instruction possibly has a legal segment override on the
2280 second operand, so copy the segment to where non-string
2281 instructions store it, allowing common code. */
2282 i
.seg
[0] = i
.seg
[1];
2284 else if ((i
.tm
.operand_types
[mem_op
+ 1] & EsSeg
) != 0)
2286 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
2288 as_bad (_("`%s' operand %d must use `%%es' segment"),
2298 process_suffix (void)
2300 /* If matched instruction specifies an explicit instruction mnemonic
2302 if (i
.tm
.opcode_modifier
& (Size16
| Size32
| Size64
))
2304 if (i
.tm
.opcode_modifier
& Size16
)
2305 i
.suffix
= WORD_MNEM_SUFFIX
;
2306 else if (i
.tm
.opcode_modifier
& Size64
)
2307 i
.suffix
= QWORD_MNEM_SUFFIX
;
2309 i
.suffix
= LONG_MNEM_SUFFIX
;
2311 else if (i
.reg_operands
)
2313 /* If there's no instruction mnemonic suffix we try to invent one
2314 based on register operands. */
2317 /* We take i.suffix from the last register operand specified,
2318 Destination register type is more significant than source
2322 for (op
= i
.operands
; --op
>= 0;)
2323 if ((i
.types
[op
] & Reg
)
2324 && !(i
.tm
.operand_types
[op
] & InOutPortReg
))
2326 i
.suffix
= ((i
.types
[op
] & Reg8
) ? BYTE_MNEM_SUFFIX
:
2327 (i
.types
[op
] & Reg16
) ? WORD_MNEM_SUFFIX
:
2328 (i
.types
[op
] & Reg64
) ? QWORD_MNEM_SUFFIX
:
2333 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
2335 if (!check_byte_reg ())
2338 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
2340 if (!check_long_reg ())
2343 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
2345 if (!check_qword_reg ())
2348 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
2350 if (!check_word_reg ())
2353 else if (intel_syntax
&& (i
.tm
.opcode_modifier
& IgnoreSize
))
2354 /* Do nothing if the instruction is going to ignore the prefix. */
2359 else if ((i
.tm
.opcode_modifier
& DefaultSize
)
2361 /* exclude fldenv/frstor/fsave/fstenv */
2362 && (i
.tm
.opcode_modifier
& No_sSuf
))
2364 i
.suffix
= stackop_size
;
2366 else if (intel_syntax
2368 && ((i
.tm
.operand_types
[0] & JumpAbsolute
)
2369 || (i
.tm
.opcode_modifier
& (JumpByte
|JumpInterSegment
))
2370 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
2371 && i
.tm
.extension_opcode
<= 3)))
2376 if (!(i
.tm
.opcode_modifier
& No_qSuf
))
2378 i
.suffix
= QWORD_MNEM_SUFFIX
;
2382 if (!(i
.tm
.opcode_modifier
& No_lSuf
))
2383 i
.suffix
= LONG_MNEM_SUFFIX
;
2386 if (!(i
.tm
.opcode_modifier
& No_wSuf
))
2387 i
.suffix
= WORD_MNEM_SUFFIX
;
2396 if (i
.tm
.opcode_modifier
& W
)
2398 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2404 unsigned int suffixes
= ~i
.tm
.opcode_modifier
2412 if ((i
.tm
.opcode_modifier
& W
)
2413 || ((suffixes
& (suffixes
- 1))
2414 && !(i
.tm
.opcode_modifier
& (DefaultSize
| IgnoreSize
))))
2416 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
2422 /* Change the opcode based on the operand size given by i.suffix;
2423 We don't need to change things for byte insns. */
2425 if (i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
2427 /* It's not a byte, select word/dword operation. */
2428 if (i
.tm
.opcode_modifier
& W
)
2430 if (i
.tm
.opcode_modifier
& ShortForm
)
2431 i
.tm
.base_opcode
|= 8;
2433 i
.tm
.base_opcode
|= 1;
2436 /* Now select between word & dword operations via the operand
2437 size prefix, except for instructions that will ignore this
2439 if (i
.suffix
!= QWORD_MNEM_SUFFIX
2440 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
2441 && !(i
.tm
.opcode_modifier
& (IgnoreSize
| FloatMF
))
2442 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
2443 || (flag_code
== CODE_64BIT
2444 && (i
.tm
.opcode_modifier
& JumpByte
))))
2446 unsigned int prefix
= DATA_PREFIX_OPCODE
;
2448 if (i
.tm
.opcode_modifier
& JumpByte
) /* jcxz, loop */
2449 prefix
= ADDR_PREFIX_OPCODE
;
2451 if (!add_prefix (prefix
))
2455 /* Set mode64 for an operand. */
2456 if (i
.suffix
== QWORD_MNEM_SUFFIX
2457 && flag_code
== CODE_64BIT
2458 && (i
.tm
.opcode_modifier
& NoRex64
) == 0)
2459 i
.rex
|= REX_MODE64
;
2461 /* Size floating point instruction. */
2462 if (i
.suffix
== LONG_MNEM_SUFFIX
)
2463 if (i
.tm
.opcode_modifier
& FloatMF
)
2464 i
.tm
.base_opcode
^= 4;
2471 check_byte_reg (void)
2475 for (op
= i
.operands
; --op
>= 0;)
2477 /* If this is an eight bit register, it's OK. If it's the 16 or
2478 32 bit version of an eight bit register, we will just use the
2479 low portion, and that's OK too. */
2480 if (i
.types
[op
] & Reg8
)
2483 /* movzx and movsx should not generate this warning. */
2485 && (i
.tm
.base_opcode
== 0xfb7
2486 || i
.tm
.base_opcode
== 0xfb6
2487 || i
.tm
.base_opcode
== 0x63
2488 || i
.tm
.base_opcode
== 0xfbe
2489 || i
.tm
.base_opcode
== 0xfbf))
2492 if ((i
.types
[op
] & WordReg
) && i
.op
[op
].regs
->reg_num
< 4)
2494 /* Prohibit these changes in the 64bit mode, since the
2495 lowering is more complicated. */
2496 if (flag_code
== CODE_64BIT
2497 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
2499 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2500 i
.op
[op
].regs
->reg_name
,
2504 #if REGISTER_WARNINGS
2506 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
2507 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2508 (i
.op
[op
].regs
+ (i
.types
[op
] & Reg16
2509 ? REGNAM_AL
- REGNAM_AX
2510 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
2511 i
.op
[op
].regs
->reg_name
,
2516 /* Any other register is bad. */
2517 if (i
.types
[op
] & (Reg
| RegMMX
| RegXMM
2519 | Control
| Debug
| Test
2520 | FloatReg
| FloatAcc
))
2522 as_bad (_("`%%%s' not allowed with `%s%c'"),
2523 i
.op
[op
].regs
->reg_name
,
2537 for (op
= i
.operands
; --op
>= 0;)
2538 /* Reject eight bit registers, except where the template requires
2539 them. (eg. movzb) */
2540 if ((i
.types
[op
] & Reg8
) != 0
2541 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2543 as_bad (_("`%%%s' not allowed with `%s%c'"),
2544 i
.op
[op
].regs
->reg_name
,
2549 /* Warn if the e prefix on a general reg is missing. */
2550 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2551 && (i
.types
[op
] & Reg16
) != 0
2552 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2554 /* Prohibit these changes in the 64bit mode, since the
2555 lowering is more complicated. */
2556 if (flag_code
== CODE_64BIT
)
2558 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2559 i
.op
[op
].regs
->reg_name
,
2563 #if REGISTER_WARNINGS
2565 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2566 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
2567 i
.op
[op
].regs
->reg_name
,
2571 /* Warn if the r prefix on a general reg is missing. */
2572 else if ((i
.types
[op
] & Reg64
) != 0
2573 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2575 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2576 i
.op
[op
].regs
->reg_name
,
2588 for (op
= i
.operands
; --op
>= 0; )
2589 /* Reject eight bit registers, except where the template requires
2590 them. (eg. movzb) */
2591 if ((i
.types
[op
] & Reg8
) != 0
2592 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2594 as_bad (_("`%%%s' not allowed with `%s%c'"),
2595 i
.op
[op
].regs
->reg_name
,
2600 /* Warn if the e prefix on a general reg is missing. */
2601 else if (((i
.types
[op
] & Reg16
) != 0
2602 || (i
.types
[op
] & Reg32
) != 0)
2603 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2605 /* Prohibit these changes in the 64bit mode, since the
2606 lowering is more complicated. */
2607 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2608 i
.op
[op
].regs
->reg_name
,
2619 for (op
= i
.operands
; --op
>= 0;)
2620 /* Reject eight bit registers, except where the template requires
2621 them. (eg. movzb) */
2622 if ((i
.types
[op
] & Reg8
) != 0
2623 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2625 as_bad (_("`%%%s' not allowed with `%s%c'"),
2626 i
.op
[op
].regs
->reg_name
,
2631 /* Warn if the e prefix on a general reg is present. */
2632 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2633 && (i
.types
[op
] & Reg32
) != 0
2634 && (i
.tm
.operand_types
[op
] & (Reg16
| Acc
)) != 0)
2636 /* Prohibit these changes in the 64bit mode, since the
2637 lowering is more complicated. */
2638 if (flag_code
== CODE_64BIT
)
2640 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2641 i
.op
[op
].regs
->reg_name
,
2646 #if REGISTER_WARNINGS
2647 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2648 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
2649 i
.op
[op
].regs
->reg_name
,
2659 unsigned int overlap0
, overlap1
, overlap2
;
2661 overlap0
= i
.types
[0] & i
.tm
.operand_types
[0];
2662 if ((overlap0
& (Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
))
2663 && overlap0
!= Imm8
&& overlap0
!= Imm8S
2664 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2665 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2669 overlap0
&= (i
.suffix
== BYTE_MNEM_SUFFIX
2671 : (i
.suffix
== WORD_MNEM_SUFFIX
2673 : (i
.suffix
== QWORD_MNEM_SUFFIX
2677 else if (overlap0
== (Imm16
| Imm32S
| Imm32
)
2678 || overlap0
== (Imm16
| Imm32
)
2679 || overlap0
== (Imm16
| Imm32S
))
2681 overlap0
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)
2684 if (overlap0
!= Imm8
&& overlap0
!= Imm8S
2685 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2686 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2688 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2692 i
.types
[0] = overlap0
;
2694 overlap1
= i
.types
[1] & i
.tm
.operand_types
[1];
2695 if ((overlap1
& (Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
| Imm64
))
2696 && overlap1
!= Imm8
&& overlap1
!= Imm8S
2697 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2698 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2702 overlap1
&= (i
.suffix
== BYTE_MNEM_SUFFIX
2704 : (i
.suffix
== WORD_MNEM_SUFFIX
2706 : (i
.suffix
== QWORD_MNEM_SUFFIX
2710 else if (overlap1
== (Imm16
| Imm32
| Imm32S
)
2711 || overlap1
== (Imm16
| Imm32
)
2712 || overlap1
== (Imm16
| Imm32S
))
2714 overlap1
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)
2717 if (overlap1
!= Imm8
&& overlap1
!= Imm8S
2718 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2719 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2721 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1
, i
.suffix
);
2725 i
.types
[1] = overlap1
;
2727 overlap2
= i
.types
[2] & i
.tm
.operand_types
[2];
2728 assert ((overlap2
& Imm
) == 0);
2729 i
.types
[2] = overlap2
;
2737 /* Default segment register this instruction will use for memory
2738 accesses. 0 means unknown. This is only for optimizing out
2739 unnecessary segment overrides. */
2740 const seg_entry
*default_seg
= 0;
2742 /* The imul $imm, %reg instruction is converted into
2743 imul $imm, %reg, %reg, and the clr %reg instruction
2744 is converted into xor %reg, %reg. */
2745 if (i
.tm
.opcode_modifier
& regKludge
)
2747 unsigned int first_reg_op
= (i
.types
[0] & Reg
) ? 0 : 1;
2748 /* Pretend we saw the extra register operand. */
2749 assert (i
.op
[first_reg_op
+ 1].regs
== 0);
2750 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
2751 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
2755 if (i
.tm
.opcode_modifier
& ShortForm
)
2757 /* The register or float register operand is in operand 0 or 1. */
2758 unsigned int op
= (i
.types
[0] & (Reg
| FloatReg
)) ? 0 : 1;
2759 /* Register goes in low 3 bits of opcode. */
2760 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
2761 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
2763 if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
2765 /* Warn about some common errors, but press on regardless.
2766 The first case can be generated by gcc (<= 2.8.1). */
2767 if (i
.operands
== 2)
2769 /* Reversed arguments on faddp, fsubp, etc. */
2770 as_warn (_("translating to `%s %%%s,%%%s'"), i
.tm
.name
,
2771 i
.op
[1].regs
->reg_name
,
2772 i
.op
[0].regs
->reg_name
);
2776 /* Extraneous `l' suffix on fp insn. */
2777 as_warn (_("translating to `%s %%%s'"), i
.tm
.name
,
2778 i
.op
[0].regs
->reg_name
);
2782 else if (i
.tm
.opcode_modifier
& Modrm
)
2784 /* The opcode is completed (modulo i.tm.extension_opcode which
2785 must be put into the modrm byte). Now, we make the modrm and
2786 index base bytes based on all the info we've collected. */
2788 default_seg
= build_modrm_byte ();
2790 else if (i
.tm
.opcode_modifier
& (Seg2ShortForm
| Seg3ShortForm
))
2792 if (i
.tm
.base_opcode
== POP_SEG_SHORT
2793 && i
.op
[0].regs
->reg_num
== 1)
2795 as_bad (_("you can't `pop %%cs'"));
2798 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
2799 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
2802 else if ((i
.tm
.base_opcode
& ~(D
| W
)) == MOV_AX_DISP32
)
2806 else if ((i
.tm
.opcode_modifier
& IsString
) != 0)
2808 /* For the string instructions that allow a segment override
2809 on one of their operands, the default segment is ds. */
2813 if (i
.tm
.base_opcode
== 0x8d /* lea */ && i
.seg
[0] && !quiet_warnings
)
2814 as_warn (_("segment override on `lea' is ineffectual"));
2816 /* If a segment was explicitly specified, and the specified segment
2817 is not the default, use an opcode prefix to select it. If we
2818 never figured out what the default segment is, then default_seg
2819 will be zero at this point, and the specified segment prefix will
2821 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
2823 if (!add_prefix (i
.seg
[0]->seg_prefix
))
2829 static const seg_entry
*
2832 const seg_entry
*default_seg
= 0;
2834 /* i.reg_operands MUST be the number of real register operands;
2835 implicit registers do not count. */
2836 if (i
.reg_operands
== 2)
2838 unsigned int source
, dest
;
2839 source
= ((i
.types
[0]
2840 & (Reg
| RegMMX
| RegXMM
2842 | Control
| Debug
| Test
))
2847 /* One of the register operands will be encoded in the i.tm.reg
2848 field, the other in the combined i.tm.mode and i.tm.regmem
2849 fields. If no form of this instruction supports a memory
2850 destination operand, then we assume the source operand may
2851 sometimes be a memory operand and so we need to store the
2852 destination in the i.rm.reg field. */
2853 if ((i
.tm
.operand_types
[dest
] & AnyMem
) == 0)
2855 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
2856 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
2857 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
2859 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
2864 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
2865 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
2866 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
2868 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
2871 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_EXTX
| REX_EXTZ
)))
2873 if (!((i
.types
[0] | i
.types
[1]) & Control
))
2875 i
.rex
&= ~(REX_EXTX
| REX_EXTZ
);
2876 add_prefix (LOCK_PREFIX_OPCODE
);
2880 { /* If it's not 2 reg operands... */
2883 unsigned int fake_zero_displacement
= 0;
2884 unsigned int op
= ((i
.types
[0] & AnyMem
)
2886 : (i
.types
[1] & AnyMem
) ? 1 : 2);
2890 if (i
.base_reg
== 0)
2893 if (!i
.disp_operands
)
2894 fake_zero_displacement
= 1;
2895 if (i
.index_reg
== 0)
2897 /* Operand is just <disp> */
2898 if (flag_code
== CODE_64BIT
)
2900 /* 64bit mode overwrites the 32bit absolute
2901 addressing by RIP relative addressing and
2902 absolute addressing is encoded by one of the
2903 redundant SIB forms. */
2904 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2905 i
.sib
.base
= NO_BASE_REGISTER
;
2906 i
.sib
.index
= NO_INDEX_REGISTER
;
2907 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0) ? Disp32S
: Disp32
);
2909 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
2911 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
2912 i
.types
[op
] = Disp16
;
2916 i
.rm
.regmem
= NO_BASE_REGISTER
;
2917 i
.types
[op
] = Disp32
;
2920 else /* !i.base_reg && i.index_reg */
2922 i
.sib
.index
= i
.index_reg
->reg_num
;
2923 i
.sib
.base
= NO_BASE_REGISTER
;
2924 i
.sib
.scale
= i
.log2_scale_factor
;
2925 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2926 i
.types
[op
] &= ~Disp
;
2927 if (flag_code
!= CODE_64BIT
)
2928 i
.types
[op
] |= Disp32
; /* Must be 32 bit */
2930 i
.types
[op
] |= Disp32S
;
2931 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
2935 /* RIP addressing for 64bit mode. */
2936 else if (i
.base_reg
->reg_type
== BaseIndex
)
2938 i
.rm
.regmem
= NO_BASE_REGISTER
;
2939 i
.types
[op
] &= ~ Disp
;
2940 i
.types
[op
] |= Disp32S
;
2941 i
.flags
[op
] = Operand_PCrel
;
2942 if (! i
.disp_operands
)
2943 fake_zero_displacement
= 1;
2945 else if (i
.base_reg
->reg_type
& Reg16
)
2947 switch (i
.base_reg
->reg_num
)
2950 if (i
.index_reg
== 0)
2952 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
2953 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
2957 if (i
.index_reg
== 0)
2960 if ((i
.types
[op
] & Disp
) == 0)
2962 /* fake (%bp) into 0(%bp) */
2963 i
.types
[op
] |= Disp8
;
2964 fake_zero_displacement
= 1;
2967 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
2968 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
2970 default: /* (%si) -> 4 or (%di) -> 5 */
2971 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
2973 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2975 else /* i.base_reg and 32/64 bit mode */
2977 if (flag_code
== CODE_64BIT
2978 && (i
.types
[op
] & Disp
))
2979 i
.types
[op
] = (i
.types
[op
] & Disp8
) | (i
.prefix
[ADDR_PREFIX
] == 0 ? Disp32S
: Disp32
);
2981 i
.rm
.regmem
= i
.base_reg
->reg_num
;
2982 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
2984 i
.sib
.base
= i
.base_reg
->reg_num
;
2985 /* x86-64 ignores REX prefix bit here to avoid decoder
2987 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
2990 if (i
.disp_operands
== 0)
2992 fake_zero_displacement
= 1;
2993 i
.types
[op
] |= Disp8
;
2996 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
3000 i
.sib
.scale
= i
.log2_scale_factor
;
3001 if (i
.index_reg
== 0)
3003 /* <disp>(%esp) becomes two byte modrm with no index
3004 register. We've already stored the code for esp
3005 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3006 Any base register besides %esp will not use the
3007 extra modrm byte. */
3008 i
.sib
.index
= NO_INDEX_REGISTER
;
3009 #if !SCALE1_WHEN_NO_INDEX
3010 /* Another case where we force the second modrm byte. */
3011 if (i
.log2_scale_factor
)
3012 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3017 i
.sib
.index
= i
.index_reg
->reg_num
;
3018 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3019 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
3022 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
3025 if (fake_zero_displacement
)
3027 /* Fakes a zero displacement assuming that i.types[op]
3028 holds the correct displacement size. */
3031 assert (i
.op
[op
].disps
== 0);
3032 exp
= &disp_expressions
[i
.disp_operands
++];
3033 i
.op
[op
].disps
= exp
;
3034 exp
->X_op
= O_constant
;
3035 exp
->X_add_number
= 0;
3036 exp
->X_add_symbol
= (symbolS
*) 0;
3037 exp
->X_op_symbol
= (symbolS
*) 0;
3041 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3042 (if any) based on i.tm.extension_opcode. Again, we must be
3043 careful to make sure that segment/control/debug/test/MMX
3044 registers are coded into the i.rm.reg field. */
3049 & (Reg
| RegMMX
| RegXMM
3051 | Control
| Debug
| Test
))
3054 & (Reg
| RegMMX
| RegXMM
3056 | Control
| Debug
| Test
))
3059 /* If there is an extension opcode to put here, the register
3060 number must be put into the regmem field. */
3061 if (i
.tm
.extension_opcode
!= None
)
3063 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
3064 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
3069 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
3070 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
3074 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3075 must set it to 3 to indicate this is a register operand
3076 in the regmem field. */
3077 if (!i
.mem_operands
)
3081 /* Fill in i.rm.reg field with extension opcode (if any). */
3082 if (i
.tm
.extension_opcode
!= None
)
3083 i
.rm
.reg
= i
.tm
.extension_opcode
;
3094 relax_substateT subtype
;
3099 if (flag_code
== CODE_16BIT
)
3103 if (i
.prefix
[DATA_PREFIX
] != 0)
3109 /* Pentium4 branch hints. */
3110 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
3111 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
3116 if (i
.prefix
[REX_PREFIX
] != 0)
3122 if (i
.prefixes
!= 0 && !intel_syntax
)
3123 as_warn (_("skipping prefixes on this instruction"));
3125 /* It's always a symbol; End frag & setup for relax.
3126 Make sure there is enough room in this frag for the largest
3127 instruction we may generate in md_convert_frag. This is 2
3128 bytes for the opcode and room for the prefix and largest
3130 frag_grow (prefix
+ 2 + 4);
3131 /* Prefix and 1 opcode byte go in fr_fix. */
3132 p
= frag_more (prefix
+ 1);
3133 if (i
.prefix
[DATA_PREFIX
] != 0)
3134 *p
++ = DATA_PREFIX_OPCODE
;
3135 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
3136 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
3137 *p
++ = i
.prefix
[SEG_PREFIX
];
3138 if (i
.prefix
[REX_PREFIX
] != 0)
3139 *p
++ = i
.prefix
[REX_PREFIX
];
3140 *p
= i
.tm
.base_opcode
;
3142 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
3143 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
3144 else if ((cpu_arch_flags
& Cpu386
) != 0)
3145 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
3147 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
3150 sym
= i
.op
[0].disps
->X_add_symbol
;
3151 off
= i
.op
[0].disps
->X_add_number
;
3153 if (i
.op
[0].disps
->X_op
!= O_constant
3154 && i
.op
[0].disps
->X_op
!= O_symbol
)
3156 /* Handle complex expressions. */
3157 sym
= make_expr_symbol (i
.op
[0].disps
);
3161 /* 1 possible extra opcode + 4 byte displacement go in var part.
3162 Pass reloc in fr_var. */
3163 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
3173 if (i
.tm
.opcode_modifier
& JumpByte
)
3175 /* This is a loop or jecxz type instruction. */
3177 if (i
.prefix
[ADDR_PREFIX
] != 0)
3179 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
3182 /* Pentium4 branch hints. */
3183 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
3184 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
3186 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
3195 if (flag_code
== CODE_16BIT
)
3198 if (i
.prefix
[DATA_PREFIX
] != 0)
3200 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
3210 if (i
.prefix
[REX_PREFIX
] != 0)
3212 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
3216 if (i
.prefixes
!= 0 && !intel_syntax
)
3217 as_warn (_("skipping prefixes on this instruction"));
3219 p
= frag_more (1 + size
);
3220 *p
++ = i
.tm
.base_opcode
;
3222 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3223 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
3225 /* All jumps handled here are signed, but don't use a signed limit
3226 check for 32 and 16 bit jumps as we want to allow wrap around at
3227 4G and 64k respectively. */
3229 fixP
->fx_signed
= 1;
3233 output_interseg_jump ()
3241 if (flag_code
== CODE_16BIT
)
3245 if (i
.prefix
[DATA_PREFIX
] != 0)
3251 if (i
.prefix
[REX_PREFIX
] != 0)
3261 if (i
.prefixes
!= 0 && !intel_syntax
)
3262 as_warn (_("skipping prefixes on this instruction"));
3264 /* 1 opcode; 2 segment; offset */
3265 p
= frag_more (prefix
+ 1 + 2 + size
);
3267 if (i
.prefix
[DATA_PREFIX
] != 0)
3268 *p
++ = DATA_PREFIX_OPCODE
;
3270 if (i
.prefix
[REX_PREFIX
] != 0)
3271 *p
++ = i
.prefix
[REX_PREFIX
];
3273 *p
++ = i
.tm
.base_opcode
;
3274 if (i
.op
[1].imms
->X_op
== O_constant
)
3276 offsetT n
= i
.op
[1].imms
->X_add_number
;
3279 && !fits_in_unsigned_word (n
)
3280 && !fits_in_signed_word (n
))
3282 as_bad (_("16-bit jump out of range"));
3285 md_number_to_chars (p
, n
, size
);
3288 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3289 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
3290 if (i
.op
[0].imms
->X_op
!= O_constant
)
3291 as_bad (_("can't handle non absolute segment in `%s'"),
3293 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
3299 fragS
*insn_start_frag
;
3300 offsetT insn_start_off
;
3302 /* Tie dwarf2 debug info to the address at the start of the insn.
3303 We can't do this after the insn has been output as the current
3304 frag may have been closed off. eg. by frag_var. */
3305 dwarf2_emit_insn (0);
3307 insn_start_frag
= frag_now
;
3308 insn_start_off
= frag_now_fix ();
3311 if (i
.tm
.opcode_modifier
& Jump
)
3313 else if (i
.tm
.opcode_modifier
& (JumpByte
| JumpDword
))
3315 else if (i
.tm
.opcode_modifier
& JumpInterSegment
)
3316 output_interseg_jump ();
3319 /* Output normal instructions here. */
3323 /* All opcodes on i386 have either 1 or 2 bytes. We may use one
3324 more higher byte to specify a prefix the instruction
3326 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
3328 if ((i
.tm
.cpu_flags
& CpuPadLock
) != 0)
3330 unsigned int prefix
;
3331 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
3333 if (prefix
!= REPE_PREFIX_OPCODE
3334 || i
.prefix
[LOCKREP_PREFIX
] != REPE_PREFIX_OPCODE
)
3335 add_prefix (prefix
);
3338 add_prefix ((i
.tm
.base_opcode
>> 16) & 0xff);
3341 /* The prefix bytes. */
3343 q
< i
.prefix
+ sizeof (i
.prefix
) / sizeof (i
.prefix
[0]);
3349 md_number_to_chars (p
, (valueT
) *q
, 1);
3353 /* Now the opcode; be careful about word order here! */
3354 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
3356 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
3362 /* Put out high byte first: can't use md_number_to_chars! */
3363 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
3364 *p
= i
.tm
.base_opcode
& 0xff;
3367 /* Now the modrm byte and sib byte (if present). */
3368 if (i
.tm
.opcode_modifier
& Modrm
)
3371 md_number_to_chars (p
,
3372 (valueT
) (i
.rm
.regmem
<< 0
3376 /* If i.rm.regmem == ESP (4)
3377 && i.rm.mode != (Register mode)
3379 ==> need second modrm byte. */
3380 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
3382 && !(i
.base_reg
&& (i
.base_reg
->reg_type
& Reg16
) != 0))
3385 md_number_to_chars (p
,
3386 (valueT
) (i
.sib
.base
<< 0
3388 | i
.sib
.scale
<< 6),
3393 if (i
.disp_operands
)
3394 output_disp (insn_start_frag
, insn_start_off
);
3397 output_imm (insn_start_frag
, insn_start_off
);
3405 #endif /* DEBUG386 */
3409 output_disp (insn_start_frag
, insn_start_off
)
3410 fragS
*insn_start_frag
;
3411 offsetT insn_start_off
;
3416 for (n
= 0; n
< i
.operands
; n
++)
3418 if (i
.types
[n
] & Disp
)
3420 if (i
.op
[n
].disps
->X_op
== O_constant
)
3426 if (i
.types
[n
] & (Disp8
| Disp16
| Disp64
))
3429 if (i
.types
[n
] & Disp8
)
3431 if (i
.types
[n
] & Disp64
)
3434 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
3436 p
= frag_more (size
);
3437 md_number_to_chars (p
, val
, size
);
3441 enum bfd_reloc_code_real reloc_type
;
3444 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
3446 /* The PC relative address is computed relative
3447 to the instruction boundary, so in case immediate
3448 fields follows, we need to adjust the value. */
3449 if (pcrel
&& i
.imm_operands
)
3454 for (n1
= 0; n1
< i
.operands
; n1
++)
3455 if (i
.types
[n1
] & Imm
)
3457 if (i
.types
[n1
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3460 if (i
.types
[n1
] & (Imm8
| Imm8S
))
3462 if (i
.types
[n1
] & Imm64
)
3467 /* We should find the immediate. */
3468 if (n1
== i
.operands
)
3470 i
.op
[n
].disps
->X_add_number
-= imm_size
;
3473 if (i
.types
[n
] & Disp32S
)
3476 if (i
.types
[n
] & (Disp16
| Disp64
))
3479 if (i
.types
[n
] & Disp64
)
3483 p
= frag_more (size
);
3484 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
3485 if (reloc_type
== BFD_RELOC_32
3487 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
3488 && (i
.op
[n
].disps
->X_op
== O_symbol
3489 || (i
.op
[n
].disps
->X_op
== O_add
3490 && ((symbol_get_value_expression
3491 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
3496 if (insn_start_frag
== frag_now
)
3497 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
3502 add
= insn_start_frag
->fr_fix
- insn_start_off
;
3503 for (fr
= insn_start_frag
->fr_next
;
3504 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
3506 add
+= p
- frag_now
->fr_literal
;
3509 /* We don't support dynamic linking on x86-64 yet. */
3510 if (flag_code
== CODE_64BIT
)
3512 reloc_type
= BFD_RELOC_386_GOTPC
;
3513 i
.op
[n
].disps
->X_add_number
+= add
;
3515 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3516 i
.op
[n
].disps
, pcrel
, reloc_type
);
3523 output_imm (insn_start_frag
, insn_start_off
)
3524 fragS
*insn_start_frag
;
3525 offsetT insn_start_off
;
3530 for (n
= 0; n
< i
.operands
; n
++)
3532 if (i
.types
[n
] & Imm
)
3534 if (i
.op
[n
].imms
->X_op
== O_constant
)
3540 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3543 if (i
.types
[n
] & (Imm8
| Imm8S
))
3545 else if (i
.types
[n
] & Imm64
)
3548 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
3550 p
= frag_more (size
);
3551 md_number_to_chars (p
, val
, size
);
3555 /* Not absolute_section.
3556 Need a 32-bit fixup (don't support 8bit
3557 non-absolute imms). Try to support other
3559 enum bfd_reloc_code_real reloc_type
;
3563 if ((i
.types
[n
] & (Imm32S
))
3564 && (i
.suffix
== QWORD_MNEM_SUFFIX
3565 || (!i
.suffix
&& (i
.tm
.opcode_modifier
& No_lSuf
))))
3567 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3570 if (i
.types
[n
] & (Imm8
| Imm8S
))
3572 if (i
.types
[n
] & Imm64
)
3576 p
= frag_more (size
);
3577 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
3579 /* This is tough to explain. We end up with this one if we
3580 * have operands that look like
3581 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
3582 * obtain the absolute address of the GOT, and it is strongly
3583 * preferable from a performance point of view to avoid using
3584 * a runtime relocation for this. The actual sequence of
3585 * instructions often look something like:
3590 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
3592 * The call and pop essentially return the absolute address
3593 * of the label .L66 and store it in %ebx. The linker itself
3594 * will ultimately change the first operand of the addl so
3595 * that %ebx points to the GOT, but to keep things simple, the
3596 * .o file must have this operand set so that it generates not
3597 * the absolute address of .L66, but the absolute address of
3598 * itself. This allows the linker itself simply treat a GOTPC
3599 * relocation as asking for a pcrel offset to the GOT to be
3600 * added in, and the addend of the relocation is stored in the
3601 * operand field for the instruction itself.
3603 * Our job here is to fix the operand so that it would add
3604 * the correct offset so that %ebx would point to itself. The
3605 * thing that is tricky is that .-.L66 will point to the
3606 * beginning of the instruction, so we need to further modify
3607 * the operand so that it will point to itself. There are
3608 * other cases where you have something like:
3610 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
3612 * and here no correction would be required. Internally in
3613 * the assembler we treat operands of this form as not being
3614 * pcrel since the '.' is explicitly mentioned, and I wonder
3615 * whether it would simplify matters to do it this way. Who
3616 * knows. In earlier versions of the PIC patches, the
3617 * pcrel_adjust field was used to store the correction, but
3618 * since the expression is not pcrel, I felt it would be
3619 * confusing to do it this way. */
3621 if (reloc_type
== BFD_RELOC_32
3623 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
3624 && (i
.op
[n
].imms
->X_op
== O_symbol
3625 || (i
.op
[n
].imms
->X_op
== O_add
3626 && ((symbol_get_value_expression
3627 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
3632 if (insn_start_frag
== frag_now
)
3633 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
3638 add
= insn_start_frag
->fr_fix
- insn_start_off
;
3639 for (fr
= insn_start_frag
->fr_next
;
3640 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
3642 add
+= p
- frag_now
->fr_literal
;
3645 /* We don't support dynamic linking on x86-64 yet. */
3646 if (flag_code
== CODE_64BIT
)
3648 reloc_type
= BFD_RELOC_386_GOTPC
;
3649 i
.op
[n
].imms
->X_add_number
+= add
;
3651 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3652 i
.op
[n
].imms
, 0, reloc_type
);
3659 static char *lex_got
PARAMS ((enum bfd_reloc_code_real
*, int *));
3661 /* Parse operands of the form
3662 <symbol>@GOTOFF+<nnn>
3663 and similar .plt or .got references.
3665 If we find one, set up the correct relocation in RELOC and copy the
3666 input string, minus the `@GOTOFF' into a malloc'd buffer for
3667 parsing by the calling routine. Return this buffer, and if ADJUST
3668 is non-null set it to the length of the string we removed from the
3669 input line. Otherwise return NULL. */
3671 lex_got (reloc
, adjust
)
3672 enum bfd_reloc_code_real
*reloc
;
3675 static const char * const mode_name
[NUM_FLAG_CODE
] = { "32", "16", "64" };
3676 static const struct {
3678 const enum bfd_reloc_code_real rel
[NUM_FLAG_CODE
];
3680 { "PLT", { BFD_RELOC_386_PLT32
, 0, BFD_RELOC_X86_64_PLT32
} },
3681 { "GOTOFF", { BFD_RELOC_386_GOTOFF
, 0, 0 } },
3682 { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL
} },
3683 { "TLSGD", { BFD_RELOC_386_TLS_GD
, 0, BFD_RELOC_X86_64_TLSGD
} },
3684 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
, 0, 0 } },
3685 { "TLSLD", { 0, 0, BFD_RELOC_X86_64_TLSLD
} },
3686 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
, 0, BFD_RELOC_X86_64_GOTTPOFF
} },
3687 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
, 0, BFD_RELOC_X86_64_TPOFF32
} },
3688 { "NTPOFF", { BFD_RELOC_386_TLS_LE
, 0, 0 } },
3689 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
, 0, BFD_RELOC_X86_64_DTPOFF32
} },
3690 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE
, 0, 0 } },
3691 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE
, 0, 0 } },
3692 { "GOT", { BFD_RELOC_386_GOT32
, 0, BFD_RELOC_X86_64_GOT32
} }
3697 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
3698 if (is_end_of_line
[(unsigned char) *cp
])
3701 for (j
= 0; j
< sizeof (gotrel
) / sizeof (gotrel
[0]); j
++)
3705 len
= strlen (gotrel
[j
].str
);
3706 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
3708 if (gotrel
[j
].rel
[(unsigned int) flag_code
] != 0)
3711 char *tmpbuf
, *past_reloc
;
3713 *reloc
= gotrel
[j
].rel
[(unsigned int) flag_code
];
3717 if (GOT_symbol
== NULL
)
3718 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
3720 /* Replace the relocation token with ' ', so that
3721 errors like foo@GOTOFF1 will be detected. */
3723 /* The length of the first part of our input line. */
3724 first
= cp
- input_line_pointer
;
3726 /* The second part goes from after the reloc token until
3727 (and including) an end_of_line char. Don't use strlen
3728 here as the end_of_line char may not be a NUL. */
3729 past_reloc
= cp
+ 1 + len
;
3730 for (cp
= past_reloc
; !is_end_of_line
[(unsigned char) *cp
++]; )
3732 second
= cp
- past_reloc
;
3734 /* Allocate and copy string. The trailing NUL shouldn't
3735 be necessary, but be safe. */
3736 tmpbuf
= xmalloc (first
+ second
+ 2);
3737 memcpy (tmpbuf
, input_line_pointer
, first
);
3738 tmpbuf
[first
] = ' ';
3739 memcpy (tmpbuf
+ first
+ 1, past_reloc
, second
);
3740 tmpbuf
[first
+ second
+ 1] = '\0';
3744 as_bad (_("@%s reloc is not supported in %s bit mode"),
3745 gotrel
[j
].str
, mode_name
[(unsigned int) flag_code
]);
3750 /* Might be a symbol version string. Don't as_bad here. */
3754 /* x86_cons_fix_new is called via the expression parsing code when a
3755 reloc is needed. We use this hook to get the correct .got reloc. */
3756 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
3759 x86_cons_fix_new (frag
, off
, len
, exp
)
3765 enum bfd_reloc_code_real r
= reloc (len
, 0, 0, got_reloc
);
3766 got_reloc
= NO_RELOC
;
3767 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
3771 x86_cons (exp
, size
)
3777 /* Handle @GOTOFF and the like in an expression. */
3779 char *gotfree_input_line
;
3782 save
= input_line_pointer
;
3783 gotfree_input_line
= lex_got (&got_reloc
, &adjust
);
3784 if (gotfree_input_line
)
3785 input_line_pointer
= gotfree_input_line
;
3789 if (gotfree_input_line
)
3791 /* expression () has merrily parsed up to the end of line,
3792 or a comma - in the wrong buffer. Transfer how far
3793 input_line_pointer has moved to the right buffer. */
3794 input_line_pointer
= (save
3795 + (input_line_pointer
- gotfree_input_line
)
3797 free (gotfree_input_line
);
3808 x86_pe_cons_fix_new (frag
, off
, len
, exp
)
3814 enum bfd_reloc_code_real r
= reloc (len
, 0, 0, NO_RELOC
);
3816 if (exp
->X_op
== O_secrel
)
3818 exp
->X_op
= O_symbol
;
3819 r
= BFD_RELOC_32_SECREL
;
3822 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
3826 pe_directive_secrel (dummy
)
3827 int dummy ATTRIBUTE_UNUSED
;
3834 if (exp
.X_op
== O_symbol
)
3835 exp
.X_op
= O_secrel
;
3837 emit_expr (&exp
, 4);
3839 while (*input_line_pointer
++ == ',');
3841 input_line_pointer
--;
3842 demand_empty_rest_of_line ();
3847 static int i386_immediate
PARAMS ((char *));
3850 i386_immediate (imm_start
)
3853 char *save_input_line_pointer
;
3855 char *gotfree_input_line
;
3860 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
3862 as_bad (_("only 1 or 2 immediate operands are allowed"));
3866 exp
= &im_expressions
[i
.imm_operands
++];
3867 i
.op
[this_operand
].imms
= exp
;
3869 if (is_space_char (*imm_start
))
3872 save_input_line_pointer
= input_line_pointer
;
3873 input_line_pointer
= imm_start
;
3876 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
);
3877 if (gotfree_input_line
)
3878 input_line_pointer
= gotfree_input_line
;
3881 exp_seg
= expression (exp
);
3884 if (*input_line_pointer
)
3885 as_bad (_("junk `%s' after expression"), input_line_pointer
);
3887 input_line_pointer
= save_input_line_pointer
;
3889 if (gotfree_input_line
)
3890 free (gotfree_input_line
);
3893 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
3895 /* Missing or bad expr becomes absolute 0. */
3896 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
3898 exp
->X_op
= O_constant
;
3899 exp
->X_add_number
= 0;
3900 exp
->X_add_symbol
= (symbolS
*) 0;
3901 exp
->X_op_symbol
= (symbolS
*) 0;
3903 else if (exp
->X_op
== O_constant
)
3905 /* Size it properly later. */
3906 i
.types
[this_operand
] |= Imm64
;
3907 /* If BFD64, sign extend val. */
3908 if (!use_rela_relocations
)
3909 if ((exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
3910 exp
->X_add_number
= (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
3912 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3913 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
3914 && exp_seg
!= absolute_section
3915 && exp_seg
!= text_section
3916 && exp_seg
!= data_section
3917 && exp_seg
!= bss_section
3918 && exp_seg
!= undefined_section
3919 && !bfd_is_com_section (exp_seg
))
3921 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
3927 /* This is an address. The size of the address will be
3928 determined later, depending on destination register,
3929 suffix, or the default for the section. */
3930 i
.types
[this_operand
] |= Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
;
3936 static char *i386_scale
PARAMS ((char *));
3943 char *save
= input_line_pointer
;
3945 input_line_pointer
= scale
;
3946 val
= get_absolute_expression ();
3951 i
.log2_scale_factor
= 0;
3954 i
.log2_scale_factor
= 1;
3957 i
.log2_scale_factor
= 2;
3960 i
.log2_scale_factor
= 3;
3964 char sep
= *input_line_pointer
;
3966 *input_line_pointer
= '\0';
3967 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
3969 *input_line_pointer
= sep
;
3970 input_line_pointer
= save
;
3974 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
3976 as_warn (_("scale factor of %d without an index register"),
3977 1 << i
.log2_scale_factor
);
3978 #if SCALE1_WHEN_NO_INDEX
3979 i
.log2_scale_factor
= 0;
3982 scale
= input_line_pointer
;
3983 input_line_pointer
= save
;
3987 static int i386_displacement
PARAMS ((char *, char *));
3990 i386_displacement (disp_start
, disp_end
)
3996 char *save_input_line_pointer
;
3998 char *gotfree_input_line
;
4000 int bigdisp
= Disp32
;
4002 if (flag_code
== CODE_64BIT
)
4004 if (i
.prefix
[ADDR_PREFIX
] == 0)
4007 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
4009 i
.types
[this_operand
] |= bigdisp
;
4011 exp
= &disp_expressions
[i
.disp_operands
];
4012 i
.op
[this_operand
].disps
= exp
;
4014 save_input_line_pointer
= input_line_pointer
;
4015 input_line_pointer
= disp_start
;
4016 END_STRING_AND_SAVE (disp_end
);
4018 #ifndef GCC_ASM_O_HACK
4019 #define GCC_ASM_O_HACK 0
4022 END_STRING_AND_SAVE (disp_end
+ 1);
4023 if ((i
.types
[this_operand
] & BaseIndex
) != 0
4024 && displacement_string_end
[-1] == '+')
4026 /* This hack is to avoid a warning when using the "o"
4027 constraint within gcc asm statements.
4030 #define _set_tssldt_desc(n,addr,limit,type) \
4031 __asm__ __volatile__ ( \
4033 "movw %w1,2+%0\n\t" \
4035 "movb %b1,4+%0\n\t" \
4036 "movb %4,5+%0\n\t" \
4037 "movb $0,6+%0\n\t" \
4038 "movb %h1,7+%0\n\t" \
4040 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4042 This works great except that the output assembler ends
4043 up looking a bit weird if it turns out that there is
4044 no offset. You end up producing code that looks like:
4057 So here we provide the missing zero. */
4059 *displacement_string_end
= '0';
4063 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
);
4064 if (gotfree_input_line
)
4065 input_line_pointer
= gotfree_input_line
;
4068 exp_seg
= expression (exp
);
4071 if (*input_line_pointer
)
4072 as_bad (_("junk `%s' after expression"), input_line_pointer
);
4074 RESTORE_END_STRING (disp_end
+ 1);
4076 RESTORE_END_STRING (disp_end
);
4077 input_line_pointer
= save_input_line_pointer
;
4079 if (gotfree_input_line
)
4080 free (gotfree_input_line
);
4083 /* We do this to make sure that the section symbol is in
4084 the symbol table. We will ultimately change the relocation
4085 to be relative to the beginning of the section. */
4086 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
4087 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
4089 if (exp
->X_op
!= O_symbol
)
4091 as_bad (_("bad expression used with @%s"),
4092 (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
4098 if (S_IS_LOCAL (exp
->X_add_symbol
)
4099 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
4100 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
4101 exp
->X_op
= O_subtract
;
4102 exp
->X_op_symbol
= GOT_symbol
;
4103 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
4104 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
4106 i
.reloc
[this_operand
] = BFD_RELOC_32
;
4109 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
4111 /* Missing or bad expr becomes absolute 0. */
4112 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
4114 exp
->X_op
= O_constant
;
4115 exp
->X_add_number
= 0;
4116 exp
->X_add_symbol
= (symbolS
*) 0;
4117 exp
->X_op_symbol
= (symbolS
*) 0;
4120 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4121 if (exp
->X_op
!= O_constant
4122 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
4123 && exp_seg
!= absolute_section
4124 && exp_seg
!= text_section
4125 && exp_seg
!= data_section
4126 && exp_seg
!= bss_section
4127 && exp_seg
!= undefined_section
4128 && !bfd_is_com_section (exp_seg
))
4130 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
4134 else if (flag_code
== CODE_64BIT
)
4135 i
.types
[this_operand
] |= Disp32S
| Disp32
;
4139 static int i386_index_check
PARAMS ((const char *));
4141 /* Make sure the memory operand we've been dealt is valid.
4142 Return 1 on success, 0 on a failure. */
4145 i386_index_check (operand_string
)
4146 const char *operand_string
;
4149 #if INFER_ADDR_PREFIX
4155 if (flag_code
== CODE_64BIT
)
4157 unsigned RegXX
= (i
.prefix
[ADDR_PREFIX
] == 0 ? Reg64
: Reg32
);
4160 && ((i
.base_reg
->reg_type
& RegXX
) == 0)
4161 && (i
.base_reg
->reg_type
!= BaseIndex
4164 && ((i
.index_reg
->reg_type
& (RegXX
| BaseIndex
))
4165 != (RegXX
| BaseIndex
))))
4170 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
4174 && ((i
.base_reg
->reg_type
& (Reg16
| BaseIndex
| RegRex
))
4175 != (Reg16
| BaseIndex
)))
4177 && (((i
.index_reg
->reg_type
& (Reg16
| BaseIndex
))
4178 != (Reg16
| BaseIndex
))
4180 && i
.base_reg
->reg_num
< 6
4181 && i
.index_reg
->reg_num
>= 6
4182 && i
.log2_scale_factor
== 0))))
4189 && (i
.base_reg
->reg_type
& (Reg32
| RegRex
)) != Reg32
)
4191 && ((i
.index_reg
->reg_type
& (Reg32
| BaseIndex
| RegRex
))
4192 != (Reg32
| BaseIndex
))))
4198 #if INFER_ADDR_PREFIX
4199 if (i
.prefix
[ADDR_PREFIX
] == 0)
4201 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
4203 /* Change the size of any displacement too. At most one of
4204 Disp16 or Disp32 is set.
4205 FIXME. There doesn't seem to be any real need for separate
4206 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
4207 Removing them would probably clean up the code quite a lot. */
4208 if (flag_code
!= CODE_64BIT
&& (i
.types
[this_operand
] & (Disp16
| Disp32
)))
4209 i
.types
[this_operand
] ^= (Disp16
| Disp32
);
4214 as_bad (_("`%s' is not a valid base/index expression"),
4218 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4220 flag_code_names
[flag_code
]);
4225 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
4229 i386_operand (operand_string
)
4230 char *operand_string
;
4234 char *op_string
= operand_string
;
4236 if (is_space_char (*op_string
))
4239 /* We check for an absolute prefix (differentiating,
4240 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
4241 if (*op_string
== ABSOLUTE_PREFIX
)
4244 if (is_space_char (*op_string
))
4246 i
.types
[this_operand
] |= JumpAbsolute
;
4249 /* Check if operand is a register. */
4250 if ((*op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
4251 && (r
= parse_register (op_string
, &end_op
)) != NULL
)
4253 /* Check for a segment override by searching for ':' after a
4254 segment register. */
4256 if (is_space_char (*op_string
))
4258 if (*op_string
== ':' && (r
->reg_type
& (SReg2
| SReg3
)))
4263 i
.seg
[i
.mem_operands
] = &es
;
4266 i
.seg
[i
.mem_operands
] = &cs
;
4269 i
.seg
[i
.mem_operands
] = &ss
;
4272 i
.seg
[i
.mem_operands
] = &ds
;
4275 i
.seg
[i
.mem_operands
] = &fs
;
4278 i
.seg
[i
.mem_operands
] = &gs
;
4282 /* Skip the ':' and whitespace. */
4284 if (is_space_char (*op_string
))
4287 if (!is_digit_char (*op_string
)
4288 && !is_identifier_char (*op_string
)
4289 && *op_string
!= '('
4290 && *op_string
!= ABSOLUTE_PREFIX
)
4292 as_bad (_("bad memory operand `%s'"), op_string
);
4295 /* Handle case of %es:*foo. */
4296 if (*op_string
== ABSOLUTE_PREFIX
)
4299 if (is_space_char (*op_string
))
4301 i
.types
[this_operand
] |= JumpAbsolute
;
4303 goto do_memory_reference
;
4307 as_bad (_("junk `%s' after register"), op_string
);
4310 i
.types
[this_operand
] |= r
->reg_type
& ~BaseIndex
;
4311 i
.op
[this_operand
].regs
= r
;
4314 else if (*op_string
== REGISTER_PREFIX
)
4316 as_bad (_("bad register name `%s'"), op_string
);
4319 else if (*op_string
== IMMEDIATE_PREFIX
)
4322 if (i
.types
[this_operand
] & JumpAbsolute
)
4324 as_bad (_("immediate operand illegal with absolute jump"));
4327 if (!i386_immediate (op_string
))
4330 else if (is_digit_char (*op_string
)
4331 || is_identifier_char (*op_string
)
4332 || *op_string
== '(')
4334 /* This is a memory reference of some sort. */
4337 /* Start and end of displacement string expression (if found). */
4338 char *displacement_string_start
;
4339 char *displacement_string_end
;
4341 do_memory_reference
:
4342 if ((i
.mem_operands
== 1
4343 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
4344 || i
.mem_operands
== 2)
4346 as_bad (_("too many memory references for `%s'"),
4347 current_templates
->start
->name
);
4351 /* Check for base index form. We detect the base index form by
4352 looking for an ')' at the end of the operand, searching
4353 for the '(' matching it, and finding a REGISTER_PREFIX or ','
4355 base_string
= op_string
+ strlen (op_string
);
4358 if (is_space_char (*base_string
))
4361 /* If we only have a displacement, set-up for it to be parsed later. */
4362 displacement_string_start
= op_string
;
4363 displacement_string_end
= base_string
+ 1;
4365 if (*base_string
== ')')
4368 unsigned int parens_balanced
= 1;
4369 /* We've already checked that the number of left & right ()'s are
4370 equal, so this loop will not be infinite. */
4374 if (*base_string
== ')')
4376 if (*base_string
== '(')
4379 while (parens_balanced
);
4381 temp_string
= base_string
;
4383 /* Skip past '(' and whitespace. */
4385 if (is_space_char (*base_string
))
4388 if (*base_string
== ','
4389 || ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
4390 && (i
.base_reg
= parse_register (base_string
, &end_op
)) != NULL
))
4392 displacement_string_end
= temp_string
;
4394 i
.types
[this_operand
] |= BaseIndex
;
4398 base_string
= end_op
;
4399 if (is_space_char (*base_string
))
4403 /* There may be an index reg or scale factor here. */
4404 if (*base_string
== ',')
4407 if (is_space_char (*base_string
))
4410 if ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
4411 && (i
.index_reg
= parse_register (base_string
, &end_op
)) != NULL
)
4413 base_string
= end_op
;
4414 if (is_space_char (*base_string
))
4416 if (*base_string
== ',')
4419 if (is_space_char (*base_string
))
4422 else if (*base_string
!= ')')
4424 as_bad (_("expecting `,' or `)' after index register in `%s'"),
4429 else if (*base_string
== REGISTER_PREFIX
)
4431 as_bad (_("bad register name `%s'"), base_string
);
4435 /* Check for scale factor. */
4436 if (*base_string
!= ')')
4438 char *end_scale
= i386_scale (base_string
);
4443 base_string
= end_scale
;
4444 if (is_space_char (*base_string
))
4446 if (*base_string
!= ')')
4448 as_bad (_("expecting `)' after scale factor in `%s'"),
4453 else if (!i
.index_reg
)
4455 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
4460 else if (*base_string
!= ')')
4462 as_bad (_("expecting `,' or `)' after base register in `%s'"),
4467 else if (*base_string
== REGISTER_PREFIX
)
4469 as_bad (_("bad register name `%s'"), base_string
);
4474 /* If there's an expression beginning the operand, parse it,
4475 assuming displacement_string_start and
4476 displacement_string_end are meaningful. */
4477 if (displacement_string_start
!= displacement_string_end
)
4479 if (!i386_displacement (displacement_string_start
,
4480 displacement_string_end
))
4484 /* Special case for (%dx) while doing input/output op. */
4486 && i
.base_reg
->reg_type
== (Reg16
| InOutPortReg
)
4488 && i
.log2_scale_factor
== 0
4489 && i
.seg
[i
.mem_operands
] == 0
4490 && (i
.types
[this_operand
] & Disp
) == 0)
4492 i
.types
[this_operand
] = InOutPortReg
;
4496 if (i386_index_check (operand_string
) == 0)
4502 /* It's not a memory operand; argh! */
4503 as_bad (_("invalid char %s beginning operand %d `%s'"),
4504 output_invalid (*op_string
),
4509 return 1; /* Normal return. */
4512 /* md_estimate_size_before_relax()
4514 Called just before relax() for rs_machine_dependent frags. The x86
4515 assembler uses these frags to handle variable size jump
4518 Any symbol that is now undefined will not become defined.
4519 Return the correct fr_subtype in the frag.
4520 Return the initial "guess for variable size of frag" to caller.
4521 The guess is actually the growth beyond the fixed part. Whatever
4522 we do to grow the fixed or variable part contributes to our
4526 md_estimate_size_before_relax (fragP
, segment
)
4530 /* We've already got fragP->fr_subtype right; all we have to do is
4531 check for un-relaxable symbols. On an ELF system, we can't relax
4532 an externally visible symbol, because it may be overridden by a
4534 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
4535 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4536 || (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4537 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
4538 || S_IS_WEAK (fragP
->fr_symbol
)))
4542 /* Symbol is undefined in this segment, or we need to keep a
4543 reloc so that weak symbols can be overridden. */
4544 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
4545 enum bfd_reloc_code_real reloc_type
;
4546 unsigned char *opcode
;
4549 if (fragP
->fr_var
!= NO_RELOC
)
4550 reloc_type
= fragP
->fr_var
;
4552 reloc_type
= BFD_RELOC_16_PCREL
;
4554 reloc_type
= BFD_RELOC_32_PCREL
;
4556 old_fr_fix
= fragP
->fr_fix
;
4557 opcode
= (unsigned char *) fragP
->fr_opcode
;
4559 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
4562 /* Make jmp (0xeb) a (d)word displacement jump. */
4564 fragP
->fr_fix
+= size
;
4565 fix_new (fragP
, old_fr_fix
, size
,
4567 fragP
->fr_offset
, 1,
4573 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
4575 /* Negate the condition, and branch past an
4576 unconditional jump. */
4579 /* Insert an unconditional jump. */
4581 /* We added two extra opcode bytes, and have a two byte
4583 fragP
->fr_fix
+= 2 + 2;
4584 fix_new (fragP
, old_fr_fix
+ 2, 2,
4586 fragP
->fr_offset
, 1,
4593 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
4598 fixP
= fix_new (fragP
, old_fr_fix
, 1,
4600 fragP
->fr_offset
, 1,
4602 fixP
->fx_signed
= 1;
4606 /* This changes the byte-displacement jump 0x7N
4607 to the (d)word-displacement jump 0x0f,0x8N. */
4608 opcode
[1] = opcode
[0] + 0x10;
4609 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4610 /* We've added an opcode byte. */
4611 fragP
->fr_fix
+= 1 + size
;
4612 fix_new (fragP
, old_fr_fix
+ 1, size
,
4614 fragP
->fr_offset
, 1,
4619 BAD_CASE (fragP
->fr_subtype
);
4623 return fragP
->fr_fix
- old_fr_fix
;
4626 /* Guess size depending on current relax state. Initially the relax
4627 state will correspond to a short jump and we return 1, because
4628 the variable part of the frag (the branch offset) is one byte
4629 long. However, we can relax a section more than once and in that
4630 case we must either set fr_subtype back to the unrelaxed state,
4631 or return the value for the appropriate branch. */
4632 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
4635 /* Called after relax() is finished.
4637 In: Address of frag.
4638 fr_type == rs_machine_dependent.
4639 fr_subtype is what the address relaxed to.
4641 Out: Any fixSs and constants are set up.
4642 Caller will turn frag into a ".space 0". */
4645 md_convert_frag (abfd
, sec
, fragP
)
4646 bfd
*abfd ATTRIBUTE_UNUSED
;
4647 segT sec ATTRIBUTE_UNUSED
;
4650 unsigned char *opcode
;
4651 unsigned char *where_to_put_displacement
= NULL
;
4652 offsetT target_address
;
4653 offsetT opcode_address
;
4654 unsigned int extension
= 0;
4655 offsetT displacement_from_opcode_start
;
4657 opcode
= (unsigned char *) fragP
->fr_opcode
;
4659 /* Address we want to reach in file space. */
4660 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
4662 /* Address opcode resides at in file space. */
4663 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
4665 /* Displacement from opcode start to fill into instruction. */
4666 displacement_from_opcode_start
= target_address
- opcode_address
;
4668 if ((fragP
->fr_subtype
& BIG
) == 0)
4670 /* Don't have to change opcode. */
4671 extension
= 1; /* 1 opcode + 1 displacement */
4672 where_to_put_displacement
= &opcode
[1];
4676 if (no_cond_jump_promotion
4677 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
4678 as_warn_where (fragP
->fr_file
, fragP
->fr_line
, _("long jump required"));
4680 switch (fragP
->fr_subtype
)
4682 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
4683 extension
= 4; /* 1 opcode + 4 displacement */
4685 where_to_put_displacement
= &opcode
[1];
4688 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
4689 extension
= 2; /* 1 opcode + 2 displacement */
4691 where_to_put_displacement
= &opcode
[1];
4694 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
4695 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
4696 extension
= 5; /* 2 opcode + 4 displacement */
4697 opcode
[1] = opcode
[0] + 0x10;
4698 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4699 where_to_put_displacement
= &opcode
[2];
4702 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
4703 extension
= 3; /* 2 opcode + 2 displacement */
4704 opcode
[1] = opcode
[0] + 0x10;
4705 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4706 where_to_put_displacement
= &opcode
[2];
4709 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
4714 where_to_put_displacement
= &opcode
[3];
4718 BAD_CASE (fragP
->fr_subtype
);
4723 /* Now put displacement after opcode. */
4724 md_number_to_chars ((char *) where_to_put_displacement
,
4725 (valueT
) (displacement_from_opcode_start
- extension
),
4726 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
4727 fragP
->fr_fix
+= extension
;
4730 /* Size of byte displacement jmp. */
4731 int md_short_jump_size
= 2;
4733 /* Size of dword displacement jmp. */
4734 int md_long_jump_size
= 5;
4736 /* Size of relocation record. */
4737 const int md_reloc_size
= 8;
4740 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4742 addressT from_addr
, to_addr
;
4743 fragS
*frag ATTRIBUTE_UNUSED
;
4744 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4748 offset
= to_addr
- (from_addr
+ 2);
4749 /* Opcode for byte-disp jump. */
4750 md_number_to_chars (ptr
, (valueT
) 0xeb, 1);
4751 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 1);
4755 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4757 addressT from_addr
, to_addr
;
4758 fragS
*frag ATTRIBUTE_UNUSED
;
4759 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4763 offset
= to_addr
- (from_addr
+ 5);
4764 md_number_to_chars (ptr
, (valueT
) 0xe9, 1);
4765 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 4);
4768 /* Apply a fixup (fixS) to segment data, once it has been determined
4769 by our caller that we have all the info we need to fix it up.
4771 On the 386, immediates, displacements, and data pointers are all in
4772 the same (little-endian) format, so we don't need to care about which
4776 md_apply_fix3 (fixP
, valP
, seg
)
4777 /* The fix we're to put in. */
4779 /* Pointer to the value of the bits. */
4781 /* Segment fix is from. */
4782 segT seg ATTRIBUTE_UNUSED
;
4784 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
4785 valueT value
= *valP
;
4787 #if !defined (TE_Mach)
4790 switch (fixP
->fx_r_type
)
4796 case BFD_RELOC_X86_64_32S
:
4797 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
4800 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
4803 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
4808 if (fixP
->fx_addsy
!= NULL
4809 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
4810 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
4811 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
4812 && !use_rela_relocations
)
4814 /* This is a hack. There should be a better way to handle this.
4815 This covers for the fact that bfd_install_relocation will
4816 subtract the current location (for partial_inplace, PC relative
4817 relocations); see more below. */
4819 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4821 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
4824 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4826 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4827 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
4829 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
4832 || (symbol_section_p (fixP
->fx_addsy
)
4833 && sym_seg
!= absolute_section
))
4834 && !generic_force_reloc (fixP
))
4836 /* Yes, we add the values in twice. This is because
4837 bfd_install_relocation subtracts them out again. I think
4838 bfd_install_relocation is broken, but I don't dare change
4840 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4844 #if defined (OBJ_COFF) && defined (TE_PE)
4845 /* For some reason, the PE format does not store a
4846 section address offset for a PC relative symbol. */
4847 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
4848 #if defined(BFD_ASSEMBLER) || defined(S_IS_WEAK)
4849 || S_IS_WEAK (fixP
->fx_addsy
)
4852 value
+= md_pcrel_from (fixP
);
4856 /* Fix a few things - the dynamic linker expects certain values here,
4857 and we must not disappoint it. */
4858 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4859 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4861 switch (fixP
->fx_r_type
)
4863 case BFD_RELOC_386_PLT32
:
4864 case BFD_RELOC_X86_64_PLT32
:
4865 /* Make the jump instruction point to the address of the operand. At
4866 runtime we merely add the offset to the actual PLT entry. */
4870 case BFD_RELOC_386_TLS_GD
:
4871 case BFD_RELOC_386_TLS_LDM
:
4872 case BFD_RELOC_386_TLS_IE_32
:
4873 case BFD_RELOC_386_TLS_IE
:
4874 case BFD_RELOC_386_TLS_GOTIE
:
4875 case BFD_RELOC_X86_64_TLSGD
:
4876 case BFD_RELOC_X86_64_TLSLD
:
4877 case BFD_RELOC_X86_64_GOTTPOFF
:
4878 value
= 0; /* Fully resolved at runtime. No addend. */
4880 case BFD_RELOC_386_TLS_LE
:
4881 case BFD_RELOC_386_TLS_LDO_32
:
4882 case BFD_RELOC_386_TLS_LE_32
:
4883 case BFD_RELOC_X86_64_DTPOFF32
:
4884 case BFD_RELOC_X86_64_TPOFF32
:
4885 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
4888 case BFD_RELOC_386_GOT32
:
4889 case BFD_RELOC_X86_64_GOT32
:
4890 value
= 0; /* Fully resolved at runtime. No addend. */
4893 case BFD_RELOC_VTABLE_INHERIT
:
4894 case BFD_RELOC_VTABLE_ENTRY
:
4901 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
4903 #endif /* !defined (TE_Mach) */
4905 /* Are we finished with this relocation now? */
4906 if (fixP
->fx_addsy
== NULL
)
4908 else if (use_rela_relocations
)
4910 fixP
->fx_no_overflow
= 1;
4911 /* Remember value for tc_gen_reloc. */
4912 fixP
->fx_addnumber
= value
;
4916 md_number_to_chars (p
, value
, fixP
->fx_size
);
4919 #define MAX_LITTLENUMS 6
4921 /* Turn the string pointed to by litP into a floating point constant
4922 of type TYPE, and emit the appropriate bytes. The number of
4923 LITTLENUMS emitted is stored in *SIZEP. An error message is
4924 returned, or NULL on OK. */
4927 md_atof (type
, litP
, sizeP
)
4933 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4934 LITTLENUM_TYPE
*wordP
;
4956 return _("Bad call to md_atof ()");
4958 t
= atof_ieee (input_line_pointer
, type
, words
);
4960 input_line_pointer
= t
;
4962 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
4963 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
4964 the bigendian 386. */
4965 for (wordP
= words
+ prec
- 1; prec
--;)
4967 md_number_to_chars (litP
, (valueT
) (*wordP
--), sizeof (LITTLENUM_TYPE
));
4968 litP
+= sizeof (LITTLENUM_TYPE
);
4973 char output_invalid_buf
[8];
4980 sprintf (output_invalid_buf
, "'%c'", c
);
4982 sprintf (output_invalid_buf
, "(0x%x)", (unsigned) c
);
4983 return output_invalid_buf
;
4986 /* REG_STRING starts *before* REGISTER_PREFIX. */
4988 static const reg_entry
*
4989 parse_register (reg_string
, end_op
)
4993 char *s
= reg_string
;
4995 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
4998 /* Skip possible REGISTER_PREFIX and possible whitespace. */
4999 if (*s
== REGISTER_PREFIX
)
5002 if (is_space_char (*s
))
5006 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
5008 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
5009 return (const reg_entry
*) NULL
;
5013 /* For naked regs, make sure that we are not dealing with an identifier.
5014 This prevents confusing an identifier like `eax_var' with register
5016 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
5017 return (const reg_entry
*) NULL
;
5021 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
5023 /* Handle floating point regs, allowing spaces in the (i) part. */
5024 if (r
== i386_regtab
/* %st is first entry of table */)
5026 if (is_space_char (*s
))
5031 if (is_space_char (*s
))
5033 if (*s
>= '0' && *s
<= '7')
5035 r
= &i386_float_regtab
[*s
- '0'];
5037 if (is_space_char (*s
))
5045 /* We have "%st(" then garbage. */
5046 return (const reg_entry
*) NULL
;
5051 && ((r
->reg_flags
& (RegRex64
| RegRex
)) | (r
->reg_type
& Reg64
)) != 0
5052 && (r
->reg_type
!= Control
|| !(cpu_arch_flags
& CpuSledgehammer
))
5053 && flag_code
!= CODE_64BIT
)
5054 return (const reg_entry
*) NULL
;
5059 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5060 const char *md_shortopts
= "kVQ:sqn";
5062 const char *md_shortopts
= "qn";
5065 struct option md_longopts
[] = {
5066 #define OPTION_32 (OPTION_MD_BASE + 0)
5067 {"32", no_argument
, NULL
, OPTION_32
},
5068 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5069 #define OPTION_64 (OPTION_MD_BASE + 1)
5070 {"64", no_argument
, NULL
, OPTION_64
},
5072 {NULL
, no_argument
, NULL
, 0}
5074 size_t md_longopts_size
= sizeof (md_longopts
);
5077 md_parse_option (c
, arg
)
5079 char *arg ATTRIBUTE_UNUSED
;
5084 optimize_align_code
= 0;
5091 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5092 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5093 should be emitted or not. FIXME: Not implemented. */
5097 /* -V: SVR4 argument to print version ID. */
5099 print_version_id ();
5102 /* -k: Ignore for FreeBSD compatibility. */
5107 /* -s: On i386 Solaris, this tells the native assembler to use
5108 .stab instead of .stab.excl. We always use .stab anyhow. */
5113 const char **list
, **l
;
5115 list
= bfd_target_list ();
5116 for (l
= list
; *l
!= NULL
; l
++)
5117 if (strcmp (*l
, "elf64-x86-64") == 0)
5119 default_arch
= "x86_64";
5123 as_fatal (_("No compiled in support for x86_64"));
5130 default_arch
= "i386";
5140 md_show_usage (stream
)
5143 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5144 fprintf (stream
, _("\
5146 -V print assembler version number\n\
5148 -n Do not optimize code alignment\n\
5149 -q quieten some warnings\n\
5152 fprintf (stream
, _("\
5153 -n Do not optimize code alignment\n\
5154 -q quieten some warnings\n"));
5158 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
5159 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5161 /* Pick the target format to use. */
5164 i386_target_format ()
5166 if (!strcmp (default_arch
, "x86_64"))
5167 set_code_flag (CODE_64BIT
);
5168 else if (!strcmp (default_arch
, "i386"))
5169 set_code_flag (CODE_32BIT
);
5171 as_fatal (_("Unknown architecture"));
5172 switch (OUTPUT_FLAVOR
)
5174 #ifdef OBJ_MAYBE_AOUT
5175 case bfd_target_aout_flavour
:
5176 return AOUT_TARGET_FORMAT
;
5178 #ifdef OBJ_MAYBE_COFF
5179 case bfd_target_coff_flavour
:
5182 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
5183 case bfd_target_elf_flavour
:
5185 if (flag_code
== CODE_64BIT
)
5186 use_rela_relocations
= 1;
5187 return flag_code
== CODE_64BIT
? "elf64-x86-64" : ELF_TARGET_FORMAT
;
5196 #endif /* OBJ_MAYBE_ more than one */
5198 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5199 void i386_elf_emit_arch_note ()
5201 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
5202 && cpu_arch_name
!= NULL
)
5205 asection
*seg
= now_seg
;
5206 subsegT subseg
= now_subseg
;
5207 Elf_Internal_Note i_note
;
5208 Elf_External_Note e_note
;
5209 asection
*note_secp
;
5212 /* Create the .note section. */
5213 note_secp
= subseg_new (".note", 0);
5214 bfd_set_section_flags (stdoutput
,
5216 SEC_HAS_CONTENTS
| SEC_READONLY
);
5218 /* Process the arch string. */
5219 len
= strlen (cpu_arch_name
);
5221 i_note
.namesz
= len
+ 1;
5223 i_note
.type
= NT_ARCH
;
5224 p
= frag_more (sizeof (e_note
.namesz
));
5225 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
5226 p
= frag_more (sizeof (e_note
.descsz
));
5227 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
5228 p
= frag_more (sizeof (e_note
.type
));
5229 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
5230 p
= frag_more (len
+ 1);
5231 strcpy (p
, cpu_arch_name
);
5233 frag_align (2, 0, 0);
5235 subseg_set (seg
, subseg
);
5241 md_undefined_symbol (name
)
5244 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
5245 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
5246 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
5247 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
5251 if (symbol_find (name
))
5252 as_bad (_("GOT already in symbol table"));
5253 GOT_symbol
= symbol_new (name
, undefined_section
,
5254 (valueT
) 0, &zero_address_frag
);
5261 /* Round up a section size to the appropriate boundary. */
5264 md_section_align (segment
, size
)
5265 segT segment ATTRIBUTE_UNUSED
;
5268 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5269 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
5271 /* For a.out, force the section size to be aligned. If we don't do
5272 this, BFD will align it for us, but it will not write out the
5273 final bytes of the section. This may be a bug in BFD, but it is
5274 easier to fix it here since that is how the other a.out targets
5278 align
= bfd_get_section_alignment (stdoutput
, segment
);
5279 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
5286 /* On the i386, PC-relative offsets are relative to the start of the
5287 next instruction. That is, the address of the offset, plus its
5288 size, since the offset is always the last part of the insn. */
5291 md_pcrel_from (fixP
)
5294 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5301 int ignore ATTRIBUTE_UNUSED
;
5305 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5307 obj_elf_section_change_hook ();
5309 temp
= get_absolute_expression ();
5310 subseg_set (bss_section
, (subsegT
) temp
);
5311 demand_empty_rest_of_line ();
5317 i386_validate_fix (fixp
)
5320 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
5322 /* GOTOFF relocation are nonsense in 64bit mode. */
5323 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
5325 if (flag_code
!= CODE_64BIT
)
5327 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
5331 if (flag_code
== CODE_64BIT
)
5333 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
5340 tc_gen_reloc (section
, fixp
)
5341 asection
*section ATTRIBUTE_UNUSED
;
5345 bfd_reloc_code_real_type code
;
5347 switch (fixp
->fx_r_type
)
5349 case BFD_RELOC_X86_64_PLT32
:
5350 case BFD_RELOC_X86_64_GOT32
:
5351 case BFD_RELOC_X86_64_GOTPCREL
:
5352 case BFD_RELOC_386_PLT32
:
5353 case BFD_RELOC_386_GOT32
:
5354 case BFD_RELOC_386_GOTOFF
:
5355 case BFD_RELOC_386_GOTPC
:
5356 case BFD_RELOC_386_TLS_GD
:
5357 case BFD_RELOC_386_TLS_LDM
:
5358 case BFD_RELOC_386_TLS_LDO_32
:
5359 case BFD_RELOC_386_TLS_IE_32
:
5360 case BFD_RELOC_386_TLS_IE
:
5361 case BFD_RELOC_386_TLS_GOTIE
:
5362 case BFD_RELOC_386_TLS_LE_32
:
5363 case BFD_RELOC_386_TLS_LE
:
5364 case BFD_RELOC_X86_64_TLSGD
:
5365 case BFD_RELOC_X86_64_TLSLD
:
5366 case BFD_RELOC_X86_64_DTPOFF32
:
5367 case BFD_RELOC_X86_64_GOTTPOFF
:
5368 case BFD_RELOC_X86_64_TPOFF32
:
5370 case BFD_RELOC_VTABLE_ENTRY
:
5371 case BFD_RELOC_VTABLE_INHERIT
:
5373 case BFD_RELOC_32_SECREL
:
5375 code
= fixp
->fx_r_type
;
5377 case BFD_RELOC_X86_64_32S
:
5378 if (!fixp
->fx_pcrel
)
5380 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
5381 code
= fixp
->fx_r_type
;
5387 switch (fixp
->fx_size
)
5390 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5391 _("can not do %d byte pc-relative relocation"),
5393 code
= BFD_RELOC_32_PCREL
;
5395 case 1: code
= BFD_RELOC_8_PCREL
; break;
5396 case 2: code
= BFD_RELOC_16_PCREL
; break;
5397 case 4: code
= BFD_RELOC_32_PCREL
; break;
5402 switch (fixp
->fx_size
)
5405 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5406 _("can not do %d byte relocation"),
5408 code
= BFD_RELOC_32
;
5410 case 1: code
= BFD_RELOC_8
; break;
5411 case 2: code
= BFD_RELOC_16
; break;
5412 case 4: code
= BFD_RELOC_32
; break;
5414 case 8: code
= BFD_RELOC_64
; break;
5421 if (code
== BFD_RELOC_32
5423 && fixp
->fx_addsy
== GOT_symbol
)
5425 /* We don't support GOTPC on 64bit targets. */
5426 if (flag_code
== CODE_64BIT
)
5428 code
= BFD_RELOC_386_GOTPC
;
5431 rel
= (arelent
*) xmalloc (sizeof (arelent
));
5432 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
5433 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
5435 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5437 if (!use_rela_relocations
)
5439 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
5440 vtable entry to be used in the relocation's section offset. */
5441 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5442 rel
->address
= fixp
->fx_offset
;
5446 /* Use the rela in 64bit mode. */
5449 if (!fixp
->fx_pcrel
)
5450 rel
->addend
= fixp
->fx_offset
;
5454 case BFD_RELOC_X86_64_PLT32
:
5455 case BFD_RELOC_X86_64_GOT32
:
5456 case BFD_RELOC_X86_64_GOTPCREL
:
5457 case BFD_RELOC_X86_64_TLSGD
:
5458 case BFD_RELOC_X86_64_TLSLD
:
5459 case BFD_RELOC_X86_64_GOTTPOFF
:
5460 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
5463 rel
->addend
= (section
->vma
5465 + fixp
->fx_addnumber
5466 + md_pcrel_from (fixp
));
5471 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
5472 if (rel
->howto
== NULL
)
5474 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5475 _("cannot represent relocation type %s"),
5476 bfd_get_reloc_code_name (code
));
5477 /* Set howto to a garbage value so that we can keep going. */
5478 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
5479 assert (rel
->howto
!= NULL
);
5486 /* Parse operands using Intel syntax. This implements a recursive descent
5487 parser based on the BNF grammar published in Appendix B of the MASM 6.1
5490 FIXME: We do not recognize the full operand grammar defined in the MASM
5491 documentation. In particular, all the structure/union and
5492 high-level macro operands are missing.
5494 Uppercase words are terminals, lower case words are non-terminals.
5495 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
5496 bars '|' denote choices. Most grammar productions are implemented in
5497 functions called 'intel_<production>'.
5499 Initial production is 'expr'.
5505 binOp & | AND | \| | OR | ^ | XOR
5507 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
5509 constant digits [[ radixOverride ]]
5511 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
5549 => expr expr cmpOp e04
5552 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
5553 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
5555 hexdigit a | b | c | d | e | f
5556 | A | B | C | D | E | F
5562 mulOp * | / | % | MOD | << | SHL | >> | SHR
5566 register specialRegister
5570 segmentRegister CS | DS | ES | FS | GS | SS
5572 specialRegister CR0 | CR2 | CR3 | CR4
5573 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
5574 | TR3 | TR4 | TR5 | TR6 | TR7
5576 We simplify the grammar in obvious places (e.g., register parsing is
5577 done by calling parse_register) and eliminate immediate left recursion
5578 to implement a recursive-descent parser.
5582 expr' cmpOp e04 expr'
5633 /* Parsing structure for the intel syntax parser. Used to implement the
5634 semantic actions for the operand grammar. */
5635 struct intel_parser_s
5637 char *op_string
; /* The string being parsed. */
5638 int got_a_float
; /* Whether the operand is a float. */
5639 int op_modifier
; /* Operand modifier. */
5640 int is_mem
; /* 1 if operand is memory reference. */
5641 int in_offset
; /* >=1 if parsing operand of offset. */
5642 int in_bracket
; /* >=1 if parsing operand in brackets. */
5643 const reg_entry
*reg
; /* Last register reference found. */
5644 char *disp
; /* Displacement string being built. */
5645 char *next_operand
; /* Resume point when splitting operands. */
5648 static struct intel_parser_s intel_parser
;
5650 /* Token structure for parsing intel syntax. */
5653 int code
; /* Token code. */
5654 const reg_entry
*reg
; /* Register entry for register tokens. */
5655 char *str
; /* String representation. */
5658 static struct intel_token cur_token
, prev_token
;
5660 /* Token codes for the intel parser. Since T_SHORT is already used
5661 by COFF, undefine it first to prevent a warning. */
5680 /* Prototypes for intel parser functions. */
5681 static int intel_match_token
PARAMS ((int code
));
5682 static void intel_get_token
PARAMS ((void));
5683 static void intel_putback_token
PARAMS ((void));
5684 static int intel_expr
PARAMS ((void));
5685 static int intel_e04
PARAMS ((void));
5686 static int intel_e05
PARAMS ((void));
5687 static int intel_e06
PARAMS ((void));
5688 static int intel_e09
PARAMS ((void));
5689 static int intel_bracket_expr
PARAMS ((void));
5690 static int intel_e10
PARAMS ((void));
5691 static int intel_e11
PARAMS ((void));
5694 i386_intel_operand (operand_string
, got_a_float
)
5695 char *operand_string
;
5701 p
= intel_parser
.op_string
= xstrdup (operand_string
);
5702 intel_parser
.disp
= (char *) xmalloc (strlen (operand_string
) + 1);
5706 /* Initialize token holders. */
5707 cur_token
.code
= prev_token
.code
= T_NIL
;
5708 cur_token
.reg
= prev_token
.reg
= NULL
;
5709 cur_token
.str
= prev_token
.str
= NULL
;
5711 /* Initialize parser structure. */
5712 intel_parser
.got_a_float
= got_a_float
;
5713 intel_parser
.op_modifier
= 0;
5714 intel_parser
.is_mem
= 0;
5715 intel_parser
.in_offset
= 0;
5716 intel_parser
.in_bracket
= 0;
5717 intel_parser
.reg
= NULL
;
5718 intel_parser
.disp
[0] = '\0';
5719 intel_parser
.next_operand
= NULL
;
5721 /* Read the first token and start the parser. */
5723 ret
= intel_expr ();
5728 if (cur_token
.code
!= T_NIL
)
5730 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
5731 current_templates
->start
->name
, cur_token
.str
);
5734 /* If we found a memory reference, hand it over to i386_displacement
5735 to fill in the rest of the operand fields. */
5736 else if (intel_parser
.is_mem
)
5738 if ((i
.mem_operands
== 1
5739 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
5740 || i
.mem_operands
== 2)
5742 as_bad (_("too many memory references for '%s'"),
5743 current_templates
->start
->name
);
5748 char *s
= intel_parser
.disp
;
5751 if (!quiet_warnings
&& intel_parser
.is_mem
< 0)
5752 /* See the comments in intel_bracket_expr. */
5753 as_warn (_("Treating `%s' as memory reference"), operand_string
);
5755 /* Add the displacement expression. */
5757 ret
= i386_displacement (s
, s
+ strlen (s
));
5760 /* Swap base and index in 16-bit memory operands like
5761 [si+bx]. Since i386_index_check is also used in AT&T
5762 mode we have to do that here. */
5765 && (i
.base_reg
->reg_type
& Reg16
)
5766 && (i
.index_reg
->reg_type
& Reg16
)
5767 && i
.base_reg
->reg_num
>= 6
5768 && i
.index_reg
->reg_num
< 6)
5770 const reg_entry
*base
= i
.index_reg
;
5772 i
.index_reg
= i
.base_reg
;
5775 ret
= i386_index_check (operand_string
);
5780 /* Constant and OFFSET expressions are handled by i386_immediate. */
5781 else if ((intel_parser
.op_modifier
& (1 << T_OFFSET
))
5782 || intel_parser
.reg
== NULL
)
5783 ret
= i386_immediate (intel_parser
.disp
);
5785 if (intel_parser
.next_operand
&& this_operand
>= MAX_OPERANDS
- 1)
5787 if (!ret
|| !intel_parser
.next_operand
)
5789 intel_parser
.op_string
= intel_parser
.next_operand
;
5790 this_operand
= i
.operands
++;
5794 free (intel_parser
.disp
);
5799 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
5803 expr' cmpOp e04 expr'
5808 /* XXX Implement the comparison operators. */
5809 return intel_e04 ();
5826 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
5827 i
.base_reg
= i386_regtab
+ REGNAM_AL
; /* al is invalid as base */
5829 if (cur_token
.code
== '+')
5831 else if (cur_token
.code
== '-')
5832 nregs
= NUM_ADDRESS_REGS
;
5836 strcat (intel_parser
.disp
, cur_token
.str
);
5837 intel_match_token (cur_token
.code
);
5848 int nregs
= ~NUM_ADDRESS_REGS
;
5855 if (cur_token
.code
== '&' || cur_token
.code
== '|' || cur_token
.code
== '^')
5859 str
[0] = cur_token
.code
;
5861 strcat (intel_parser
.disp
, str
);
5866 intel_match_token (cur_token
.code
);
5871 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
5872 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 1; /* cl is invalid as base */
5883 int nregs
= ~NUM_ADDRESS_REGS
;
5890 if (cur_token
.code
== '*' || cur_token
.code
== '/' || cur_token
.code
== '%')
5894 str
[0] = cur_token
.code
;
5896 strcat (intel_parser
.disp
, str
);
5898 else if (cur_token
.code
== T_SHL
)
5899 strcat (intel_parser
.disp
, "<<");
5900 else if (cur_token
.code
== T_SHR
)
5901 strcat (intel_parser
.disp
, ">>");
5905 intel_match_token (cur_token
.code
);
5910 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
5911 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 2; /* dl is invalid as base */
5929 int nregs
= ~NUM_ADDRESS_REGS
;
5934 /* Don't consume constants here. */
5935 if (cur_token
.code
== '+' || cur_token
.code
== '-')
5937 /* Need to look one token ahead - if the next token
5938 is a constant, the current token is its sign. */
5941 intel_match_token (cur_token
.code
);
5942 next_code
= cur_token
.code
;
5943 intel_putback_token ();
5944 if (next_code
== T_CONST
)
5948 /* e09 OFFSET e09 */
5949 if (cur_token
.code
== T_OFFSET
)
5952 ++intel_parser
.in_offset
;
5956 else if (cur_token
.code
== T_SHORT
)
5957 intel_parser
.op_modifier
|= 1 << T_SHORT
;
5960 else if (cur_token
.code
== '+')
5961 strcat (intel_parser
.disp
, "+");
5966 else if (cur_token
.code
== '-' || cur_token
.code
== '~')
5972 str
[0] = cur_token
.code
;
5974 strcat (intel_parser
.disp
, str
);
5981 intel_match_token (cur_token
.code
);
5989 /* e09' PTR e10 e09' */
5990 if (cur_token
.code
== T_PTR
)
5994 if (prev_token
.code
== T_BYTE
)
5995 suffix
= BYTE_MNEM_SUFFIX
;
5997 else if (prev_token
.code
== T_WORD
)
5999 if (current_templates
->start
->name
[0] == 'l'
6000 && current_templates
->start
->name
[2] == 's'
6001 && current_templates
->start
->name
[3] == 0)
6002 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
6003 else if (intel_parser
.got_a_float
== 2) /* "fi..." */
6004 suffix
= SHORT_MNEM_SUFFIX
;
6006 suffix
= WORD_MNEM_SUFFIX
;
6009 else if (prev_token
.code
== T_DWORD
)
6011 if (current_templates
->start
->name
[0] == 'l'
6012 && current_templates
->start
->name
[2] == 's'
6013 && current_templates
->start
->name
[3] == 0)
6014 suffix
= WORD_MNEM_SUFFIX
;
6015 else if (flag_code
== CODE_16BIT
6016 && (current_templates
->start
->opcode_modifier
6017 & (Jump
|JumpDword
|JumpInterSegment
)))
6018 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
6019 else if (intel_parser
.got_a_float
== 1) /* "f..." */
6020 suffix
= SHORT_MNEM_SUFFIX
;
6022 suffix
= LONG_MNEM_SUFFIX
;
6025 else if (prev_token
.code
== T_FWORD
)
6027 if (current_templates
->start
->name
[0] == 'l'
6028 && current_templates
->start
->name
[2] == 's'
6029 && current_templates
->start
->name
[3] == 0)
6030 suffix
= LONG_MNEM_SUFFIX
;
6031 else if (!intel_parser
.got_a_float
)
6033 if (flag_code
== CODE_16BIT
)
6034 add_prefix (DATA_PREFIX_OPCODE
);
6035 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
6038 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
6041 else if (prev_token
.code
== T_QWORD
)
6043 if (intel_parser
.got_a_float
== 1) /* "f..." */
6044 suffix
= LONG_MNEM_SUFFIX
;
6046 suffix
= QWORD_MNEM_SUFFIX
;
6049 else if (prev_token
.code
== T_TBYTE
)
6051 if (intel_parser
.got_a_float
== 1)
6052 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
6054 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
6057 else if (prev_token
.code
== T_XMMWORD
)
6059 /* XXX ignored for now, but accepted since gcc uses it */
6065 as_bad (_("Unknown operand modifier `%s'"), prev_token
.str
);
6069 if (current_templates
->start
->base_opcode
== 0x8d /* lea */)
6073 else if (i
.suffix
!= suffix
)
6075 as_bad (_("Conflicting operand modifiers"));
6081 /* e09' : e10 e09' */
6082 else if (cur_token
.code
== ':')
6084 if (prev_token
.code
!= T_REG
)
6086 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
6087 segment/group identifier (which we don't have), using comma
6088 as the operand separator there is even less consistent, since
6089 there all branches only have a single operand. */
6090 if (this_operand
!= 0
6091 || intel_parser
.in_offset
6092 || intel_parser
.in_bracket
6093 || (!(current_templates
->start
->opcode_modifier
6094 & (Jump
|JumpDword
|JumpInterSegment
))
6095 && !(current_templates
->start
->operand_types
[0]
6097 return intel_match_token (T_NIL
);
6098 /* Remember the start of the 2nd operand and terminate 1st
6100 XXX This isn't right, yet (when SSSS:OOOO is right operand of
6101 another expression), but it gets at least the simplest case
6102 (a plain number or symbol on the left side) right. */
6103 intel_parser
.next_operand
= intel_parser
.op_string
;
6104 *--intel_parser
.op_string
= '\0';
6105 return intel_match_token (':');
6113 intel_match_token (cur_token
.code
);
6119 --intel_parser
.in_offset
;
6122 if (NUM_ADDRESS_REGS
> nregs
)
6124 as_bad (_("Invalid operand to `OFFSET'"));
6127 intel_parser
.op_modifier
|= 1 << T_OFFSET
;
6130 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
6131 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 3; /* bl is invalid as base */
6136 intel_bracket_expr ()
6138 int was_offset
= intel_parser
.op_modifier
& (1 << T_OFFSET
);
6139 const char *start
= intel_parser
.op_string
;
6142 if (i
.op
[this_operand
].regs
)
6143 return intel_match_token (T_NIL
);
6145 intel_match_token ('[');
6147 /* Mark as a memory operand only if it's not already known to be an
6148 offset expression. If it's an offset expression, we need to keep
6150 if (!intel_parser
.in_offset
)
6152 ++intel_parser
.in_bracket
;
6153 /* Unfortunately gas always diverged from MASM in a respect that can't
6154 be easily fixed without risking to break code sequences likely to be
6155 encountered (the testsuite even check for this): MASM doesn't consider
6156 an expression inside brackets unconditionally as a memory reference.
6157 When that is e.g. a constant, an offset expression, or the sum of the
6158 two, this is still taken as a constant load. gas, however, always
6159 treated these as memory references. As a compromise, we'll try to make
6160 offset expressions inside brackets work the MASM way (since that's
6161 less likely to be found in real world code), but make constants alone
6162 continue to work the traditional gas way. In either case, issue a
6164 intel_parser
.op_modifier
&= ~was_offset
;
6167 strcat (intel_parser
.disp
, "[");
6169 /* Add a '+' to the displacement string if necessary. */
6170 if (*intel_parser
.disp
!= '\0'
6171 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
6172 strcat (intel_parser
.disp
, "+");
6175 && (len
= intel_parser
.op_string
- start
- 1,
6176 intel_match_token (']')))
6178 /* Preserve brackets when the operand is an offset expression. */
6179 if (intel_parser
.in_offset
)
6180 strcat (intel_parser
.disp
, "]");
6183 --intel_parser
.in_bracket
;
6184 if (i
.base_reg
|| i
.index_reg
)
6185 intel_parser
.is_mem
= 1;
6186 if (!intel_parser
.is_mem
)
6188 if (!(intel_parser
.op_modifier
& (1 << T_OFFSET
)))
6189 /* Defer the warning until all of the operand was parsed. */
6190 intel_parser
.is_mem
= -1;
6191 else if (!quiet_warnings
)
6192 as_warn (_("`[%.*s]' taken to mean just `%.*s'"), len
, start
, len
, start
);
6195 intel_parser
.op_modifier
|= was_offset
;
6212 while (cur_token
.code
== '[')
6214 if (!intel_bracket_expr ())
6239 switch (cur_token
.code
)
6243 intel_match_token ('(');
6244 strcat (intel_parser
.disp
, "(");
6246 if (intel_expr () && intel_match_token (')'))
6248 strcat (intel_parser
.disp
, ")");
6255 /* Operands for jump/call inside brackets denote absolute addresses.
6256 XXX This shouldn't be needed anymore (or if it should rather live
6257 in intel_bracket_expr). */
6258 if (current_templates
->start
->opcode_modifier
6259 & (Jump
|JumpDword
|JumpByte
|JumpInterSegment
))
6260 i
.types
[this_operand
] |= JumpAbsolute
;
6262 return intel_bracket_expr ();
6267 strcat (intel_parser
.disp
, cur_token
.str
);
6268 intel_match_token (cur_token
.code
);
6270 /* Mark as a memory operand only if it's not already known to be an
6271 offset expression. */
6272 if (!intel_parser
.in_offset
)
6273 intel_parser
.is_mem
= 1;
6280 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
6282 intel_match_token (T_REG
);
6284 /* Check for segment change. */
6285 if (cur_token
.code
== ':')
6287 if (!(reg
->reg_type
& (SReg2
| SReg3
)))
6289 as_bad (_("`%s' is not a valid segment register"), reg
->reg_name
);
6292 else if (i
.seg
[i
.mem_operands
])
6293 as_warn (_("Extra segment override ignored"));
6296 if (!intel_parser
.in_offset
)
6297 intel_parser
.is_mem
= 1;
6298 switch (reg
->reg_num
)
6301 i
.seg
[i
.mem_operands
] = &es
;
6304 i
.seg
[i
.mem_operands
] = &cs
;
6307 i
.seg
[i
.mem_operands
] = &ss
;
6310 i
.seg
[i
.mem_operands
] = &ds
;
6313 i
.seg
[i
.mem_operands
] = &fs
;
6316 i
.seg
[i
.mem_operands
] = &gs
;
6322 /* Not a segment register. Check for register scaling. */
6323 else if (cur_token
.code
== '*')
6325 if (!intel_parser
.in_bracket
)
6327 as_bad (_("Register scaling only allowed in memory operands"));
6331 if (reg
->reg_type
& Reg16
) /* Disallow things like [si*1]. */
6332 reg
= i386_regtab
+ REGNAM_AX
+ 4; /* sp is invalid as index */
6333 else if (i
.index_reg
)
6334 reg
= i386_regtab
+ REGNAM_EAX
+ 4; /* esp is invalid as index */
6336 /* What follows must be a valid scale. */
6337 intel_match_token ('*');
6339 i
.types
[this_operand
] |= BaseIndex
;
6341 /* Set the scale after setting the register (otherwise,
6342 i386_scale will complain) */
6343 if (cur_token
.code
== '+' || cur_token
.code
== '-')
6345 char *str
, sign
= cur_token
.code
;
6346 intel_match_token (cur_token
.code
);
6347 if (cur_token
.code
!= T_CONST
)
6349 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
6353 str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
6354 strcpy (str
+ 1, cur_token
.str
);
6356 if (!i386_scale (str
))
6360 else if (!i386_scale (cur_token
.str
))
6362 intel_match_token (cur_token
.code
);
6365 /* No scaling. If this is a memory operand, the register is either a
6366 base register (first occurrence) or an index register (second
6368 else if (intel_parser
.in_bracket
&& !(reg
->reg_type
& (SReg2
| SReg3
)))
6373 else if (!i
.index_reg
)
6377 as_bad (_("Too many register references in memory operand"));
6381 i
.types
[this_operand
] |= BaseIndex
;
6384 /* Offset modifier. Add the register to the displacement string to be
6385 parsed as an immediate expression after we're done. */
6386 else if (intel_parser
.in_offset
)
6388 as_warn (_("Using register names in OFFSET expressions is deprecated"));
6389 strcat (intel_parser
.disp
, reg
->reg_name
);
6392 /* It's neither base nor index nor offset. */
6393 else if (!intel_parser
.is_mem
)
6395 i
.types
[this_operand
] |= reg
->reg_type
& ~BaseIndex
;
6396 i
.op
[this_operand
].regs
= reg
;
6401 as_bad (_("Invalid use of register"));
6405 /* Since registers are not part of the displacement string (except
6406 when we're parsing offset operands), we may need to remove any
6407 preceding '+' from the displacement string. */
6408 if (*intel_parser
.disp
!= '\0'
6409 && !intel_parser
.in_offset
)
6411 char *s
= intel_parser
.disp
;
6412 s
+= strlen (s
) - 1;
6435 intel_match_token (cur_token
.code
);
6437 if (cur_token
.code
== T_PTR
)
6440 /* It must have been an identifier. */
6441 intel_putback_token ();
6442 cur_token
.code
= T_ID
;
6448 if (!intel_parser
.in_offset
&& intel_parser
.is_mem
<= 0)
6452 /* The identifier represents a memory reference only if it's not
6453 preceded by an offset modifier and if it's not an equate. */
6454 symbolP
= symbol_find(cur_token
.str
);
6455 if (!symbolP
|| S_GET_SEGMENT(symbolP
) != absolute_section
)
6456 intel_parser
.is_mem
= 1;
6464 char *save_str
, sign
= 0;
6466 /* Allow constants that start with `+' or `-'. */
6467 if (cur_token
.code
== '-' || cur_token
.code
== '+')
6469 sign
= cur_token
.code
;
6470 intel_match_token (cur_token
.code
);
6471 if (cur_token
.code
!= T_CONST
)
6473 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
6479 save_str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
6480 strcpy (save_str
+ !!sign
, cur_token
.str
);
6484 /* Get the next token to check for register scaling. */
6485 intel_match_token (cur_token
.code
);
6487 /* Check if this constant is a scaling factor for an index register. */
6488 if (cur_token
.code
== '*')
6490 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
6492 const reg_entry
*reg
= cur_token
.reg
;
6494 if (!intel_parser
.in_bracket
)
6496 as_bad (_("Register scaling only allowed in memory operands"));
6500 if (reg
->reg_type
& Reg16
) /* Disallow things like [1*si]. */
6501 reg
= i386_regtab
+ REGNAM_AX
+ 4; /* sp is invalid as index */
6502 else if (i
.index_reg
)
6503 reg
= i386_regtab
+ REGNAM_EAX
+ 4; /* esp is invalid as index */
6505 /* The constant is followed by `* reg', so it must be
6508 i
.types
[this_operand
] |= BaseIndex
;
6510 /* Set the scale after setting the register (otherwise,
6511 i386_scale will complain) */
6512 if (!i386_scale (save_str
))
6514 intel_match_token (T_REG
);
6516 /* Since registers are not part of the displacement
6517 string, we may need to remove any preceding '+' from
6518 the displacement string. */
6519 if (*intel_parser
.disp
!= '\0')
6521 char *s
= intel_parser
.disp
;
6522 s
+= strlen (s
) - 1;
6532 /* The constant was not used for register scaling. Since we have
6533 already consumed the token following `*' we now need to put it
6534 back in the stream. */
6535 intel_putback_token ();
6538 /* Add the constant to the displacement string. */
6539 strcat (intel_parser
.disp
, save_str
);
6546 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
6550 /* Match the given token against cur_token. If they match, read the next
6551 token from the operand string. */
6553 intel_match_token (code
)
6556 if (cur_token
.code
== code
)
6563 as_bad (_("Unexpected token `%s'"), cur_token
.str
);
6568 /* Read a new token from intel_parser.op_string and store it in cur_token. */
6573 const reg_entry
*reg
;
6574 struct intel_token new_token
;
6576 new_token
.code
= T_NIL
;
6577 new_token
.reg
= NULL
;
6578 new_token
.str
= NULL
;
6580 /* Free the memory allocated to the previous token and move
6581 cur_token to prev_token. */
6583 free (prev_token
.str
);
6585 prev_token
= cur_token
;
6587 /* Skip whitespace. */
6588 while (is_space_char (*intel_parser
.op_string
))
6589 intel_parser
.op_string
++;
6591 /* Return an empty token if we find nothing else on the line. */
6592 if (*intel_parser
.op_string
== '\0')
6594 cur_token
= new_token
;
6598 /* The new token cannot be larger than the remainder of the operand
6600 new_token
.str
= (char *) xmalloc (strlen (intel_parser
.op_string
) + 1);
6601 new_token
.str
[0] = '\0';
6603 if (strchr ("0123456789", *intel_parser
.op_string
))
6605 char *p
= new_token
.str
;
6606 char *q
= intel_parser
.op_string
;
6607 new_token
.code
= T_CONST
;
6609 /* Allow any kind of identifier char to encompass floating point and
6610 hexadecimal numbers. */
6611 while (is_identifier_char (*q
))
6615 /* Recognize special symbol names [0-9][bf]. */
6616 if (strlen (intel_parser
.op_string
) == 2
6617 && (intel_parser
.op_string
[1] == 'b'
6618 || intel_parser
.op_string
[1] == 'f'))
6619 new_token
.code
= T_ID
;
6622 else if ((*intel_parser
.op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
6623 && ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
))
6625 new_token
.code
= T_REG
;
6626 new_token
.reg
= reg
;
6628 if (*intel_parser
.op_string
== REGISTER_PREFIX
)
6630 new_token
.str
[0] = REGISTER_PREFIX
;
6631 new_token
.str
[1] = '\0';
6634 strcat (new_token
.str
, reg
->reg_name
);
6637 else if (is_identifier_char (*intel_parser
.op_string
))
6639 char *p
= new_token
.str
;
6640 char *q
= intel_parser
.op_string
;
6642 /* A '.' or '$' followed by an identifier char is an identifier.
6643 Otherwise, it's operator '.' followed by an expression. */
6644 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
6646 new_token
.code
= '.';
6647 new_token
.str
[0] = '.';
6648 new_token
.str
[1] = '\0';
6652 while (is_identifier_char (*q
) || *q
== '@')
6656 if (strcasecmp (new_token
.str
, "NOT") == 0)
6657 new_token
.code
= '~';
6659 else if (strcasecmp (new_token
.str
, "MOD") == 0)
6660 new_token
.code
= '%';
6662 else if (strcasecmp (new_token
.str
, "AND") == 0)
6663 new_token
.code
= '&';
6665 else if (strcasecmp (new_token
.str
, "OR") == 0)
6666 new_token
.code
= '|';
6668 else if (strcasecmp (new_token
.str
, "XOR") == 0)
6669 new_token
.code
= '^';
6671 else if (strcasecmp (new_token
.str
, "SHL") == 0)
6672 new_token
.code
= T_SHL
;
6674 else if (strcasecmp (new_token
.str
, "SHR") == 0)
6675 new_token
.code
= T_SHR
;
6677 else if (strcasecmp (new_token
.str
, "BYTE") == 0)
6678 new_token
.code
= T_BYTE
;
6680 else if (strcasecmp (new_token
.str
, "WORD") == 0)
6681 new_token
.code
= T_WORD
;
6683 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
6684 new_token
.code
= T_DWORD
;
6686 else if (strcasecmp (new_token
.str
, "FWORD") == 0)
6687 new_token
.code
= T_FWORD
;
6689 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
6690 new_token
.code
= T_QWORD
;
6692 else if (strcasecmp (new_token
.str
, "TBYTE") == 0
6693 /* XXX remove (gcc still uses it) */
6694 || strcasecmp (new_token
.str
, "XWORD") == 0)
6695 new_token
.code
= T_TBYTE
;
6697 else if (strcasecmp (new_token
.str
, "XMMWORD") == 0
6698 || strcasecmp (new_token
.str
, "OWORD") == 0)
6699 new_token
.code
= T_XMMWORD
;
6701 else if (strcasecmp (new_token
.str
, "PTR") == 0)
6702 new_token
.code
= T_PTR
;
6704 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
6705 new_token
.code
= T_SHORT
;
6707 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
6709 new_token
.code
= T_OFFSET
;
6711 /* ??? This is not mentioned in the MASM grammar but gcc
6712 makes use of it with -mintel-syntax. OFFSET may be
6713 followed by FLAT: */
6714 if (strncasecmp (q
, " FLAT:", 6) == 0)
6715 strcat (new_token
.str
, " FLAT:");
6718 /* ??? This is not mentioned in the MASM grammar. */
6719 else if (strcasecmp (new_token
.str
, "FLAT") == 0)
6721 new_token
.code
= T_OFFSET
;
6723 strcat (new_token
.str
, ":");
6725 as_bad (_("`:' expected"));
6729 new_token
.code
= T_ID
;
6733 else if (strchr ("+-/*%|&^:[]()~", *intel_parser
.op_string
))
6735 new_token
.code
= *intel_parser
.op_string
;
6736 new_token
.str
[0] = *intel_parser
.op_string
;
6737 new_token
.str
[1] = '\0';
6740 else if (strchr ("<>", *intel_parser
.op_string
)
6741 && *intel_parser
.op_string
== *(intel_parser
.op_string
+ 1))
6743 new_token
.code
= *intel_parser
.op_string
== '<' ? T_SHL
: T_SHR
;
6744 new_token
.str
[0] = *intel_parser
.op_string
;
6745 new_token
.str
[1] = *intel_parser
.op_string
;
6746 new_token
.str
[2] = '\0';
6750 as_bad (_("Unrecognized token `%s'"), intel_parser
.op_string
);
6752 intel_parser
.op_string
+= strlen (new_token
.str
);
6753 cur_token
= new_token
;
6756 /* Put cur_token back into the token stream and make cur_token point to
6759 intel_putback_token ()
6761 if (cur_token
.code
!= T_NIL
)
6763 intel_parser
.op_string
-= strlen (cur_token
.str
);
6764 free (cur_token
.str
);
6766 cur_token
= prev_token
;
6768 /* Forget prev_token. */
6769 prev_token
.code
= T_NIL
;
6770 prev_token
.reg
= NULL
;
6771 prev_token
.str
= NULL
;
6775 tc_x86_regname_to_dw2regnum (const char *regname
)
6777 unsigned int regnum
;
6778 unsigned int regnames_count
;
6779 char *regnames_32
[] =
6781 "eax", "ecx", "edx", "ebx",
6782 "esp", "ebp", "esi", "edi",
6785 char *regnames_64
[] =
6787 "rax", "rbx", "rcx", "rdx",
6788 "rdi", "rsi", "rbp", "rsp",
6789 "r8", "r9", "r10", "r11",
6790 "r12", "r13", "r14", "r15",
6795 if (flag_code
== CODE_64BIT
)
6797 regnames
= regnames_64
;
6798 regnames_count
= ARRAY_SIZE (regnames_64
);
6802 regnames
= regnames_32
;
6803 regnames_count
= ARRAY_SIZE (regnames_32
);
6806 for (regnum
= 0; regnum
< regnames_count
; regnum
++)
6807 if (strcmp (regname
, regnames
[regnum
]) == 0)
6814 tc_x86_frame_initial_instructions (void)
6816 static unsigned int sp_regno
;
6819 sp_regno
= tc_x86_regname_to_dw2regnum (flag_code
== CODE_64BIT
6822 cfi_add_CFA_def_cfa (sp_regno
, -x86_cie_data_alignment
);
6823 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
6827 i386_elf_section_type (const char *str
, size_t len
)
6829 if (flag_code
== CODE_64BIT
6830 && len
== sizeof ("unwind") - 1
6831 && strncmp (str
, "unwind", 6) == 0)
6832 return SHT_X86_64_UNWIND
;
6839 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
6843 expr
.X_op
= O_secrel
;
6844 expr
.X_add_symbol
= symbol
;
6845 expr
.X_add_number
= 0;
6846 emit_expr (&expr
, size
);