1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 Bugs & suggestions are completely welcome. This is free software.
27 Please help us make it better. */
33 #include "dwarf2dbg.h"
34 #include "opcode/i386.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
44 #ifndef SCALE1_WHEN_NO_INDEX
45 /* Specifying a scale factor besides 1 when there is no index is
46 futile. eg. `mov (%ebx,2),%al' does exactly the same as
47 `mov (%ebx),%al'. To slavishly follow what the programmer
48 specified, set SCALE1_WHEN_NO_INDEX to 0. */
49 #define SCALE1_WHEN_NO_INDEX 1
55 static unsigned int mode_from_disp_size
PARAMS ((unsigned int));
56 static int fits_in_signed_byte
PARAMS ((offsetT
));
57 static int fits_in_unsigned_byte
PARAMS ((offsetT
));
58 static int fits_in_unsigned_word
PARAMS ((offsetT
));
59 static int fits_in_signed_word
PARAMS ((offsetT
));
60 static int fits_in_unsigned_long
PARAMS ((offsetT
));
61 static int fits_in_signed_long
PARAMS ((offsetT
));
62 static int smallest_imm_type
PARAMS ((offsetT
));
63 static offsetT offset_in_range
PARAMS ((offsetT
, int));
64 static int add_prefix
PARAMS ((unsigned int));
65 static void set_code_flag
PARAMS ((int));
66 static void set_16bit_gcc_code_flag
PARAMS ((int));
67 static void set_intel_syntax
PARAMS ((int));
68 static void set_cpu_arch
PARAMS ((int));
71 static bfd_reloc_code_real_type reloc
72 PARAMS ((int, int, int, bfd_reloc_code_real_type
));
76 #define DEFAULT_ARCH "i386"
78 static char *default_arch
= DEFAULT_ARCH
;
80 /* 'md_assemble ()' gathers together information and puts it into a
87 const reg_entry
*regs
;
92 /* TM holds the template for the insn were currently assembling. */
95 /* SUFFIX holds the instruction mnemonic suffix if given.
96 (e.g. 'l' for 'movl') */
99 /* OPERANDS gives the number of given operands. */
100 unsigned int operands
;
102 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
103 of given register, displacement, memory operands and immediate
105 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
107 /* TYPES [i] is the type (see above #defines) which tells us how to
108 use OP[i] for the corresponding operand. */
109 unsigned int types
[MAX_OPERANDS
];
111 /* Displacement expression, immediate expression, or register for each
113 union i386_op op
[MAX_OPERANDS
];
115 /* Flags for operands. */
116 unsigned int flags
[MAX_OPERANDS
];
117 #define Operand_PCrel 1
119 /* Relocation type for operand */
121 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
123 int reloc
[MAX_OPERANDS
];
126 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
127 the base index byte below. */
128 const reg_entry
*base_reg
;
129 const reg_entry
*index_reg
;
130 unsigned int log2_scale_factor
;
132 /* SEG gives the seg_entries of this insn. They are zero unless
133 explicit segment overrides are given. */
134 const seg_entry
*seg
[2];
136 /* PREFIX holds all the given prefix opcodes (usually null).
137 PREFIXES is the number of prefix opcodes. */
138 unsigned int prefixes
;
139 unsigned char prefix
[MAX_PREFIXES
];
141 /* RM and SIB are the modrm byte and the sib byte where the
142 addressing modes of this insn are encoded. */
149 typedef struct _i386_insn i386_insn
;
151 /* List of chars besides those in app.c:symbol_chars that can start an
152 operand. Used to prevent the scrubber eating vital white-space. */
154 const char extra_symbol_chars
[] = "*%-(@";
156 const char extra_symbol_chars
[] = "*%-(";
159 /* This array holds the chars that always start a comment. If the
160 pre-processor is disabled, these aren't very useful. */
161 #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD))
162 /* Putting '/' here makes it impossible to use the divide operator.
163 However, we need it for compatibility with SVR4 systems. */
164 const char comment_chars
[] = "#/";
165 #define PREFIX_SEPARATOR '\\'
167 const char comment_chars
[] = "#";
168 #define PREFIX_SEPARATOR '/'
171 /* This array holds the chars that only start a comment at the beginning of
172 a line. If the line seems to have the form '# 123 filename'
173 .line and .file directives will appear in the pre-processed output.
174 Note that input_file.c hand checks for '#' at the beginning of the
175 first line of the input file. This is because the compiler outputs
176 #NO_APP at the beginning of its output.
177 Also note that comments started like this one will always work if
178 '/' isn't otherwise defined. */
179 #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD))
180 const char line_comment_chars
[] = "";
182 const char line_comment_chars
[] = "/";
185 const char line_separator_chars
[] = ";";
187 /* Chars that can be used to separate mant from exp in floating point
189 const char EXP_CHARS
[] = "eE";
191 /* Chars that mean this number is a floating point constant
194 const char FLT_CHARS
[] = "fFdDxX";
196 /* Tables for lexical analysis. */
197 static char mnemonic_chars
[256];
198 static char register_chars
[256];
199 static char operand_chars
[256];
200 static char identifier_chars
[256];
201 static char digit_chars
[256];
203 /* Lexical macros. */
204 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
205 #define is_operand_char(x) (operand_chars[(unsigned char) x])
206 #define is_register_char(x) (register_chars[(unsigned char) x])
207 #define is_space_char(x) ((x) == ' ')
208 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
209 #define is_digit_char(x) (digit_chars[(unsigned char) x])
211 /* All non-digit non-letter charcters that may occur in an operand. */
212 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
214 /* md_assemble() always leaves the strings it's passed unaltered. To
215 effect this we maintain a stack of saved characters that we've smashed
216 with '\0's (indicating end of strings for various sub-fields of the
217 assembler instruction). */
218 static char save_stack
[32];
219 static char *save_stack_p
;
220 #define END_STRING_AND_SAVE(s) \
221 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
222 #define RESTORE_END_STRING(s) \
223 do { *(s) = *--save_stack_p; } while (0)
225 /* The instruction we're assembling. */
228 /* Possible templates for current insn. */
229 static const templates
*current_templates
;
231 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
232 static expressionS disp_expressions
[2], im_expressions
[2];
234 /* Current operand we are working on. */
235 static int this_operand
;
237 /* We support four different modes. FLAG_CODE variable is used to distinguish
245 static enum flag_code flag_code
;
246 static int use_rela_relocations
= 0;
248 /* The names used to print error messages. */
249 static const char *flag_code_names
[] =
256 /* 1 for intel syntax,
258 static int intel_syntax
= 0;
260 /* 1 if register prefix % not required. */
261 static int allow_naked_reg
= 0;
263 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
264 leave, push, and pop instructions so that gcc has the same stack
265 frame as in 32 bit mode. */
266 static char stackop_size
= '\0';
268 /* Non-zero to quieten some warnings. */
269 static int quiet_warnings
= 0;
272 static const char *cpu_arch_name
= NULL
;
274 /* CPU feature flags. */
275 static unsigned int cpu_arch_flags
= CpuUnknownFlags
|CpuNo64
;
277 /* If set, conditional jumps are not automatically promoted to handle
278 larger than a byte offset. */
279 static unsigned int no_cond_jump_promotion
= 0;
281 /* Interface to relax_segment.
282 There are 3 major relax states for 386 jump insns because the
283 different types of jumps add different sizes to frags when we're
284 figuring out what sort of jump to choose to reach a given label. */
287 #define UNCOND_JUMP 1
289 #define COND_JUMP86 3
294 #define SMALL16 (SMALL|CODE16)
296 #define BIG16 (BIG|CODE16)
300 #define INLINE __inline__
306 #define ENCODE_RELAX_STATE(type, size) \
307 ((relax_substateT) (((type) << 2) | (size)))
308 #define TYPE_FROM_RELAX_STATE(s) \
310 #define DISP_SIZE_FROM_RELAX_STATE(s) \
311 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
313 /* This table is used by relax_frag to promote short jumps to long
314 ones where necessary. SMALL (short) jumps may be promoted to BIG
315 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
316 don't allow a short jump in a 32 bit code segment to be promoted to
317 a 16 bit offset jump because it's slower (requires data size
318 prefix), and doesn't work, unless the destination is in the bottom
319 64k of the code segment (The top 16 bits of eip are zeroed). */
321 const relax_typeS md_relax_table
[] =
324 1) most positive reach of this state,
325 2) most negative reach of this state,
326 3) how many bytes this mode will add to the size of the current frag
327 4) which index into the table to try if we can't fit into this one. */
333 /* UNCOND_JUMP states. */
334 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
335 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
336 /* dword jmp adds 3 bytes to frag:
337 0 extra opcode bytes, 3 extra displacement bytes. */
339 /* word jmp adds 1 byte to frag:
340 0 extra opcode bytes, 1 extra displacement byte. */
343 /* COND_JUMP states. */
344 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
345 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
346 /* dword conditionals adds 4 bytes to frag:
347 1 extra opcode byte, 3 extra displacement bytes. */
349 /* word conditionals add 2 bytes to frag:
350 1 extra opcode byte, 1 extra displacement byte. */
353 /* COND_JUMP86 states. */
354 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
355 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
356 /* dword conditionals adds 4 bytes to frag:
357 1 extra opcode byte, 3 extra displacement bytes. */
359 /* word conditionals add 3 bytes to frag:
360 1 extra opcode byte, 2 extra displacement bytes. */
364 static const arch_entry cpu_arch
[] = {
366 {"i186", Cpu086
|Cpu186
},
367 {"i286", Cpu086
|Cpu186
|Cpu286
},
368 {"i386", Cpu086
|Cpu186
|Cpu286
|Cpu386
},
369 {"i486", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
},
370 {"i586", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
371 {"i686", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
372 {"pentium", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
373 {"pentiumpro",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
374 {"pentium4", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuSSE
|CpuSSE2
},
375 {"k6", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
|Cpu3dnow
},
376 {"athlon", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuMMX
|Cpu3dnow
},
377 {"sledgehammer",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuSledgehammer
|CpuMMX
|Cpu3dnow
|CpuSSE
|CpuSSE2
},
382 i386_align_code (fragP
, count
)
386 /* Various efficient no-op patterns for aligning code labels.
387 Note: Don't try to assemble the instructions in the comments.
388 0L and 0w are not legal. */
389 static const char f32_1
[] =
391 static const char f32_2
[] =
392 {0x89,0xf6}; /* movl %esi,%esi */
393 static const char f32_3
[] =
394 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
395 static const char f32_4
[] =
396 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
397 static const char f32_5
[] =
399 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
400 static const char f32_6
[] =
401 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
402 static const char f32_7
[] =
403 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
404 static const char f32_8
[] =
406 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
407 static const char f32_9
[] =
408 {0x89,0xf6, /* movl %esi,%esi */
409 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
410 static const char f32_10
[] =
411 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
412 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
413 static const char f32_11
[] =
414 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
415 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
416 static const char f32_12
[] =
417 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
418 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
419 static const char f32_13
[] =
420 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
421 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
422 static const char f32_14
[] =
423 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
424 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
425 static const char f32_15
[] =
426 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
427 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
428 static const char f16_3
[] =
429 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
430 static const char f16_4
[] =
431 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
432 static const char f16_5
[] =
434 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
435 static const char f16_6
[] =
436 {0x89,0xf6, /* mov %si,%si */
437 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
438 static const char f16_7
[] =
439 {0x8d,0x74,0x00, /* lea 0(%si),%si */
440 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
441 static const char f16_8
[] =
442 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
443 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
444 static const char *const f32_patt
[] = {
445 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
446 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
, f32_15
448 static const char *const f16_patt
[] = {
449 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
,
450 f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
453 /* ??? We can't use these fillers for x86_64, since they often kills the
454 upper halves. Solve later. */
455 if (flag_code
== CODE_64BIT
)
458 if (count
> 0 && count
<= 15)
460 if (flag_code
== CODE_16BIT
)
462 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
463 f16_patt
[count
- 1], count
);
465 /* Adjust jump offset. */
466 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
469 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
470 f32_patt
[count
- 1], count
);
471 fragP
->fr_var
= count
;
475 static char *output_invalid
PARAMS ((int c
));
476 static int i386_operand
PARAMS ((char *operand_string
));
477 static int i386_intel_operand
PARAMS ((char *operand_string
, int got_a_float
));
478 static const reg_entry
*parse_register
PARAMS ((char *reg_string
,
482 static void s_bss
PARAMS ((int));
485 symbolS
*GOT_symbol
; /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
487 static INLINE
unsigned int
488 mode_from_disp_size (t
)
491 return (t
& Disp8
) ? 1 : (t
& (Disp16
| Disp32
| Disp32S
)) ? 2 : 0;
495 fits_in_signed_byte (num
)
498 return (num
>= -128) && (num
<= 127);
502 fits_in_unsigned_byte (num
)
505 return (num
& 0xff) == num
;
509 fits_in_unsigned_word (num
)
512 return (num
& 0xffff) == num
;
516 fits_in_signed_word (num
)
519 return (-32768 <= num
) && (num
<= 32767);
522 fits_in_signed_long (num
)
523 offsetT num ATTRIBUTE_UNUSED
;
528 return (!(((offsetT
) -1 << 31) & num
)
529 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
531 } /* fits_in_signed_long() */
533 fits_in_unsigned_long (num
)
534 offsetT num ATTRIBUTE_UNUSED
;
539 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
541 } /* fits_in_unsigned_long() */
544 smallest_imm_type (num
)
547 if (cpu_arch_flags
!= (Cpu086
| Cpu186
| Cpu286
| Cpu386
| Cpu486
| CpuNo64
)
548 && !(cpu_arch_flags
& (CpuUnknown
)))
550 /* This code is disabled on the 486 because all the Imm1 forms
551 in the opcode table are slower on the i486. They're the
552 versions with the implicitly specified single-position
553 displacement, which has another syntax if you really want to
556 return Imm1
| Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
;
558 return (fits_in_signed_byte (num
)
559 ? (Imm8S
| Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
560 : fits_in_unsigned_byte (num
)
561 ? (Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
562 : (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
563 ? (Imm16
| Imm32
| Imm32S
| Imm64
)
564 : fits_in_signed_long (num
)
565 ? (Imm32
| Imm32S
| Imm64
)
566 : fits_in_unsigned_long (num
)
572 offset_in_range (val
, size
)
580 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
581 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
582 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
584 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
589 /* If BFD64, sign extend val. */
590 if (!use_rela_relocations
)
591 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
592 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
594 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
596 char buf1
[40], buf2
[40];
598 sprint_value (buf1
, val
);
599 sprint_value (buf2
, val
& mask
);
600 as_warn (_("%s shortened to %s"), buf1
, buf2
);
605 /* Returns 0 if attempting to add a prefix where one from the same
606 class already exists, 1 if non rep/repne added, 2 if rep/repne
615 if (prefix
>= 0x40 && prefix
< 0x50 && flag_code
== CODE_64BIT
)
623 case CS_PREFIX_OPCODE
:
624 case DS_PREFIX_OPCODE
:
625 case ES_PREFIX_OPCODE
:
626 case FS_PREFIX_OPCODE
:
627 case GS_PREFIX_OPCODE
:
628 case SS_PREFIX_OPCODE
:
632 case REPNE_PREFIX_OPCODE
:
633 case REPE_PREFIX_OPCODE
:
636 case LOCK_PREFIX_OPCODE
:
644 case ADDR_PREFIX_OPCODE
:
648 case DATA_PREFIX_OPCODE
:
655 as_bad (_("same type of prefix used twice"));
660 i
.prefix
[q
] = prefix
;
665 set_code_flag (value
)
669 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
670 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
671 if (value
== CODE_64BIT
&& !(cpu_arch_flags
& CpuSledgehammer
))
673 as_bad (_("64bit mode not supported on this CPU."));
675 if (value
== CODE_32BIT
&& !(cpu_arch_flags
& Cpu386
))
677 as_bad (_("32bit mode not supported on this CPU."));
683 set_16bit_gcc_code_flag (new_code_flag
)
686 flag_code
= new_code_flag
;
687 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
688 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
693 set_intel_syntax (syntax_flag
)
696 /* Find out if register prefixing is specified. */
697 int ask_naked_reg
= 0;
700 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
702 char *string
= input_line_pointer
;
703 int e
= get_symbol_end ();
705 if (strcmp (string
, "prefix") == 0)
707 else if (strcmp (string
, "noprefix") == 0)
710 as_bad (_("bad argument to syntax directive."));
711 *input_line_pointer
= e
;
713 demand_empty_rest_of_line ();
715 intel_syntax
= syntax_flag
;
717 if (ask_naked_reg
== 0)
720 allow_naked_reg
= (intel_syntax
721 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
723 /* Conservative default. */
728 allow_naked_reg
= (ask_naked_reg
< 0);
733 int dummy ATTRIBUTE_UNUSED
;
737 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
739 char *string
= input_line_pointer
;
740 int e
= get_symbol_end ();
743 for (i
= 0; cpu_arch
[i
].name
; i
++)
745 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
747 cpu_arch_name
= cpu_arch
[i
].name
;
748 cpu_arch_flags
= (cpu_arch
[i
].flags
749 | (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
));
753 if (!cpu_arch
[i
].name
)
754 as_bad (_("no such architecture: `%s'"), string
);
756 *input_line_pointer
= e
;
759 as_bad (_("missing cpu architecture"));
761 no_cond_jump_promotion
= 0;
762 if (*input_line_pointer
== ','
763 && ! is_end_of_line
[(unsigned char) input_line_pointer
[1]])
765 char *string
= ++input_line_pointer
;
766 int e
= get_symbol_end ();
768 if (strcmp (string
, "nojumps") == 0)
769 no_cond_jump_promotion
= 1;
770 else if (strcmp (string
, "jumps") == 0)
773 as_bad (_("no such architecture modifier: `%s'"), string
);
775 *input_line_pointer
= e
;
778 demand_empty_rest_of_line ();
781 const pseudo_typeS md_pseudo_table
[] =
783 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
784 {"align", s_align_bytes
, 0},
786 {"align", s_align_ptwo
, 0},
788 {"arch", set_cpu_arch
, 0},
792 {"ffloat", float_cons
, 'f'},
793 {"dfloat", float_cons
, 'd'},
794 {"tfloat", float_cons
, 'x'},
796 {"noopt", s_ignore
, 0},
797 {"optim", s_ignore
, 0},
798 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
799 {"code16", set_code_flag
, CODE_16BIT
},
800 {"code32", set_code_flag
, CODE_32BIT
},
801 {"code64", set_code_flag
, CODE_64BIT
},
802 {"intel_syntax", set_intel_syntax
, 1},
803 {"att_syntax", set_intel_syntax
, 0},
804 {"file", dwarf2_directive_file
, 0},
805 {"loc", dwarf2_directive_loc
, 0},
809 /* For interface with expression (). */
810 extern char *input_line_pointer
;
812 /* Hash table for instruction mnemonic lookup. */
813 static struct hash_control
*op_hash
;
815 /* Hash table for register lookup. */
816 static struct hash_control
*reg_hash
;
822 if (!strcmp (default_arch
, "x86_64"))
823 return bfd_mach_x86_64
;
824 else if (!strcmp (default_arch
, "i386"))
825 return bfd_mach_i386_i386
;
827 as_fatal (_("Unknown architecture"));
834 const char *hash_err
;
836 /* Initialize op_hash hash table. */
837 op_hash
= hash_new ();
840 register const template *optab
;
841 register templates
*core_optab
;
843 /* Setup for loop. */
845 core_optab
= (templates
*) xmalloc (sizeof (templates
));
846 core_optab
->start
= optab
;
851 if (optab
->name
== NULL
852 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
854 /* different name --> ship out current template list;
855 add to hash table; & begin anew. */
856 core_optab
->end
= optab
;
857 hash_err
= hash_insert (op_hash
,
862 as_fatal (_("Internal Error: Can't hash %s: %s"),
866 if (optab
->name
== NULL
)
868 core_optab
= (templates
*) xmalloc (sizeof (templates
));
869 core_optab
->start
= optab
;
874 /* Initialize reg_hash hash table. */
875 reg_hash
= hash_new ();
877 register const reg_entry
*regtab
;
879 for (regtab
= i386_regtab
;
880 regtab
< i386_regtab
+ sizeof (i386_regtab
) / sizeof (i386_regtab
[0]);
883 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
885 as_fatal (_("Internal Error: Can't hash %s: %s"),
891 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
896 for (c
= 0; c
< 256; c
++)
901 mnemonic_chars
[c
] = c
;
902 register_chars
[c
] = c
;
903 operand_chars
[c
] = c
;
905 else if (islower (c
))
907 mnemonic_chars
[c
] = c
;
908 register_chars
[c
] = c
;
909 operand_chars
[c
] = c
;
911 else if (isupper (c
))
913 mnemonic_chars
[c
] = tolower (c
);
914 register_chars
[c
] = mnemonic_chars
[c
];
915 operand_chars
[c
] = c
;
918 if (isalpha (c
) || isdigit (c
))
919 identifier_chars
[c
] = c
;
922 identifier_chars
[c
] = c
;
923 operand_chars
[c
] = c
;
928 identifier_chars
['@'] = '@';
930 digit_chars
['-'] = '-';
931 identifier_chars
['_'] = '_';
932 identifier_chars
['.'] = '.';
934 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
935 operand_chars
[(unsigned char) *p
] = *p
;
938 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
939 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
941 record_alignment (text_section
, 2);
942 record_alignment (data_section
, 2);
943 record_alignment (bss_section
, 2);
949 i386_print_statistics (file
)
952 hash_print_statistics (file
, "i386 opcode", op_hash
);
953 hash_print_statistics (file
, "i386 register", reg_hash
);
958 /* Debugging routines for md_assemble. */
959 static void pi
PARAMS ((char *, i386_insn
*));
960 static void pte
PARAMS ((template *));
961 static void pt
PARAMS ((unsigned int));
962 static void pe
PARAMS ((expressionS
*));
963 static void ps
PARAMS ((symbolS
*));
972 fprintf (stdout
, "%s: template ", line
);
974 fprintf (stdout
, " address: base %s index %s scale %x\n",
975 x
->base_reg
? x
->base_reg
->reg_name
: "none",
976 x
->index_reg
? x
->index_reg
->reg_name
: "none",
977 x
->log2_scale_factor
);
978 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
979 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
980 fprintf (stdout
, " sib: base %x index %x scale %x\n",
981 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
982 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
983 x
->rex
.mode64
, x
->rex
.extX
, x
->rex
.extY
, x
->rex
.extZ
);
984 for (i
= 0; i
< x
->operands
; i
++)
986 fprintf (stdout
, " #%d: ", i
+ 1);
988 fprintf (stdout
, "\n");
990 & (Reg
| SReg2
| SReg3
| Control
| Debug
| Test
| RegMMX
| RegXMM
))
991 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
992 if (x
->types
[i
] & Imm
)
994 if (x
->types
[i
] & Disp
)
1004 fprintf (stdout
, " %d operands ", t
->operands
);
1005 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
1006 if (t
->extension_opcode
!= None
)
1007 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
1008 if (t
->opcode_modifier
& D
)
1009 fprintf (stdout
, "D");
1010 if (t
->opcode_modifier
& W
)
1011 fprintf (stdout
, "W");
1012 fprintf (stdout
, "\n");
1013 for (i
= 0; i
< t
->operands
; i
++)
1015 fprintf (stdout
, " #%d type ", i
+ 1);
1016 pt (t
->operand_types
[i
]);
1017 fprintf (stdout
, "\n");
1025 fprintf (stdout
, " operation %d\n", e
->X_op
);
1026 fprintf (stdout
, " add_number %ld (%lx)\n",
1027 (long) e
->X_add_number
, (long) e
->X_add_number
);
1028 if (e
->X_add_symbol
)
1030 fprintf (stdout
, " add_symbol ");
1031 ps (e
->X_add_symbol
);
1032 fprintf (stdout
, "\n");
1036 fprintf (stdout
, " op_symbol ");
1037 ps (e
->X_op_symbol
);
1038 fprintf (stdout
, "\n");
1046 fprintf (stdout
, "%s type %s%s",
1048 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
1049 segment_name (S_GET_SEGMENT (s
)));
1071 { BaseIndex
, "BaseIndex" },
1075 { Disp32S
, "d32s" },
1077 { InOutPortReg
, "InOutPortReg" },
1078 { ShiftCount
, "ShiftCount" },
1079 { Control
, "control reg" },
1080 { Test
, "test reg" },
1081 { Debug
, "debug reg" },
1082 { FloatReg
, "FReg" },
1083 { FloatAcc
, "FAcc" },
1087 { JumpAbsolute
, "Jump Absolute" },
1098 register struct type_name
*ty
;
1100 for (ty
= type_names
; ty
->mask
; ty
++)
1102 fprintf (stdout
, "%s, ", ty
->tname
);
1106 #endif /* DEBUG386 */
1109 tc_i386_force_relocation (fixp
)
1112 #ifdef BFD_ASSEMBLER
1113 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1114 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1119 return fixp
->fx_r_type
== 7;
1123 #ifdef BFD_ASSEMBLER
1125 static bfd_reloc_code_real_type
1126 reloc (size
, pcrel
, sign
, other
)
1130 bfd_reloc_code_real_type other
;
1132 if (other
!= NO_RELOC
)
1138 as_bad (_("There are no unsigned pc-relative relocations"));
1141 case 1: return BFD_RELOC_8_PCREL
;
1142 case 2: return BFD_RELOC_16_PCREL
;
1143 case 4: return BFD_RELOC_32_PCREL
;
1145 as_bad (_("can not do %d byte pc-relative relocation"), size
);
1152 case 4: return BFD_RELOC_X86_64_32S
;
1157 case 1: return BFD_RELOC_8
;
1158 case 2: return BFD_RELOC_16
;
1159 case 4: return BFD_RELOC_32
;
1160 case 8: return BFD_RELOC_64
;
1162 as_bad (_("can not do %s %d byte relocation"),
1163 sign
? "signed" : "unsigned", size
);
1167 return BFD_RELOC_NONE
;
1170 /* Here we decide which fixups can be adjusted to make them relative to
1171 the beginning of the section instead of the symbol. Basically we need
1172 to make sure that the dynamic relocations are done correctly, so in
1173 some cases we force the original symbol to be used. */
1176 tc_i386_fix_adjustable (fixP
)
1179 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1180 /* Prevent all adjustments to global symbols, or else dynamic
1181 linking will not work correctly. */
1182 if (S_IS_EXTERNAL (fixP
->fx_addsy
)
1183 || S_IS_WEAK (fixP
->fx_addsy
))
1186 /* adjust_reloc_syms doesn't know about the GOT. */
1187 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
1188 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
1189 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
1190 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
1191 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
1192 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
1193 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1194 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1199 #define reloc(SIZE,PCREL,SIGN,OTHER) 0
1200 #define BFD_RELOC_16 0
1201 #define BFD_RELOC_32 0
1202 #define BFD_RELOC_16_PCREL 0
1203 #define BFD_RELOC_32_PCREL 0
1204 #define BFD_RELOC_386_PLT32 0
1205 #define BFD_RELOC_386_GOT32 0
1206 #define BFD_RELOC_386_GOTOFF 0
1207 #define BFD_RELOC_X86_64_PLT32 0
1208 #define BFD_RELOC_X86_64_GOT32 0
1209 #define BFD_RELOC_X86_64_GOTPCREL 0
1212 static int intel_float_operand
PARAMS ((char *mnemonic
));
1215 intel_float_operand (mnemonic
)
1218 if (mnemonic
[0] == 'f' && mnemonic
[1] == 'i')
1221 if (mnemonic
[0] == 'f')
1227 /* This is the guts of the machine-dependent assembler. LINE points to a
1228 machine dependent instruction. This function is supposed to emit
1229 the frags/bytes it assembles to. */
1235 /* Points to template once we've found it. */
1238 /* Count the size of the instruction generated. Does not include
1239 variable part of jump insns before relax. */
1244 char mnemonic
[MAX_MNEM_SIZE
];
1246 /* Initialize globals. */
1247 memset (&i
, '\0', sizeof (i
));
1248 for (j
= 0; j
< MAX_OPERANDS
; j
++)
1249 i
.reloc
[j
] = NO_RELOC
;
1250 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
1251 memset (im_expressions
, '\0', sizeof (im_expressions
));
1252 save_stack_p
= save_stack
;
1254 /* First parse an instruction mnemonic & call i386_operand for the operands.
1255 We assume that the scrubber has arranged it so that line[0] is the valid
1256 start of a (possibly prefixed) mnemonic. */
1259 char *token_start
= l
;
1262 /* Non-zero if we found a prefix only acceptable with string insns. */
1263 const char *expecting_string_instruction
= NULL
;
1268 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
1271 if (mnem_p
>= mnemonic
+ sizeof (mnemonic
))
1273 as_bad (_("no such instruction: `%s'"), token_start
);
1278 if (!is_space_char (*l
)
1279 && *l
!= END_OF_INSN
1280 && *l
!= PREFIX_SEPARATOR
)
1282 as_bad (_("invalid character %s in mnemonic"),
1283 output_invalid (*l
));
1286 if (token_start
== l
)
1288 if (*l
== PREFIX_SEPARATOR
)
1289 as_bad (_("expecting prefix; got nothing"));
1291 as_bad (_("expecting mnemonic; got nothing"));
1295 /* Look up instruction (or prefix) via hash table. */
1296 current_templates
= hash_find (op_hash
, mnemonic
);
1298 if (*l
!= END_OF_INSN
1299 && (! is_space_char (*l
) || l
[1] != END_OF_INSN
)
1300 && current_templates
1301 && (current_templates
->start
->opcode_modifier
& IsPrefix
))
1303 /* If we are in 16-bit mode, do not allow addr16 or data16.
1304 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1305 if ((current_templates
->start
->opcode_modifier
& (Size16
| Size32
))
1306 && (((current_templates
->start
->opcode_modifier
& Size32
) != 0)
1307 ^ (flag_code
== CODE_16BIT
)))
1309 as_bad (_("redundant %s prefix"),
1310 current_templates
->start
->name
);
1313 /* Add prefix, checking for repeated prefixes. */
1314 switch (add_prefix (current_templates
->start
->base_opcode
))
1319 expecting_string_instruction
= current_templates
->start
->name
;
1322 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1329 if (!current_templates
)
1331 /* See if we can get a match by trimming off a suffix. */
1334 case WORD_MNEM_SUFFIX
:
1335 case BYTE_MNEM_SUFFIX
:
1336 case QWORD_MNEM_SUFFIX
:
1337 i
.suffix
= mnem_p
[-1];
1339 current_templates
= hash_find (op_hash
, mnemonic
);
1341 case SHORT_MNEM_SUFFIX
:
1342 case LONG_MNEM_SUFFIX
:
1345 i
.suffix
= mnem_p
[-1];
1347 current_templates
= hash_find (op_hash
, mnemonic
);
1355 if (intel_float_operand (mnemonic
))
1356 i
.suffix
= SHORT_MNEM_SUFFIX
;
1358 i
.suffix
= LONG_MNEM_SUFFIX
;
1360 current_templates
= hash_find (op_hash
, mnemonic
);
1364 if (!current_templates
)
1366 as_bad (_("no such instruction: `%s'"), token_start
);
1371 /* Check if instruction is supported on specified architecture. */
1372 if (cpu_arch_flags
!= 0)
1374 if ((current_templates
->start
->cpu_flags
& ~(Cpu64
| CpuNo64
))
1375 & ~(cpu_arch_flags
& ~(Cpu64
| CpuNo64
)))
1377 as_warn (_("`%s' is not supported on `%s'"),
1378 current_templates
->start
->name
, cpu_arch_name
);
1380 else if ((Cpu386
& ~cpu_arch_flags
) && (flag_code
!= CODE_16BIT
))
1382 as_warn (_("use .code16 to ensure correct addressing mode"));
1386 /* Check for rep/repne without a string instruction. */
1387 if (expecting_string_instruction
1388 && !(current_templates
->start
->opcode_modifier
& IsString
))
1390 as_bad (_("expecting string instruction after `%s'"),
1391 expecting_string_instruction
);
1395 /* There may be operands to parse. */
1396 if (*l
!= END_OF_INSN
)
1398 /* 1 if operand is pending after ','. */
1399 unsigned int expecting_operand
= 0;
1401 /* Non-zero if operand parens not balanced. */
1402 unsigned int paren_not_balanced
;
1406 /* Skip optional white space before operand. */
1407 if (is_space_char (*l
))
1409 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
1411 as_bad (_("invalid character %s before operand %d"),
1412 output_invalid (*l
),
1416 token_start
= l
; /* after white space */
1417 paren_not_balanced
= 0;
1418 while (paren_not_balanced
|| *l
!= ',')
1420 if (*l
== END_OF_INSN
)
1422 if (paren_not_balanced
)
1425 as_bad (_("unbalanced parenthesis in operand %d."),
1428 as_bad (_("unbalanced brackets in operand %d."),
1433 break; /* we are done */
1435 else if (!is_operand_char (*l
) && !is_space_char (*l
))
1437 as_bad (_("invalid character %s in operand %d"),
1438 output_invalid (*l
),
1445 ++paren_not_balanced
;
1447 --paren_not_balanced
;
1452 ++paren_not_balanced
;
1454 --paren_not_balanced
;
1458 if (l
!= token_start
)
1459 { /* Yes, we've read in another operand. */
1460 unsigned int operand_ok
;
1461 this_operand
= i
.operands
++;
1462 if (i
.operands
> MAX_OPERANDS
)
1464 as_bad (_("spurious operands; (%d operands/instruction max)"),
1468 /* Now parse operand adding info to 'i' as we go along. */
1469 END_STRING_AND_SAVE (l
);
1473 i386_intel_operand (token_start
,
1474 intel_float_operand (mnemonic
));
1476 operand_ok
= i386_operand (token_start
);
1478 RESTORE_END_STRING (l
);
1484 if (expecting_operand
)
1486 expecting_operand_after_comma
:
1487 as_bad (_("expecting operand after ','; got nothing"));
1492 as_bad (_("expecting operand before ','; got nothing"));
1497 /* Now *l must be either ',' or END_OF_INSN. */
1500 if (*++l
== END_OF_INSN
)
1502 /* Just skip it, if it's \n complain. */
1503 goto expecting_operand_after_comma
;
1505 expecting_operand
= 1;
1508 while (*l
!= END_OF_INSN
);
1512 /* Now we've parsed the mnemonic into a set of templates, and have the
1515 Next, we find a template that matches the given insn,
1516 making sure the overlap of the given operands types is consistent
1517 with the template operand types. */
1519 #define MATCH(overlap, given, template) \
1520 ((overlap & ~JumpAbsolute) \
1521 && ((given) & (BaseIndex|JumpAbsolute)) == ((overlap) & (BaseIndex|JumpAbsolute)))
1523 /* If given types r0 and r1 are registers they must be of the same type
1524 unless the expected operand type register overlap is null.
1525 Note that Acc in a template matches every size of reg. */
1526 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
1527 ( ((g0) & Reg) == 0 || ((g1) & Reg) == 0 || \
1528 ((g0) & Reg) == ((g1) & Reg) || \
1529 ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
1532 register unsigned int overlap0
, overlap1
;
1533 unsigned int overlap2
;
1534 unsigned int found_reverse_match
;
1537 /* All intel opcodes have reversed operands except for "bound" and
1538 "enter". We also don't reverse intersegment "jmp" and "call"
1539 instructions with 2 immediate operands so that the immediate segment
1540 precedes the offset, as it does when in AT&T mode. "enter" and the
1541 intersegment "jmp" and "call" instructions are the only ones that
1542 have two immediate operands. */
1543 if (intel_syntax
&& i
.operands
> 1
1544 && (strcmp (mnemonic
, "bound") != 0)
1545 && !((i
.types
[0] & Imm
) && (i
.types
[1] & Imm
)))
1547 union i386_op temp_op
;
1548 unsigned int temp_type
;
1549 #ifdef BFD_ASSEMBLER
1550 enum bfd_reloc_code_real temp_reloc
;
1557 if (i
.operands
== 2)
1562 else if (i
.operands
== 3)
1567 temp_type
= i
.types
[xchg2
];
1568 i
.types
[xchg2
] = i
.types
[xchg1
];
1569 i
.types
[xchg1
] = temp_type
;
1570 temp_op
= i
.op
[xchg2
];
1571 i
.op
[xchg2
] = i
.op
[xchg1
];
1572 i
.op
[xchg1
] = temp_op
;
1573 temp_reloc
= i
.reloc
[xchg2
];
1574 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
1575 i
.reloc
[xchg1
] = temp_reloc
;
1577 if (i
.mem_operands
== 2)
1579 const seg_entry
*temp_seg
;
1580 temp_seg
= i
.seg
[0];
1581 i
.seg
[0] = i
.seg
[1];
1582 i
.seg
[1] = temp_seg
;
1588 /* Try to ensure constant immediates are represented in the smallest
1590 char guess_suffix
= 0;
1594 guess_suffix
= i
.suffix
;
1595 else if (i
.reg_operands
)
1597 /* Figure out a suffix from the last register operand specified.
1598 We can't do this properly yet, ie. excluding InOutPortReg,
1599 but the following works for instructions with immediates.
1600 In any case, we can't set i.suffix yet. */
1601 for (op
= i
.operands
; --op
>= 0;)
1602 if (i
.types
[op
] & Reg
)
1604 if (i
.types
[op
] & Reg8
)
1605 guess_suffix
= BYTE_MNEM_SUFFIX
;
1606 else if (i
.types
[op
] & Reg16
)
1607 guess_suffix
= WORD_MNEM_SUFFIX
;
1608 else if (i
.types
[op
] & Reg32
)
1609 guess_suffix
= LONG_MNEM_SUFFIX
;
1610 else if (i
.types
[op
] & Reg64
)
1611 guess_suffix
= QWORD_MNEM_SUFFIX
;
1615 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
1616 guess_suffix
= WORD_MNEM_SUFFIX
;
1618 for (op
= i
.operands
; --op
>= 0;)
1619 if (i
.types
[op
] & Imm
)
1621 switch (i
.op
[op
].imms
->X_op
)
1624 /* If a suffix is given, this operand may be shortened. */
1625 switch (guess_suffix
)
1627 case LONG_MNEM_SUFFIX
:
1628 i
.types
[op
] |= Imm32
| Imm64
;
1630 case WORD_MNEM_SUFFIX
:
1631 i
.types
[op
] |= Imm16
| Imm32S
| Imm32
| Imm64
;
1633 case BYTE_MNEM_SUFFIX
:
1634 i
.types
[op
] |= Imm16
| Imm8
| Imm8S
| Imm32S
| Imm32
| Imm64
;
1638 /* If this operand is at most 16 bits, convert it
1639 to a signed 16 bit number before trying to see
1640 whether it will fit in an even smaller size.
1641 This allows a 16-bit operand such as $0xffe0 to
1642 be recognised as within Imm8S range. */
1643 if ((i
.types
[op
] & Imm16
)
1644 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
1646 i
.op
[op
].imms
->X_add_number
=
1647 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
1649 if ((i
.types
[op
] & Imm32
)
1650 && (i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1)) == 0)
1652 i
.op
[op
].imms
->X_add_number
=
1653 (i
.op
[op
].imms
->X_add_number
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
1655 i
.types
[op
] |= smallest_imm_type (i
.op
[op
].imms
->X_add_number
);
1656 /* We must avoid matching of Imm32 templates when 64bit only immediate is available. */
1657 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
1658 i
.types
[op
] &= ~Imm32
;
1663 /* Symbols and expressions. */
1665 /* Convert symbolic operand to proper sizes for matching. */
1666 switch (guess_suffix
)
1668 case QWORD_MNEM_SUFFIX
:
1669 i
.types
[op
] = Imm64
| Imm32S
;
1671 case LONG_MNEM_SUFFIX
:
1672 i
.types
[op
] = Imm32
| Imm64
;
1674 case WORD_MNEM_SUFFIX
:
1675 i
.types
[op
] = Imm16
| Imm32
| Imm64
;
1678 case BYTE_MNEM_SUFFIX
:
1679 i
.types
[op
] = Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
;
1688 if (i
.disp_operands
)
1690 /* Try to use the smallest displacement type too. */
1693 for (op
= i
.operands
; --op
>= 0;)
1694 if ((i
.types
[op
] & Disp
)
1695 && i
.op
[op
].disps
->X_op
== O_constant
)
1697 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
1699 if (i
.types
[op
] & Disp16
)
1701 /* We know this operand is at most 16 bits, so
1702 convert to a signed 16 bit number before trying
1703 to see whether it will fit in an even smaller
1706 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
1708 else if (i
.types
[op
] & Disp32
)
1710 /* We know this operand is at most 32 bits, so convert to a
1711 signed 32 bit number before trying to see whether it will
1712 fit in an even smaller size. */
1713 disp
&= (((offsetT
) 2 << 31) - 1);
1714 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
1716 if (flag_code
== CODE_64BIT
)
1718 if (fits_in_signed_long (disp
))
1719 i
.types
[op
] |= Disp32S
;
1720 if (fits_in_unsigned_long (disp
))
1721 i
.types
[op
] |= Disp32
;
1723 if ((i
.types
[op
] & (Disp32
| Disp32S
| Disp16
))
1724 && fits_in_signed_byte (disp
))
1725 i
.types
[op
] |= Disp8
;
1732 found_reverse_match
= 0;
1733 suffix_check
= (i
.suffix
== BYTE_MNEM_SUFFIX
1735 : (i
.suffix
== WORD_MNEM_SUFFIX
1737 : (i
.suffix
== SHORT_MNEM_SUFFIX
1739 : (i
.suffix
== LONG_MNEM_SUFFIX
1741 : (i
.suffix
== QWORD_MNEM_SUFFIX
1743 : (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
? No_xSuf
: 0))))));
1745 for (t
= current_templates
->start
;
1746 t
< current_templates
->end
;
1749 /* Must have right number of operands. */
1750 if (i
.operands
!= t
->operands
)
1753 /* Check the suffix, except for some instructions in intel mode. */
1754 if ((t
->opcode_modifier
& suffix_check
)
1756 && (t
->opcode_modifier
& IgnoreSize
))
1758 && t
->base_opcode
== 0xd9
1759 && (t
->extension_opcode
== 5 /* 0xd9,5 "fldcw" */
1760 || t
->extension_opcode
== 7))) /* 0xd9,7 "f{n}stcw" */
1763 /* Do not verify operands when there are none. */
1764 else if (!t
->operands
)
1766 if (t
->cpu_flags
& ~cpu_arch_flags
)
1768 /* We've found a match; break out of loop. */
1772 overlap0
= i
.types
[0] & t
->operand_types
[0];
1773 switch (t
->operands
)
1776 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0]))
1781 overlap1
= i
.types
[1] & t
->operand_types
[1];
1782 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0])
1783 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[1])
1784 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
1785 t
->operand_types
[0],
1786 overlap1
, i
.types
[1],
1787 t
->operand_types
[1]))
1789 /* Check if other direction is valid ... */
1790 if ((t
->opcode_modifier
& (D
|FloatD
)) == 0)
1793 /* Try reversing direction of operands. */
1794 overlap0
= i
.types
[0] & t
->operand_types
[1];
1795 overlap1
= i
.types
[1] & t
->operand_types
[0];
1796 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[1])
1797 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[0])
1798 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
1799 t
->operand_types
[1],
1800 overlap1
, i
.types
[1],
1801 t
->operand_types
[0]))
1803 /* Does not match either direction. */
1806 /* found_reverse_match holds which of D or FloatDR
1808 found_reverse_match
= t
->opcode_modifier
& (D
|FloatDR
);
1810 /* Found a forward 2 operand match here. */
1811 else if (t
->operands
== 3)
1813 /* Here we make use of the fact that there are no
1814 reverse match 3 operand instructions, and all 3
1815 operand instructions only need to be checked for
1816 register consistency between operands 2 and 3. */
1817 overlap2
= i
.types
[2] & t
->operand_types
[2];
1818 if (!MATCH (overlap2
, i
.types
[2], t
->operand_types
[2])
1819 || !CONSISTENT_REGISTER_MATCH (overlap1
, i
.types
[1],
1820 t
->operand_types
[1],
1821 overlap2
, i
.types
[2],
1822 t
->operand_types
[2]))
1826 /* Found either forward/reverse 2 or 3 operand match here:
1827 slip through to break. */
1829 if (t
->cpu_flags
& ~cpu_arch_flags
)
1831 found_reverse_match
= 0;
1834 /* We've found a match; break out of loop. */
1837 if (t
== current_templates
->end
)
1839 /* We found no match. */
1840 as_bad (_("suffix or operands invalid for `%s'"),
1841 current_templates
->start
->name
);
1845 if (!quiet_warnings
)
1848 && ((i
.types
[0] & JumpAbsolute
)
1849 != (t
->operand_types
[0] & JumpAbsolute
)))
1851 as_warn (_("indirect %s without `*'"), t
->name
);
1854 if ((t
->opcode_modifier
& (IsPrefix
|IgnoreSize
))
1855 == (IsPrefix
|IgnoreSize
))
1857 /* Warn them that a data or address size prefix doesn't
1858 affect assembly of the next line of code. */
1859 as_warn (_("stand-alone `%s' prefix"), t
->name
);
1863 /* Copy the template we found. */
1865 if (found_reverse_match
)
1867 /* If we found a reverse match we must alter the opcode
1868 direction bit. found_reverse_match holds bits to change
1869 (different for int & float insns). */
1871 i
.tm
.base_opcode
^= found_reverse_match
;
1873 i
.tm
.operand_types
[0] = t
->operand_types
[1];
1874 i
.tm
.operand_types
[1] = t
->operand_types
[0];
1877 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1880 && (i
.tm
.base_opcode
& 0xfffffde0) == 0xdce0)
1881 i
.tm
.base_opcode
^= FloatR
;
1883 if (i
.tm
.opcode_modifier
& FWait
)
1884 if (! add_prefix (FWAIT_OPCODE
))
1887 /* Check string instruction segment overrides. */
1888 if ((i
.tm
.opcode_modifier
& IsString
) != 0 && i
.mem_operands
!= 0)
1890 int mem_op
= (i
.types
[0] & AnyMem
) ? 0 : 1;
1891 if ((i
.tm
.operand_types
[mem_op
] & EsSeg
) != 0)
1893 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
1895 as_bad (_("`%s' operand %d must use `%%es' segment"),
1900 /* There's only ever one segment override allowed per instruction.
1901 This instruction possibly has a legal segment override on the
1902 second operand, so copy the segment to where non-string
1903 instructions store it, allowing common code. */
1904 i
.seg
[0] = i
.seg
[1];
1906 else if ((i
.tm
.operand_types
[mem_op
+ 1] & EsSeg
) != 0)
1908 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
1910 as_bad (_("`%s' operand %d must use `%%es' segment"),
1918 if (i
.reg_operands
&& flag_code
< CODE_64BIT
)
1921 for (op
= i
.operands
; --op
>= 0;)
1922 if ((i
.types
[op
] & Reg
)
1923 && (i
.op
[op
].regs
->reg_flags
& (RegRex64
|RegRex
)))
1925 as_bad (_("Extended register `%%%s' available only in 64bit mode."),
1926 i
.op
[op
].regs
->reg_name
);
1931 /* If matched instruction specifies an explicit instruction mnemonic
1933 if (i
.tm
.opcode_modifier
& (Size16
| Size32
| Size64
))
1935 if (i
.tm
.opcode_modifier
& Size16
)
1936 i
.suffix
= WORD_MNEM_SUFFIX
;
1937 else if (i
.tm
.opcode_modifier
& Size64
)
1938 i
.suffix
= QWORD_MNEM_SUFFIX
;
1940 i
.suffix
= LONG_MNEM_SUFFIX
;
1942 else if (i
.reg_operands
)
1944 /* If there's no instruction mnemonic suffix we try to invent one
1945 based on register operands. */
1948 /* We take i.suffix from the last register operand specified,
1949 Destination register type is more significant than source
1952 for (op
= i
.operands
; --op
>= 0;)
1953 if ((i
.types
[op
] & Reg
)
1954 && !(i
.tm
.operand_types
[op
] & InOutPortReg
))
1956 i
.suffix
= ((i
.types
[op
] & Reg8
) ? BYTE_MNEM_SUFFIX
:
1957 (i
.types
[op
] & Reg16
) ? WORD_MNEM_SUFFIX
:
1958 (i
.types
[op
] & Reg64
) ? QWORD_MNEM_SUFFIX
:
1963 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
1966 for (op
= i
.operands
; --op
>= 0;)
1968 /* If this is an eight bit register, it's OK. If it's
1969 the 16 or 32 bit version of an eight bit register,
1970 we will just use the low portion, and that's OK too. */
1971 if (i
.types
[op
] & Reg8
)
1974 /* movzx and movsx should not generate this warning. */
1976 && (i
.tm
.base_opcode
== 0xfb7
1977 || i
.tm
.base_opcode
== 0xfb6
1978 || i
.tm
.base_opcode
== 0x63
1979 || i
.tm
.base_opcode
== 0xfbe
1980 || i
.tm
.base_opcode
== 0xfbf))
1983 if ((i
.types
[op
] & WordReg
) && i
.op
[op
].regs
->reg_num
< 4
1985 /* Check that the template allows eight bit regs
1986 This kills insns such as `orb $1,%edx', which
1987 maybe should be allowed. */
1988 && (i
.tm
.operand_types
[op
] & (Reg8
|InOutPortReg
))
1992 /* Prohibit these changes in the 64bit mode, since
1993 the lowering is more complicated. */
1994 if (flag_code
== CODE_64BIT
1995 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
1996 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
1997 i
.op
[op
].regs
->reg_name
,
1999 #if REGISTER_WARNINGS
2001 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
2002 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2003 (i
.op
[op
].regs
- (i
.types
[op
] & Reg16
? 8 : 16))->reg_name
,
2004 i
.op
[op
].regs
->reg_name
,
2009 /* Any other register is bad. */
2010 if (i
.types
[op
] & (Reg
| RegMMX
| RegXMM
2012 | Control
| Debug
| Test
2013 | FloatReg
| FloatAcc
))
2015 as_bad (_("`%%%s' not allowed with `%s%c'"),
2016 i
.op
[op
].regs
->reg_name
,
2023 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
2027 for (op
= i
.operands
; --op
>= 0;)
2028 /* Reject eight bit registers, except where the template
2029 requires them. (eg. movzb) */
2030 if ((i
.types
[op
] & Reg8
) != 0
2031 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2033 as_bad (_("`%%%s' not allowed with `%s%c'"),
2034 i
.op
[op
].regs
->reg_name
,
2039 /* Warn if the e prefix on a general reg is missing. */
2040 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2041 && (i
.types
[op
] & Reg16
) != 0
2042 && (i
.tm
.operand_types
[op
] & (Reg32
|Acc
)) != 0)
2044 /* Prohibit these changes in the 64bit mode, since
2045 the lowering is more complicated. */
2046 if (flag_code
== CODE_64BIT
)
2047 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2048 i
.op
[op
].regs
->reg_name
,
2050 #if REGISTER_WARNINGS
2052 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2053 (i
.op
[op
].regs
+ 8)->reg_name
,
2054 i
.op
[op
].regs
->reg_name
,
2058 /* Warn if the r prefix on a general reg is missing. */
2059 else if ((i
.types
[op
] & Reg64
) != 0
2060 && (i
.tm
.operand_types
[op
] & (Reg32
|Acc
)) != 0)
2062 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2063 i
.op
[op
].regs
->reg_name
,
2067 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
2071 for (op
= i
.operands
; --op
>= 0; )
2072 /* Reject eight bit registers, except where the template
2073 requires them. (eg. movzb) */
2074 if ((i
.types
[op
] & Reg8
) != 0
2075 && (i
.tm
.operand_types
[op
] & (Reg16
|Reg32
|Acc
)) != 0)
2077 as_bad (_("`%%%s' not allowed with `%s%c'"),
2078 i
.op
[op
].regs
->reg_name
,
2083 /* Warn if the e prefix on a general reg is missing. */
2084 else if (((i
.types
[op
] & Reg16
) != 0
2085 || (i
.types
[op
] & Reg32
) != 0)
2086 && (i
.tm
.operand_types
[op
] & (Reg32
|Acc
)) != 0)
2088 /* Prohibit these changes in the 64bit mode, since
2089 the lowering is more complicated. */
2090 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2091 i
.op
[op
].regs
->reg_name
,
2095 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
2098 for (op
= i
.operands
; --op
>= 0;)
2099 /* Reject eight bit registers, except where the template
2100 requires them. (eg. movzb) */
2101 if ((i
.types
[op
] & Reg8
) != 0
2102 && (i
.tm
.operand_types
[op
] & (Reg16
|Reg32
|Acc
)) != 0)
2104 as_bad (_("`%%%s' not allowed with `%s%c'"),
2105 i
.op
[op
].regs
->reg_name
,
2110 /* Warn if the e prefix on a general reg is present. */
2111 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2112 && (i
.types
[op
] & Reg32
) != 0
2113 && (i
.tm
.operand_types
[op
] & (Reg16
|Acc
)) != 0)
2115 /* Prohibit these changes in the 64bit mode, since
2116 the lowering is more complicated. */
2117 if (flag_code
== CODE_64BIT
)
2118 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2119 i
.op
[op
].regs
->reg_name
,
2122 #if REGISTER_WARNINGS
2123 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2124 (i
.op
[op
].regs
- 8)->reg_name
,
2125 i
.op
[op
].regs
->reg_name
,
2130 else if (intel_syntax
&& (i
.tm
.opcode_modifier
& IgnoreSize
))
2131 /* Do nothing if the instruction is going to ignore the prefix. */
2136 else if ((i
.tm
.opcode_modifier
& DefaultSize
) && !i
.suffix
)
2138 i
.suffix
= stackop_size
;
2140 /* Make still unresolved immediate matches conform to size of immediate
2141 given in i.suffix. Note: overlap2 cannot be an immediate! */
2142 if ((overlap0
& (Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
))
2143 && overlap0
!= Imm8
&& overlap0
!= Imm8S
2144 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2145 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2149 overlap0
&= (i
.suffix
== BYTE_MNEM_SUFFIX
? (Imm8
| Imm8S
) :
2150 (i
.suffix
== WORD_MNEM_SUFFIX
? Imm16
:
2151 (i
.suffix
== QWORD_MNEM_SUFFIX
? Imm64
| Imm32S
: Imm32
)));
2153 else if (overlap0
== (Imm16
| Imm32S
| Imm32
)
2154 || overlap0
== (Imm16
| Imm32
)
2155 || overlap0
== (Imm16
| Imm32S
))
2158 ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)) ? Imm16
: Imm32S
;
2160 if (overlap0
!= Imm8
&& overlap0
!= Imm8S
2161 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2162 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2164 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2168 if ((overlap1
& (Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
))
2169 && overlap1
!= Imm8
&& overlap1
!= Imm8S
2170 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2171 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2175 overlap1
&= (i
.suffix
== BYTE_MNEM_SUFFIX
? (Imm8
| Imm8S
) :
2176 (i
.suffix
== WORD_MNEM_SUFFIX
? Imm16
:
2177 (i
.suffix
== QWORD_MNEM_SUFFIX
? Imm64
| Imm32S
: Imm32
)));
2179 else if (overlap1
== (Imm16
| Imm32
| Imm32S
)
2180 || overlap1
== (Imm16
| Imm32
)
2181 || overlap1
== (Imm16
| Imm32S
))
2184 ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)) ? Imm16
: Imm32S
;
2186 if (overlap1
!= Imm8
&& overlap1
!= Imm8S
2187 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2188 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2190 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1
, i
.suffix
);
2194 assert ((overlap2
& Imm
) == 0);
2196 i
.types
[0] = overlap0
;
2197 if (overlap0
& ImplicitRegister
)
2199 if (overlap0
& Imm1
)
2200 i
.imm_operands
= 0; /* kludge for shift insns. */
2202 i
.types
[1] = overlap1
;
2203 if (overlap1
& ImplicitRegister
)
2206 i
.types
[2] = overlap2
;
2207 if (overlap2
& ImplicitRegister
)
2210 /* Finalize opcode. First, we change the opcode based on the operand
2211 size given by i.suffix: We need not change things for byte insns. */
2213 if (!i
.suffix
&& (i
.tm
.opcode_modifier
& W
))
2215 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2219 /* For movzx and movsx, need to check the register type. */
2221 && (i
.tm
.base_opcode
== 0xfb6 || i
.tm
.base_opcode
== 0xfbe))
2222 if (i
.suffix
&& i
.suffix
== BYTE_MNEM_SUFFIX
)
2224 unsigned int prefix
= DATA_PREFIX_OPCODE
;
2226 if ((i
.op
[1].regs
->reg_type
& Reg16
) != 0)
2227 if (!add_prefix (prefix
))
2231 if (i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
2233 /* It's not a byte, select word/dword operation. */
2234 if (i
.tm
.opcode_modifier
& W
)
2236 if (i
.tm
.opcode_modifier
& ShortForm
)
2237 i
.tm
.base_opcode
|= 8;
2239 i
.tm
.base_opcode
|= 1;
2241 /* Now select between word & dword operations via the operand
2242 size prefix, except for instructions that will ignore this
2244 if (i
.suffix
!= QWORD_MNEM_SUFFIX
2245 && (i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
2246 && !(i
.tm
.opcode_modifier
& IgnoreSize
))
2248 unsigned int prefix
= DATA_PREFIX_OPCODE
;
2249 if (i
.tm
.opcode_modifier
& JumpByte
) /* jcxz, loop */
2250 prefix
= ADDR_PREFIX_OPCODE
;
2252 if (! add_prefix (prefix
))
2256 /* Set mode64 for an operand. */
2257 if (i
.suffix
== QWORD_MNEM_SUFFIX
2258 && !(i
.tm
.opcode_modifier
& NoRex64
))
2261 if (flag_code
< CODE_64BIT
)
2263 as_bad (_("64bit operations available only in 64bit modes."));
2268 /* Size floating point instruction. */
2269 if (i
.suffix
== LONG_MNEM_SUFFIX
)
2271 if (i
.tm
.opcode_modifier
& FloatMF
)
2272 i
.tm
.base_opcode
^= 4;
2276 if (i
.tm
.opcode_modifier
& ImmExt
)
2278 /* These AMD 3DNow! and Intel Katmai New Instructions have an
2279 opcode suffix which is coded in the same place as an 8-bit
2280 immediate field would be. Here we fake an 8-bit immediate
2281 operand from the opcode suffix stored in tm.extension_opcode. */
2285 assert (i
.imm_operands
== 0 && i
.operands
<= 2 && 2 < MAX_OPERANDS
);
2287 exp
= &im_expressions
[i
.imm_operands
++];
2288 i
.op
[i
.operands
].imms
= exp
;
2289 i
.types
[i
.operands
++] = Imm8
;
2290 exp
->X_op
= O_constant
;
2291 exp
->X_add_number
= i
.tm
.extension_opcode
;
2292 i
.tm
.extension_opcode
= None
;
2295 /* For insns with operands there are more diddles to do to the opcode. */
2298 /* Default segment register this instruction will use
2299 for memory accesses. 0 means unknown.
2300 This is only for optimizing out unnecessary segment overrides. */
2301 const seg_entry
*default_seg
= 0;
2303 /* The imul $imm, %reg instruction is converted into
2304 imul $imm, %reg, %reg, and the clr %reg instruction
2305 is converted into xor %reg, %reg. */
2306 if (i
.tm
.opcode_modifier
& regKludge
)
2308 unsigned int first_reg_op
= (i
.types
[0] & Reg
) ? 0 : 1;
2309 /* Pretend we saw the extra register operand. */
2310 assert (i
.op
[first_reg_op
+ 1].regs
== 0);
2311 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
2312 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
2316 if (i
.tm
.opcode_modifier
& ShortForm
)
2318 /* The register or float register operand is in operand 0 or 1. */
2319 unsigned int op
= (i
.types
[0] & (Reg
| FloatReg
)) ? 0 : 1;
2320 /* Register goes in low 3 bits of opcode. */
2321 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
2322 if (i
.op
[op
].regs
->reg_flags
& RegRex
)
2324 if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
2326 /* Warn about some common errors, but press on regardless.
2327 The first case can be generated by gcc (<= 2.8.1). */
2328 if (i
.operands
== 2)
2330 /* Reversed arguments on faddp, fsubp, etc. */
2331 as_warn (_("translating to `%s %%%s,%%%s'"), i
.tm
.name
,
2332 i
.op
[1].regs
->reg_name
,
2333 i
.op
[0].regs
->reg_name
);
2337 /* Extraneous `l' suffix on fp insn. */
2338 as_warn (_("translating to `%s %%%s'"), i
.tm
.name
,
2339 i
.op
[0].regs
->reg_name
);
2343 else if (i
.tm
.opcode_modifier
& Modrm
)
2345 /* The opcode is completed (modulo i.tm.extension_opcode which
2346 must be put into the modrm byte).
2347 Now, we make the modrm & index base bytes based on all the
2348 info we've collected. */
2350 /* i.reg_operands MUST be the number of real register operands;
2351 implicit registers do not count. */
2352 if (i
.reg_operands
== 2)
2354 unsigned int source
, dest
;
2355 source
= ((i
.types
[0]
2356 & (Reg
| RegMMX
| RegXMM
2358 | Control
| Debug
| Test
))
2363 /* One of the register operands will be encoded in the
2364 i.tm.reg field, the other in the combined i.tm.mode
2365 and i.tm.regmem fields. If no form of this
2366 instruction supports a memory destination operand,
2367 then we assume the source operand may sometimes be
2368 a memory operand and so we need to store the
2369 destination in the i.rm.reg field. */
2370 if ((i
.tm
.operand_types
[dest
] & AnyMem
) == 0)
2372 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
2373 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
2374 if (i
.op
[dest
].regs
->reg_flags
& RegRex
)
2376 if (i
.op
[source
].regs
->reg_flags
& RegRex
)
2381 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
2382 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
2383 if (i
.op
[dest
].regs
->reg_flags
& RegRex
)
2385 if (i
.op
[source
].regs
->reg_flags
& RegRex
)
2390 { /* If it's not 2 reg operands... */
2393 unsigned int fake_zero_displacement
= 0;
2394 unsigned int op
= ((i
.types
[0] & AnyMem
)
2396 : (i
.types
[1] & AnyMem
) ? 1 : 2);
2403 if (! i
.disp_operands
)
2404 fake_zero_displacement
= 1;
2407 /* Operand is just <disp> */
2408 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
2410 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
2411 i
.types
[op
] &= ~Disp
;
2412 i
.types
[op
] |= Disp16
;
2414 else if (flag_code
!= CODE_64BIT
)
2416 i
.rm
.regmem
= NO_BASE_REGISTER
;
2417 i
.types
[op
] &= ~Disp
;
2418 i
.types
[op
] |= Disp32
;
2422 /* 64bit mode overwrites the 32bit
2423 absolute addressing by RIP relative
2424 addressing and absolute addressing
2425 is encoded by one of the redundant
2428 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2429 i
.sib
.base
= NO_BASE_REGISTER
;
2430 i
.sib
.index
= NO_INDEX_REGISTER
;
2431 i
.types
[op
] &= ~Disp
;
2432 i
.types
[op
] |= Disp32S
;
2435 else /* ! i.base_reg && i.index_reg */
2437 i
.sib
.index
= i
.index_reg
->reg_num
;
2438 i
.sib
.base
= NO_BASE_REGISTER
;
2439 i
.sib
.scale
= i
.log2_scale_factor
;
2440 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2441 i
.types
[op
] &= ~Disp
;
2442 if (flag_code
!= CODE_64BIT
)
2443 i
.types
[op
] |= Disp32
; /* Must be 32 bit */
2445 i
.types
[op
] |= Disp32S
;
2446 if (i
.index_reg
->reg_flags
& RegRex
)
2450 /* RIP addressing for 64bit mode. */
2451 else if (i
.base_reg
->reg_type
== BaseIndex
)
2453 i
.rm
.regmem
= NO_BASE_REGISTER
;
2454 i
.types
[op
] &= ~Disp
;
2455 i
.types
[op
] |= Disp32S
;
2456 i
.flags
[op
] = Operand_PCrel
;
2458 else if (i
.base_reg
->reg_type
& Reg16
)
2460 switch (i
.base_reg
->reg_num
)
2465 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
2466 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
2473 if ((i
.types
[op
] & Disp
) == 0)
2475 /* fake (%bp) into 0(%bp) */
2476 i
.types
[op
] |= Disp8
;
2477 fake_zero_displacement
= 1;
2480 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
2481 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
2483 default: /* (%si) -> 4 or (%di) -> 5 */
2484 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
2486 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2488 else /* i.base_reg and 32/64 bit mode */
2490 if (flag_code
== CODE_64BIT
2491 && (i
.types
[op
] & Disp
))
2493 if (i
.types
[op
] & Disp8
)
2494 i
.types
[op
] = Disp8
| Disp32S
;
2496 i
.types
[op
] = Disp32S
;
2498 i
.rm
.regmem
= i
.base_reg
->reg_num
;
2499 if (i
.base_reg
->reg_flags
& RegRex
)
2501 i
.sib
.base
= i
.base_reg
->reg_num
;
2502 /* x86-64 ignores REX prefix bit here to avoid
2503 decoder complications. */
2504 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
2507 if (i
.disp_operands
== 0)
2509 fake_zero_displacement
= 1;
2510 i
.types
[op
] |= Disp8
;
2513 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
2517 i
.sib
.scale
= i
.log2_scale_factor
;
2520 /* <disp>(%esp) becomes two byte modrm
2521 with no index register. We've already
2522 stored the code for esp in i.rm.regmem
2523 ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. Any
2524 base register besides %esp will not use
2525 the extra modrm byte. */
2526 i
.sib
.index
= NO_INDEX_REGISTER
;
2527 #if ! SCALE1_WHEN_NO_INDEX
2528 /* Another case where we force the second
2530 if (i
.log2_scale_factor
)
2531 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2536 i
.sib
.index
= i
.index_reg
->reg_num
;
2537 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2538 if (i
.index_reg
->reg_flags
& RegRex
)
2541 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2544 if (fake_zero_displacement
)
2546 /* Fakes a zero displacement assuming that i.types[op]
2547 holds the correct displacement size. */
2550 assert (i
.op
[op
].disps
== 0);
2551 exp
= &disp_expressions
[i
.disp_operands
++];
2552 i
.op
[op
].disps
= exp
;
2553 exp
->X_op
= O_constant
;
2554 exp
->X_add_number
= 0;
2555 exp
->X_add_symbol
= (symbolS
*) 0;
2556 exp
->X_op_symbol
= (symbolS
*) 0;
2560 /* Fill in i.rm.reg or i.rm.regmem field with register
2561 operand (if any) based on i.tm.extension_opcode.
2562 Again, we must be careful to make sure that
2563 segment/control/debug/test/MMX registers are coded
2564 into the i.rm.reg field. */
2569 & (Reg
| RegMMX
| RegXMM
2571 | Control
| Debug
| Test
))
2574 & (Reg
| RegMMX
| RegXMM
2576 | Control
| Debug
| Test
))
2579 /* If there is an extension opcode to put here, the
2580 register number must be put into the regmem field. */
2581 if (i
.tm
.extension_opcode
!= None
)
2583 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
2584 if (i
.op
[op
].regs
->reg_flags
& RegRex
)
2589 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
2590 if (i
.op
[op
].regs
->reg_flags
& RegRex
)
2594 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2
2595 we must set it to 3 to indicate this is a register
2596 operand in the regmem field. */
2597 if (!i
.mem_operands
)
2601 /* Fill in i.rm.reg field with extension opcode (if any). */
2602 if (i
.tm
.extension_opcode
!= None
)
2603 i
.rm
.reg
= i
.tm
.extension_opcode
;
2606 else if (i
.tm
.opcode_modifier
& (Seg2ShortForm
| Seg3ShortForm
))
2608 if (i
.tm
.base_opcode
== POP_SEG_SHORT
2609 && i
.op
[0].regs
->reg_num
== 1)
2611 as_bad (_("you can't `pop %%cs'"));
2614 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
2615 if (i
.op
[0].regs
->reg_flags
& RegRex
)
2618 else if ((i
.tm
.base_opcode
& ~(D
|W
)) == MOV_AX_DISP32
)
2622 else if ((i
.tm
.opcode_modifier
& IsString
) != 0)
2624 /* For the string instructions that allow a segment override
2625 on one of their operands, the default segment is ds. */
2629 /* If a segment was explicitly specified,
2630 and the specified segment is not the default,
2631 use an opcode prefix to select it.
2632 If we never figured out what the default segment is,
2633 then default_seg will be zero at this point,
2634 and the specified segment prefix will always be used. */
2635 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
2637 if (! add_prefix (i
.seg
[0]->seg_prefix
))
2641 else if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
2643 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2644 as_warn (_("translating to `%sp'"), i
.tm
.name
);
2648 /* Handle conversion of 'int $3' --> special int3 insn. */
2649 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
2651 i
.tm
.base_opcode
= INT3_OPCODE
;
2655 if ((i
.tm
.opcode_modifier
& (Jump
| JumpByte
| JumpDword
))
2656 && i
.op
[0].disps
->X_op
== O_constant
)
2658 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2659 the absolute address given by the constant. Since ix86 jumps and
2660 calls are pc relative, we need to generate a reloc. */
2661 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
2662 i
.op
[0].disps
->X_op
= O_symbol
;
2665 if (i
.tm
.opcode_modifier
& Rex64
)
2668 /* For 8bit registers we would need an empty rex prefix.
2669 Also in the case instruction is already having prefix,
2670 we need to convert old registers to new ones. */
2672 if (((i
.types
[0] & Reg8
) && (i
.op
[0].regs
->reg_flags
& RegRex64
))
2673 || ((i
.types
[1] & Reg8
) && (i
.op
[1].regs
->reg_flags
& RegRex64
))
2674 || ((i
.rex
.mode64
|| i
.rex
.extX
|| i
.rex
.extY
|| i
.rex
.extZ
|| i
.rex
.empty
)
2675 && ((i
.types
[0] & Reg8
) || (i
.types
[1] & Reg8
))))
2679 for (x
= 0; x
< 2; x
++)
2681 /* Look for 8bit operand that does use old registers. */
2682 if (i
.types
[x
] & Reg8
2683 && !(i
.op
[x
].regs
->reg_flags
& RegRex64
))
2685 /* In case it is "hi" register, give up. */
2686 if (i
.op
[x
].regs
->reg_num
> 3)
2687 as_bad (_("Can't encode registers '%%%s' in the instruction requiring REX prefix.\n"),
2688 i
.op
[x
].regs
->reg_name
);
2690 /* Otherwise it is equivalent to the extended register.
2691 Since the encoding don't change this is merely cosmetical
2692 cleanup for debug output. */
2694 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
2699 if (i
.rex
.mode64
|| i
.rex
.extX
|| i
.rex
.extY
|| i
.rex
.extZ
|| i
.rex
.empty
)
2701 | (i
.rex
.mode64
? 8 : 0)
2702 | (i
.rex
.extX
? 4 : 0)
2703 | (i
.rex
.extY
? 2 : 0)
2704 | (i
.rex
.extZ
? 1 : 0));
2706 /* We are ready to output the insn. */
2711 if (i
.tm
.opcode_modifier
& Jump
)
2717 if (flag_code
== CODE_16BIT
)
2721 if (i
.prefix
[DATA_PREFIX
])
2727 if (i
.prefix
[REX_PREFIX
])
2733 if (i
.prefixes
!= 0 && !intel_syntax
)
2734 as_warn (_("skipping prefixes on this instruction"));
2736 /* It's always a symbol; End frag & setup for relax.
2737 Make sure there is enough room in this frag for the largest
2738 instruction we may generate in md_convert_frag. This is 2
2739 bytes for the opcode and room for the prefix and largest
2741 frag_grow (prefix
+ 2 + 4);
2742 insn_size
+= prefix
+ 1;
2743 /* Prefix and 1 opcode byte go in fr_fix. */
2744 p
= frag_more (prefix
+ 1);
2745 if (i
.prefix
[DATA_PREFIX
])
2746 *p
++ = DATA_PREFIX_OPCODE
;
2747 if (i
.prefix
[REX_PREFIX
])
2748 *p
++ = i
.prefix
[REX_PREFIX
];
2749 *p
= i
.tm
.base_opcode
;
2750 /* 1 possible extra opcode + displacement go in var part.
2751 Pass reloc in fr_var. */
2752 frag_var (rs_machine_dependent
,
2755 ((unsigned char) *p
== JUMP_PC_RELATIVE
2756 ? ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
) | code16
2757 : ((cpu_arch_flags
& Cpu386
) != 0
2758 ? ENCODE_RELAX_STATE (COND_JUMP
, SMALL
) | code16
2759 : ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
) | code16
)),
2760 i
.op
[0].disps
->X_add_symbol
,
2761 i
.op
[0].disps
->X_add_number
,
2764 else if (i
.tm
.opcode_modifier
& (JumpByte
| JumpDword
))
2768 if (i
.tm
.opcode_modifier
& JumpByte
)
2770 /* This is a loop or jecxz type instruction. */
2772 if (i
.prefix
[ADDR_PREFIX
])
2775 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
2784 if (flag_code
== CODE_16BIT
)
2787 if (i
.prefix
[DATA_PREFIX
])
2790 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
2800 if (i
.prefix
[REX_PREFIX
])
2802 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
2807 if (i
.prefixes
!= 0 && !intel_syntax
)
2808 as_warn (_("skipping prefixes on this instruction"));
2810 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
2812 insn_size
+= 1 + size
;
2813 p
= frag_more (1 + size
);
2817 /* Opcode can be at most two bytes. */
2818 insn_size
+= 2 + size
;
2819 p
= frag_more (2 + size
);
2820 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
2822 *p
++ = i
.tm
.base_opcode
& 0xff;
2824 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2825 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
2827 else if (i
.tm
.opcode_modifier
& JumpInterSegment
)
2834 if (flag_code
== CODE_16BIT
)
2838 if (i
.prefix
[DATA_PREFIX
])
2844 if (i
.prefix
[REX_PREFIX
])
2854 if (i
.prefixes
!= 0 && !intel_syntax
)
2855 as_warn (_("skipping prefixes on this instruction"));
2857 /* 1 opcode; 2 segment; offset */
2858 insn_size
+= prefix
+ 1 + 2 + size
;
2859 p
= frag_more (prefix
+ 1 + 2 + size
);
2861 if (i
.prefix
[DATA_PREFIX
])
2862 *p
++ = DATA_PREFIX_OPCODE
;
2864 if (i
.prefix
[REX_PREFIX
])
2865 *p
++ = i
.prefix
[REX_PREFIX
];
2867 *p
++ = i
.tm
.base_opcode
;
2868 if (i
.op
[1].imms
->X_op
== O_constant
)
2870 offsetT n
= i
.op
[1].imms
->X_add_number
;
2873 && !fits_in_unsigned_word (n
)
2874 && !fits_in_signed_word (n
))
2876 as_bad (_("16-bit jump out of range"));
2879 md_number_to_chars (p
, n
, size
);
2882 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2883 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
2884 if (i
.op
[0].imms
->X_op
!= O_constant
)
2885 as_bad (_("can't handle non absolute segment in `%s'"),
2887 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
2891 /* Output normal instructions here. */
2894 /* All opcodes on i386 have eighter 1 or 2 bytes. We may use third
2895 byte for the SSE instructions to specify prefix they require. */
2896 if (i
.tm
.base_opcode
& 0xff0000)
2897 add_prefix ((i
.tm
.base_opcode
>> 16) & 0xff);
2899 /* The prefix bytes. */
2901 q
< i
.prefix
+ sizeof (i
.prefix
) / sizeof (i
.prefix
[0]);
2908 md_number_to_chars (p
, (valueT
) *q
, 1);
2912 /* Now the opcode; be careful about word order here! */
2913 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
2916 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
2922 /* Put out high byte first: can't use md_number_to_chars! */
2923 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
2924 *p
= i
.tm
.base_opcode
& 0xff;
2927 /* Now the modrm byte and sib byte (if present). */
2928 if (i
.tm
.opcode_modifier
& Modrm
)
2932 md_number_to_chars (p
,
2933 (valueT
) (i
.rm
.regmem
<< 0
2937 /* If i.rm.regmem == ESP (4)
2938 && i.rm.mode != (Register mode)
2940 ==> need second modrm byte. */
2941 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
2943 && !(i
.base_reg
&& (i
.base_reg
->reg_type
& Reg16
) != 0))
2947 md_number_to_chars (p
,
2948 (valueT
) (i
.sib
.base
<< 0
2950 | i
.sib
.scale
<< 6),
2955 if (i
.disp_operands
)
2957 register unsigned int n
;
2959 for (n
= 0; n
< i
.operands
; n
++)
2961 if (i
.types
[n
] & Disp
)
2963 if (i
.op
[n
].disps
->X_op
== O_constant
)
2969 if (i
.types
[n
] & (Disp8
| Disp16
| Disp64
))
2972 if (i
.types
[n
] & Disp8
)
2974 if (i
.types
[n
] & Disp64
)
2977 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
2980 p
= frag_more (size
);
2981 md_number_to_chars (p
, val
, size
);
2987 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
2989 /* The PC relative address is computed relative
2990 to the instruction boundary, so in case immediate
2991 fields follows, we need to adjust the value. */
2992 if (pcrel
&& i
.imm_operands
)
2995 register unsigned int n1
;
2997 for (n1
= 0; n1
< i
.operands
; n1
++)
2998 if (i
.types
[n1
] & Imm
)
3000 if (i
.types
[n1
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3003 if (i
.types
[n1
] & (Imm8
| Imm8S
))
3005 if (i
.types
[n1
] & Imm64
)
3010 /* We should find the immediate. */
3011 if (n1
== i
.operands
)
3013 i
.op
[n
].disps
->X_add_number
-= imm_size
;
3016 if (i
.types
[n
] & Disp32S
)
3019 if (i
.types
[n
] & (Disp16
| Disp64
))
3022 if (i
.types
[n
] & Disp64
)
3027 p
= frag_more (size
);
3028 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3029 i
.op
[n
].disps
, pcrel
,
3030 reloc (size
, pcrel
, sign
, i
.reloc
[n
]));
3036 /* Output immediate. */
3039 register unsigned int n
;
3041 for (n
= 0; n
< i
.operands
; n
++)
3043 if (i
.types
[n
] & Imm
)
3045 if (i
.op
[n
].imms
->X_op
== O_constant
)
3051 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3054 if (i
.types
[n
] & (Imm8
| Imm8S
))
3056 else if (i
.types
[n
] & Imm64
)
3059 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
3062 p
= frag_more (size
);
3063 md_number_to_chars (p
, val
, size
);
3067 /* Not absolute_section.
3068 Need a 32-bit fixup (don't support 8bit
3069 non-absolute imms). Try to support other
3071 #ifdef BFD_ASSEMBLER
3072 enum bfd_reloc_code_real reloc_type
;
3079 if ((i
.types
[n
] & (Imm32S
))
3080 && i
.suffix
== QWORD_MNEM_SUFFIX
)
3082 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3085 if (i
.types
[n
] & (Imm8
| Imm8S
))
3087 if (i
.types
[n
] & Imm64
)
3092 p
= frag_more (size
);
3093 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
3094 #ifdef BFD_ASSEMBLER
3095 if (reloc_type
== BFD_RELOC_32
3097 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
3098 && (i
.op
[n
].imms
->X_op
== O_symbol
3099 || (i
.op
[n
].imms
->X_op
== O_add
3100 && ((symbol_get_value_expression
3101 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
3104 /* We don't support dynamic linking on x86-64 yet. */
3105 if (flag_code
== CODE_64BIT
)
3107 reloc_type
= BFD_RELOC_386_GOTPC
;
3108 i
.op
[n
].imms
->X_add_number
+= 3;
3111 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3112 i
.op
[n
].imms
, 0, reloc_type
);
3119 dwarf2_emit_insn (insn_size
);
3126 #endif /* DEBUG386 */
3130 static int i386_immediate
PARAMS ((char *));
3133 i386_immediate (imm_start
)
3136 char *save_input_line_pointer
;
3140 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
3142 as_bad (_("only 1 or 2 immediate operands are allowed"));
3146 exp
= &im_expressions
[i
.imm_operands
++];
3147 i
.op
[this_operand
].imms
= exp
;
3149 if (is_space_char (*imm_start
))
3152 save_input_line_pointer
= input_line_pointer
;
3153 input_line_pointer
= imm_start
;
3157 /* We can have operands of the form
3158 <symbol>@GOTOFF+<nnn>
3159 Take the easy way out here and copy everything
3160 into a temporary buffer... */
3163 cp
= strchr (input_line_pointer
, '@');
3170 /* GOT relocations are not supported in 16 bit mode. */
3171 if (flag_code
== CODE_16BIT
)
3172 as_bad (_("GOT relocations not supported in 16 bit mode"));
3174 if (GOT_symbol
== NULL
)
3175 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
3177 if (strncmp (cp
+ 1, "PLT", 3) == 0)
3179 if (flag_code
== CODE_64BIT
)
3180 i
.reloc
[this_operand
] = BFD_RELOC_X86_64_PLT32
;
3182 i
.reloc
[this_operand
] = BFD_RELOC_386_PLT32
;
3185 else if (strncmp (cp
+ 1, "GOTOFF", 6) == 0)
3187 if (flag_code
== CODE_64BIT
)
3188 as_bad ("GOTOFF relocations are unsupported in 64bit mode.");
3189 i
.reloc
[this_operand
] = BFD_RELOC_386_GOTOFF
;
3192 else if (strncmp (cp
+ 1, "GOTPCREL", 8) == 0)
3194 if (flag_code
== CODE_64BIT
)
3195 i
.reloc
[this_operand
] = BFD_RELOC_X86_64_GOTPCREL
;
3197 as_bad ("GOTPCREL relocations are supported only in 64bit mode.");
3200 else if (strncmp (cp
+ 1, "GOT", 3) == 0)
3202 if (flag_code
== CODE_64BIT
)
3203 i
.reloc
[this_operand
] = BFD_RELOC_X86_64_GOT32
;
3205 i
.reloc
[this_operand
] = BFD_RELOC_386_GOT32
;
3209 as_bad (_("bad reloc specifier in expression"));
3211 /* Replace the relocation token with ' ', so that errors like
3212 foo@GOTOFF1 will be detected. */
3213 first
= cp
- input_line_pointer
;
3214 tmpbuf
= (char *) alloca (strlen (input_line_pointer
));
3215 memcpy (tmpbuf
, input_line_pointer
, first
);
3216 tmpbuf
[first
] = ' ';
3217 strcpy (tmpbuf
+ first
+ 1, cp
+ 1 + len
);
3218 input_line_pointer
= tmpbuf
;
3223 exp_seg
= expression (exp
);
3226 if (*input_line_pointer
)
3227 as_bad (_("ignoring junk `%s' after expression"), input_line_pointer
);
3229 input_line_pointer
= save_input_line_pointer
;
3231 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
3233 /* Missing or bad expr becomes absolute 0. */
3234 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
3236 exp
->X_op
= O_constant
;
3237 exp
->X_add_number
= 0;
3238 exp
->X_add_symbol
= (symbolS
*) 0;
3239 exp
->X_op_symbol
= (symbolS
*) 0;
3241 else if (exp
->X_op
== O_constant
)
3243 /* Size it properly later. */
3244 i
.types
[this_operand
] |= Imm64
;
3245 /* If BFD64, sign extend val. */
3246 if (!use_rela_relocations
)
3247 if ((exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
3248 exp
->X_add_number
= (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
3250 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3252 #ifdef BFD_ASSEMBLER
3253 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
3255 && exp_seg
!= text_section
3256 && exp_seg
!= data_section
3257 && exp_seg
!= bss_section
3258 && exp_seg
!= undefined_section
3259 #ifdef BFD_ASSEMBLER
3260 && !bfd_is_com_section (exp_seg
)
3264 #ifdef BFD_ASSEMBLER
3265 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
3267 as_bad (_("unimplemented segment type %d in operand"), exp_seg
);
3274 /* This is an address. The size of the address will be
3275 determined later, depending on destination register,
3276 suffix, or the default for the section. */
3277 i
.types
[this_operand
] |= Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
;
3283 static int i386_scale
PARAMS ((char *));
3289 if (!isdigit (*scale
))
3296 i
.log2_scale_factor
= 0;
3299 i
.log2_scale_factor
= 1;
3302 i
.log2_scale_factor
= 2;
3305 i
.log2_scale_factor
= 3;
3309 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
3313 if (i
.log2_scale_factor
!= 0 && ! i
.index_reg
)
3315 as_warn (_("scale factor of %d without an index register"),
3316 1 << i
.log2_scale_factor
);
3317 #if SCALE1_WHEN_NO_INDEX
3318 i
.log2_scale_factor
= 0;
3324 static int i386_displacement
PARAMS ((char *, char *));
3327 i386_displacement (disp_start
, disp_end
)
3331 register expressionS
*exp
;
3333 char *save_input_line_pointer
;
3334 int bigdisp
= Disp32
;
3336 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3338 if (flag_code
== CODE_64BIT
)
3340 i
.types
[this_operand
] |= bigdisp
;
3342 exp
= &disp_expressions
[i
.disp_operands
];
3343 i
.op
[this_operand
].disps
= exp
;
3345 save_input_line_pointer
= input_line_pointer
;
3346 input_line_pointer
= disp_start
;
3347 END_STRING_AND_SAVE (disp_end
);
3349 #ifndef GCC_ASM_O_HACK
3350 #define GCC_ASM_O_HACK 0
3353 END_STRING_AND_SAVE (disp_end
+ 1);
3354 if ((i
.types
[this_operand
] & BaseIndex
) != 0
3355 && displacement_string_end
[-1] == '+')
3357 /* This hack is to avoid a warning when using the "o"
3358 constraint within gcc asm statements.
3361 #define _set_tssldt_desc(n,addr,limit,type) \
3362 __asm__ __volatile__ ( \
3364 "movw %w1,2+%0\n\t" \
3366 "movb %b1,4+%0\n\t" \
3367 "movb %4,5+%0\n\t" \
3368 "movb $0,6+%0\n\t" \
3369 "movb %h1,7+%0\n\t" \
3371 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
3373 This works great except that the output assembler ends
3374 up looking a bit weird if it turns out that there is
3375 no offset. You end up producing code that looks like:
3388 So here we provide the missing zero. */
3390 *displacement_string_end
= '0';
3395 /* We can have operands of the form
3396 <symbol>@GOTOFF+<nnn>
3397 Take the easy way out here and copy everything
3398 into a temporary buffer... */
3401 cp
= strchr (input_line_pointer
, '@');
3408 /* GOT relocations are not supported in 16 bit mode. */
3409 if (flag_code
== CODE_16BIT
)
3410 as_bad (_("GOT relocations not supported in 16 bit mode"));
3412 if (GOT_symbol
== NULL
)
3413 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
3415 if (strncmp (cp
+ 1, "PLT", 3) == 0)
3417 if (flag_code
== CODE_64BIT
)
3418 i
.reloc
[this_operand
] = BFD_RELOC_X86_64_PLT32
;
3420 i
.reloc
[this_operand
] = BFD_RELOC_386_PLT32
;
3423 else if (strncmp (cp
+ 1, "GOTOFF", 6) == 0)
3425 if (flag_code
== CODE_64BIT
)
3426 as_bad ("GOTOFF relocation is not supported in 64bit mode.");
3427 i
.reloc
[this_operand
] = BFD_RELOC_386_GOTOFF
;
3430 else if (strncmp (cp
+ 1, "GOTPCREL", 8) == 0)
3432 if (flag_code
!= CODE_64BIT
)
3433 as_bad ("GOTPCREL relocation is supported only in 64bit mode.");
3434 i
.reloc
[this_operand
] = BFD_RELOC_X86_64_GOTPCREL
;
3437 else if (strncmp (cp
+ 1, "GOT", 3) == 0)
3439 if (flag_code
== CODE_64BIT
)
3440 i
.reloc
[this_operand
] = BFD_RELOC_X86_64_GOT32
;
3442 i
.reloc
[this_operand
] = BFD_RELOC_386_GOT32
;
3446 as_bad (_("bad reloc specifier in expression"));
3448 /* Replace the relocation token with ' ', so that errors like
3449 foo@GOTOFF1 will be detected. */
3450 first
= cp
- input_line_pointer
;
3451 tmpbuf
= (char *) alloca (strlen (input_line_pointer
));
3452 memcpy (tmpbuf
, input_line_pointer
, first
);
3453 tmpbuf
[first
] = ' ';
3454 strcpy (tmpbuf
+ first
+ 1, cp
+ 1 + len
);
3455 input_line_pointer
= tmpbuf
;
3460 exp_seg
= expression (exp
);
3462 #ifdef BFD_ASSEMBLER
3463 /* We do this to make sure that the section symbol is in
3464 the symbol table. We will ultimately change the relocation
3465 to be relative to the beginning of the section. */
3466 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
3467 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
3469 if (S_IS_LOCAL (exp
->X_add_symbol
)
3470 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
3471 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
3472 assert (exp
->X_op
== O_symbol
);
3473 exp
->X_op
= O_subtract
;
3474 exp
->X_op_symbol
= GOT_symbol
;
3475 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
3476 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
3478 i
.reloc
[this_operand
] = BFD_RELOC_32
;
3483 if (*input_line_pointer
)
3484 as_bad (_("ignoring junk `%s' after expression"),
3485 input_line_pointer
);
3487 RESTORE_END_STRING (disp_end
+ 1);
3489 RESTORE_END_STRING (disp_end
);
3490 input_line_pointer
= save_input_line_pointer
;
3492 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
3494 /* Missing or bad expr becomes absolute 0. */
3495 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
3497 exp
->X_op
= O_constant
;
3498 exp
->X_add_number
= 0;
3499 exp
->X_add_symbol
= (symbolS
*) 0;
3500 exp
->X_op_symbol
= (symbolS
*) 0;
3503 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3504 if (exp
->X_op
!= O_constant
3505 #ifdef BFD_ASSEMBLER
3506 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
3508 && exp_seg
!= text_section
3509 && exp_seg
!= data_section
3510 && exp_seg
!= bss_section
3511 && exp_seg
!= undefined_section
)
3513 #ifdef BFD_ASSEMBLER
3514 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
3516 as_bad (_("unimplemented segment type %d in operand"), exp_seg
);
3521 else if (flag_code
== CODE_64BIT
)
3522 i
.types
[this_operand
] |= Disp32S
| Disp32
;
3526 static int i386_index_check
PARAMS ((const char *));
3528 /* Make sure the memory operand we've been dealt is valid.
3529 Return 1 on success, 0 on a failure. */
3532 i386_index_check (operand_string
)
3533 const char *operand_string
;
3536 #if INFER_ADDR_PREFIX
3542 if (flag_code
== CODE_64BIT
)
3546 && ((i
.base_reg
->reg_type
& Reg64
) == 0)
3547 && (i
.base_reg
->reg_type
!= BaseIndex
3550 && ((i
.index_reg
->reg_type
& (Reg64
|BaseIndex
))
3551 != (Reg64
|BaseIndex
))))
3556 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3560 && ((i
.base_reg
->reg_type
& (Reg16
|BaseIndex
|RegRex
))
3561 != (Reg16
|BaseIndex
)))
3563 && (((i
.index_reg
->reg_type
& (Reg16
|BaseIndex
))
3564 != (Reg16
|BaseIndex
))
3566 && i
.base_reg
->reg_num
< 6
3567 && i
.index_reg
->reg_num
>= 6
3568 && i
.log2_scale_factor
== 0))))
3575 && (i
.base_reg
->reg_type
& (Reg32
| RegRex
)) != Reg32
)
3577 && ((i
.index_reg
->reg_type
& (Reg32
|BaseIndex
|RegRex
))
3578 != (Reg32
|BaseIndex
))))
3584 #if INFER_ADDR_PREFIX
3585 if (flag_code
!= CODE_64BIT
3586 && i
.prefix
[ADDR_PREFIX
] == 0 && stackop_size
!= '\0')
3588 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
3590 /* Change the size of any displacement too. At most one of
3591 Disp16 or Disp32 is set.
3592 FIXME. There doesn't seem to be any real need for separate
3593 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
3594 Removing them would probably clean up the code quite a lot. */
3595 if (i
.types
[this_operand
] & (Disp16
|Disp32
))
3596 i
.types
[this_operand
] ^= (Disp16
|Disp32
);
3601 as_bad (_("`%s' is not a valid base/index expression"),
3605 as_bad (_("`%s' is not a valid %s bit base/index expression"),
3607 flag_code_names
[flag_code
]);
3613 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
3617 i386_operand (operand_string
)
3618 char *operand_string
;
3622 char *op_string
= operand_string
;
3624 if (is_space_char (*op_string
))
3627 /* We check for an absolute prefix (differentiating,
3628 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
3629 if (*op_string
== ABSOLUTE_PREFIX
)
3632 if (is_space_char (*op_string
))
3634 i
.types
[this_operand
] |= JumpAbsolute
;
3637 /* Check if operand is a register. */
3638 if ((*op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3639 && (r
= parse_register (op_string
, &end_op
)) != NULL
)
3641 /* Check for a segment override by searching for ':' after a
3642 segment register. */
3644 if (is_space_char (*op_string
))
3646 if (*op_string
== ':' && (r
->reg_type
& (SReg2
| SReg3
)))
3651 i
.seg
[i
.mem_operands
] = &es
;
3654 i
.seg
[i
.mem_operands
] = &cs
;
3657 i
.seg
[i
.mem_operands
] = &ss
;
3660 i
.seg
[i
.mem_operands
] = &ds
;
3663 i
.seg
[i
.mem_operands
] = &fs
;
3666 i
.seg
[i
.mem_operands
] = &gs
;
3670 /* Skip the ':' and whitespace. */
3672 if (is_space_char (*op_string
))
3675 if (!is_digit_char (*op_string
)
3676 && !is_identifier_char (*op_string
)
3677 && *op_string
!= '('
3678 && *op_string
!= ABSOLUTE_PREFIX
)
3680 as_bad (_("bad memory operand `%s'"), op_string
);
3683 /* Handle case of %es:*foo. */
3684 if (*op_string
== ABSOLUTE_PREFIX
)
3687 if (is_space_char (*op_string
))
3689 i
.types
[this_operand
] |= JumpAbsolute
;
3691 goto do_memory_reference
;
3695 as_bad (_("junk `%s' after register"), op_string
);
3698 i
.types
[this_operand
] |= r
->reg_type
& ~BaseIndex
;
3699 i
.op
[this_operand
].regs
= r
;
3702 else if (*op_string
== REGISTER_PREFIX
)
3704 as_bad (_("bad register name `%s'"), op_string
);
3707 else if (*op_string
== IMMEDIATE_PREFIX
)
3710 if (i
.types
[this_operand
] & JumpAbsolute
)
3712 as_bad (_("immediate operand illegal with absolute jump"));
3715 if (!i386_immediate (op_string
))
3718 else if (is_digit_char (*op_string
)
3719 || is_identifier_char (*op_string
)
3720 || *op_string
== '(')
3722 /* This is a memory reference of some sort. */
3725 /* Start and end of displacement string expression (if found). */
3726 char *displacement_string_start
;
3727 char *displacement_string_end
;
3729 do_memory_reference
:
3730 if ((i
.mem_operands
== 1
3731 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
3732 || i
.mem_operands
== 2)
3734 as_bad (_("too many memory references for `%s'"),
3735 current_templates
->start
->name
);
3739 /* Check for base index form. We detect the base index form by
3740 looking for an ')' at the end of the operand, searching
3741 for the '(' matching it, and finding a REGISTER_PREFIX or ','
3743 base_string
= op_string
+ strlen (op_string
);
3746 if (is_space_char (*base_string
))
3749 /* If we only have a displacement, set-up for it to be parsed later. */
3750 displacement_string_start
= op_string
;
3751 displacement_string_end
= base_string
+ 1;
3753 if (*base_string
== ')')
3756 unsigned int parens_balanced
= 1;
3757 /* We've already checked that the number of left & right ()'s are
3758 equal, so this loop will not be infinite. */
3762 if (*base_string
== ')')
3764 if (*base_string
== '(')
3767 while (parens_balanced
);
3769 temp_string
= base_string
;
3771 /* Skip past '(' and whitespace. */
3773 if (is_space_char (*base_string
))
3776 if (*base_string
== ','
3777 || ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3778 && (i
.base_reg
= parse_register (base_string
, &end_op
)) != NULL
))
3780 displacement_string_end
= temp_string
;
3782 i
.types
[this_operand
] |= BaseIndex
;
3786 base_string
= end_op
;
3787 if (is_space_char (*base_string
))
3791 /* There may be an index reg or scale factor here. */
3792 if (*base_string
== ',')
3795 if (is_space_char (*base_string
))
3798 if ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3799 && (i
.index_reg
= parse_register (base_string
, &end_op
)) != NULL
)
3801 base_string
= end_op
;
3802 if (is_space_char (*base_string
))
3804 if (*base_string
== ',')
3807 if (is_space_char (*base_string
))
3810 else if (*base_string
!= ')')
3812 as_bad (_("expecting `,' or `)' after index register in `%s'"),
3817 else if (*base_string
== REGISTER_PREFIX
)
3819 as_bad (_("bad register name `%s'"), base_string
);
3823 /* Check for scale factor. */
3824 if (isdigit ((unsigned char) *base_string
))
3826 if (!i386_scale (base_string
))
3830 if (is_space_char (*base_string
))
3832 if (*base_string
!= ')')
3834 as_bad (_("expecting `)' after scale factor in `%s'"),
3839 else if (!i
.index_reg
)
3841 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
3846 else if (*base_string
!= ')')
3848 as_bad (_("expecting `,' or `)' after base register in `%s'"),
3853 else if (*base_string
== REGISTER_PREFIX
)
3855 as_bad (_("bad register name `%s'"), base_string
);
3860 /* If there's an expression beginning the operand, parse it,
3861 assuming displacement_string_start and
3862 displacement_string_end are meaningful. */
3863 if (displacement_string_start
!= displacement_string_end
)
3865 if (!i386_displacement (displacement_string_start
,
3866 displacement_string_end
))
3870 /* Special case for (%dx) while doing input/output op. */
3872 && i
.base_reg
->reg_type
== (Reg16
| InOutPortReg
)
3874 && i
.log2_scale_factor
== 0
3875 && i
.seg
[i
.mem_operands
] == 0
3876 && (i
.types
[this_operand
] & Disp
) == 0)
3878 i
.types
[this_operand
] = InOutPortReg
;
3882 if (i386_index_check (operand_string
) == 0)
3888 /* It's not a memory operand; argh! */
3889 as_bad (_("invalid char %s beginning operand %d `%s'"),
3890 output_invalid (*op_string
),
3895 return 1; /* Normal return. */
3898 /* md_estimate_size_before_relax()
3900 Called just before relax() for rs_machine_dependent frags. The x86
3901 assembler uses these frags to handle variable size jump
3904 Any symbol that is now undefined will not become defined.
3905 Return the correct fr_subtype in the frag.
3906 Return the initial "guess for variable size of frag" to caller.
3907 The guess is actually the growth beyond the fixed part. Whatever
3908 we do to grow the fixed or variable part contributes to our
3912 md_estimate_size_before_relax (fragP
, segment
)
3913 register fragS
*fragP
;
3914 register segT segment
;
3916 /* We've already got fragP->fr_subtype right; all we have to do is
3917 check for un-relaxable symbols. On an ELF system, we can't relax
3918 an externally visible symbol, because it may be overridden by a
3920 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
3921 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3922 || S_IS_EXTERNAL (fragP
->fr_symbol
)
3923 || S_IS_WEAK (fragP
->fr_symbol
)
3927 /* Symbol is undefined in this segment, or we need to keep a
3928 reloc so that weak symbols can be overridden. */
3929 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
3930 #ifdef BFD_ASSEMBLER
3931 enum bfd_reloc_code_real reloc_type
;
3935 unsigned char *opcode
;
3938 if (fragP
->fr_var
!= NO_RELOC
)
3939 reloc_type
= fragP
->fr_var
;
3941 reloc_type
= BFD_RELOC_16_PCREL
;
3943 reloc_type
= BFD_RELOC_32_PCREL
;
3945 old_fr_fix
= fragP
->fr_fix
;
3946 opcode
= (unsigned char *) fragP
->fr_opcode
;
3948 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
3951 /* Make jmp (0xeb) a (d)word displacement jump. */
3953 fragP
->fr_fix
+= size
;
3954 fix_new (fragP
, old_fr_fix
, size
,
3956 fragP
->fr_offset
, 1,
3961 if (no_cond_jump_promotion
)
3965 /* Negate the condition, and branch past an
3966 unconditional jump. */
3969 /* Insert an unconditional jump. */
3971 /* We added two extra opcode bytes, and have a two byte
3973 fragP
->fr_fix
+= 2 + 2;
3974 fix_new (fragP
, old_fr_fix
+ 2, 2,
3976 fragP
->fr_offset
, 1,
3983 if (no_cond_jump_promotion
)
3985 /* This changes the byte-displacement jump 0x7N
3986 to the (d)word-displacement jump 0x0f,0x8N. */
3987 opcode
[1] = opcode
[0] + 0x10;
3988 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
3989 /* We've added an opcode byte. */
3990 fragP
->fr_fix
+= 1 + size
;
3991 fix_new (fragP
, old_fr_fix
+ 1, size
,
3993 fragP
->fr_offset
, 1,
3998 BAD_CASE (fragP
->fr_subtype
);
4002 return fragP
->fr_fix
- old_fr_fix
;
4004 /* Guess a short jump. */
4008 /* Called after relax() is finished.
4010 In: Address of frag.
4011 fr_type == rs_machine_dependent.
4012 fr_subtype is what the address relaxed to.
4014 Out: Any fixSs and constants are set up.
4015 Caller will turn frag into a ".space 0". */
4017 #ifndef BFD_ASSEMBLER
4019 md_convert_frag (headers
, sec
, fragP
)
4020 object_headers
*headers ATTRIBUTE_UNUSED
;
4021 segT sec ATTRIBUTE_UNUSED
;
4022 register fragS
*fragP
;
4025 md_convert_frag (abfd
, sec
, fragP
)
4026 bfd
*abfd ATTRIBUTE_UNUSED
;
4027 segT sec ATTRIBUTE_UNUSED
;
4028 register fragS
*fragP
;
4031 register unsigned char *opcode
;
4032 unsigned char *where_to_put_displacement
= NULL
;
4033 offsetT target_address
;
4034 offsetT opcode_address
;
4035 unsigned int extension
= 0;
4036 offsetT displacement_from_opcode_start
;
4038 opcode
= (unsigned char *) fragP
->fr_opcode
;
4040 /* Address we want to reach in file space. */
4041 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
4042 #ifdef BFD_ASSEMBLER
4043 /* Not needed otherwise? */
4044 target_address
+= symbol_get_frag (fragP
->fr_symbol
)->fr_address
;
4047 /* Address opcode resides at in file space. */
4048 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
4050 /* Displacement from opcode start to fill into instruction. */
4051 displacement_from_opcode_start
= target_address
- opcode_address
;
4053 if ((fragP
->fr_subtype
& BIG
) == 0)
4055 /* Don't have to change opcode. */
4056 extension
= 1; /* 1 opcode + 1 displacement */
4057 where_to_put_displacement
= &opcode
[1];
4061 if (no_cond_jump_promotion
4062 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
4063 as_warn_where (fragP
->fr_file
, fragP
->fr_line
, _("long jump required"));
4065 switch (fragP
->fr_subtype
)
4067 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
4068 extension
= 4; /* 1 opcode + 4 displacement */
4070 where_to_put_displacement
= &opcode
[1];
4073 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
4074 extension
= 2; /* 1 opcode + 2 displacement */
4076 where_to_put_displacement
= &opcode
[1];
4079 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
4080 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
4081 extension
= 5; /* 2 opcode + 4 displacement */
4082 opcode
[1] = opcode
[0] + 0x10;
4083 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4084 where_to_put_displacement
= &opcode
[2];
4087 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
4088 extension
= 3; /* 2 opcode + 2 displacement */
4089 opcode
[1] = opcode
[0] + 0x10;
4090 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4091 where_to_put_displacement
= &opcode
[2];
4094 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
4099 where_to_put_displacement
= &opcode
[3];
4103 BAD_CASE (fragP
->fr_subtype
);
4108 /* Now put displacement after opcode. */
4109 md_number_to_chars ((char *) where_to_put_displacement
,
4110 (valueT
) (displacement_from_opcode_start
- extension
),
4111 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
4112 fragP
->fr_fix
+= extension
;
4115 /* Size of byte displacement jmp. */
4116 int md_short_jump_size
= 2;
4118 /* Size of dword displacement jmp. */
4119 int md_long_jump_size
= 5;
4121 /* Size of relocation record. */
4122 const int md_reloc_size
= 8;
4125 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4127 addressT from_addr
, to_addr
;
4128 fragS
*frag ATTRIBUTE_UNUSED
;
4129 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4133 offset
= to_addr
- (from_addr
+ 2);
4134 /* Opcode for byte-disp jump. */
4135 md_number_to_chars (ptr
, (valueT
) 0xeb, 1);
4136 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 1);
4140 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4142 addressT from_addr
, to_addr
;
4143 fragS
*frag ATTRIBUTE_UNUSED
;
4144 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4148 offset
= to_addr
- (from_addr
+ 5);
4149 md_number_to_chars (ptr
, (valueT
) 0xe9, 1);
4150 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 4);
4153 /* Apply a fixup (fixS) to segment data, once it has been determined
4154 by our caller that we have all the info we need to fix it up.
4156 On the 386, immediates, displacements, and data pointers are all in
4157 the same (little-endian) format, so we don't need to care about which
4161 md_apply_fix3 (fixP
, valp
, seg
)
4162 /* The fix we're to put in. */
4165 /* Pointer to the value of the bits. */
4168 /* Segment fix is from. */
4169 segT seg ATTRIBUTE_UNUSED
;
4171 register char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
4172 valueT value
= *valp
;
4174 #if defined (BFD_ASSEMBLER) && !defined (TE_Mach)
4177 switch (fixP
->fx_r_type
)
4183 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
4186 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
4189 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
4194 /* This is a hack. There should be a better way to handle this.
4195 This covers for the fact that bfd_install_relocation will
4196 subtract the current location (for partial_inplace, PC relative
4197 relocations); see more below. */
4198 if ((fixP
->fx_r_type
== BFD_RELOC_32_PCREL
4199 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
4200 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
4201 && fixP
->fx_addsy
&& !use_rela_relocations
)
4204 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4206 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
4209 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4211 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4212 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
4214 segT fseg
= S_GET_SEGMENT (fixP
->fx_addsy
);
4217 || (symbol_section_p (fixP
->fx_addsy
)
4218 && fseg
!= absolute_section
))
4219 && ! S_IS_EXTERNAL (fixP
->fx_addsy
)
4220 && ! S_IS_WEAK (fixP
->fx_addsy
)
4221 && S_IS_DEFINED (fixP
->fx_addsy
)
4222 && ! S_IS_COMMON (fixP
->fx_addsy
))
4224 /* Yes, we add the values in twice. This is because
4225 bfd_perform_relocation subtracts them out again. I think
4226 bfd_perform_relocation is broken, but I don't dare change
4228 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4232 #if defined (OBJ_COFF) && defined (TE_PE)
4233 /* For some reason, the PE format does not store a section
4234 address offset for a PC relative symbol. */
4235 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
4236 value
+= md_pcrel_from (fixP
);
4240 /* Fix a few things - the dynamic linker expects certain values here,
4241 and we must not dissappoint it. */
4242 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4243 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4245 switch (fixP
->fx_r_type
)
4247 case BFD_RELOC_386_PLT32
:
4248 case BFD_RELOC_X86_64_PLT32
:
4249 /* Make the jump instruction point to the address of the operand. At
4250 runtime we merely add the offset to the actual PLT entry. */
4253 case BFD_RELOC_386_GOTPC
:
4255 /* This is tough to explain. We end up with this one if we have
4256 * operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal
4257 * here is to obtain the absolute address of the GOT, and it is strongly
4258 * preferable from a performance point of view to avoid using a runtime
4259 * relocation for this. The actual sequence of instructions often look
4265 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4267 * The call and pop essentially return the absolute address of
4268 * the label .L66 and store it in %ebx. The linker itself will
4269 * ultimately change the first operand of the addl so that %ebx points to
4270 * the GOT, but to keep things simple, the .o file must have this operand
4271 * set so that it generates not the absolute address of .L66, but the
4272 * absolute address of itself. This allows the linker itself simply
4273 * treat a GOTPC relocation as asking for a pcrel offset to the GOT to be
4274 * added in, and the addend of the relocation is stored in the operand
4275 * field for the instruction itself.
4277 * Our job here is to fix the operand so that it would add the correct
4278 * offset so that %ebx would point to itself. The thing that is tricky is
4279 * that .-.L66 will point to the beginning of the instruction, so we need
4280 * to further modify the operand so that it will point to itself.
4281 * There are other cases where you have something like:
4283 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4285 * and here no correction would be required. Internally in the assembler
4286 * we treat operands of this form as not being pcrel since the '.' is
4287 * explicitly mentioned, and I wonder whether it would simplify matters
4288 * to do it this way. Who knows. In earlier versions of the PIC patches,
4289 * the pcrel_adjust field was used to store the correction, but since the
4290 * expression is not pcrel, I felt it would be confusing to do it this
4295 case BFD_RELOC_386_GOT32
:
4296 case BFD_RELOC_X86_64_GOT32
:
4297 value
= 0; /* Fully resolved at runtime. No addend. */
4299 case BFD_RELOC_386_GOTOFF
:
4300 case BFD_RELOC_X86_64_GOTPCREL
:
4303 case BFD_RELOC_VTABLE_INHERIT
:
4304 case BFD_RELOC_VTABLE_ENTRY
:
4311 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
4313 #endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */
4315 #ifndef BFD_ASSEMBLER
4316 md_number_to_chars (p
, value
, fixP
->fx_size
);
4318 /* Are we finished with this relocation now? */
4319 if (fixP
->fx_addsy
== 0 && fixP
->fx_pcrel
== 0)
4321 else if (use_rela_relocations
)
4323 fixP
->fx_no_overflow
= 1;
4326 md_number_to_chars (p
, value
, fixP
->fx_size
);
4332 #define MAX_LITTLENUMS 6
4334 /* Turn the string pointed to by litP into a floating point constant
4335 of type TYPE, and emit the appropriate bytes. The number of
4336 LITTLENUMS emitted is stored in *SIZEP. An error message is
4337 returned, or NULL on OK. */
4340 md_atof (type
, litP
, sizeP
)
4346 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4347 LITTLENUM_TYPE
*wordP
;
4369 return _("Bad call to md_atof ()");
4371 t
= atof_ieee (input_line_pointer
, type
, words
);
4373 input_line_pointer
= t
;
4375 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
4376 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
4377 the bigendian 386. */
4378 for (wordP
= words
+ prec
- 1; prec
--;)
4380 md_number_to_chars (litP
, (valueT
) (*wordP
--), sizeof (LITTLENUM_TYPE
));
4381 litP
+= sizeof (LITTLENUM_TYPE
);
4386 char output_invalid_buf
[8];
4393 sprintf (output_invalid_buf
, "'%c'", c
);
4395 sprintf (output_invalid_buf
, "(0x%x)", (unsigned) c
);
4396 return output_invalid_buf
;
4399 /* REG_STRING starts *before* REGISTER_PREFIX. */
4401 static const reg_entry
*
4402 parse_register (reg_string
, end_op
)
4406 char *s
= reg_string
;
4408 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
4411 /* Skip possible REGISTER_PREFIX and possible whitespace. */
4412 if (*s
== REGISTER_PREFIX
)
4415 if (is_space_char (*s
))
4419 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
4421 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
4422 return (const reg_entry
*) NULL
;
4426 /* For naked regs, make sure that we are not dealing with an identifier.
4427 This prevents confusing an identifier like `eax_var' with register
4429 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
4430 return (const reg_entry
*) NULL
;
4434 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
4436 /* Handle floating point regs, allowing spaces in the (i) part. */
4437 if (r
== i386_regtab
/* %st is first entry of table */)
4439 if (is_space_char (*s
))
4444 if (is_space_char (*s
))
4446 if (*s
>= '0' && *s
<= '7')
4448 r
= &i386_float_regtab
[*s
- '0'];
4450 if (is_space_char (*s
))
4458 /* We have "%st(" then garbage. */
4459 return (const reg_entry
*) NULL
;
4466 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4467 const char *md_shortopts
= "kVQ:sq";
4469 const char *md_shortopts
= "q";
4472 struct option md_longopts
[] = {
4473 #define OPTION_32 (OPTION_MD_BASE + 0)
4474 {"32", no_argument
, NULL
, OPTION_32
},
4475 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4476 #define OPTION_64 (OPTION_MD_BASE + 1)
4477 {"64", no_argument
, NULL
, OPTION_64
},
4479 {NULL
, no_argument
, NULL
, 0}
4481 size_t md_longopts_size
= sizeof (md_longopts
);
4484 md_parse_option (c
, arg
)
4486 char *arg ATTRIBUTE_UNUSED
;
4494 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4495 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
4496 should be emitted or not. FIXME: Not implemented. */
4500 /* -V: SVR4 argument to print version ID. */
4502 print_version_id ();
4505 /* -k: Ignore for FreeBSD compatibility. */
4510 /* -s: On i386 Solaris, this tells the native assembler to use
4511 .stab instead of .stab.excl. We always use .stab anyhow. */
4516 const char **list
, **l
;
4518 list
= bfd_target_list ();
4519 for (l
= list
; *l
!= NULL
; l
++)
4520 if (strcmp (*l
, "elf64-x86-64") == 0)
4522 default_arch
= "x86_64";
4526 as_fatal (_("No compiled in support for x86_64"));
4533 default_arch
= "i386";
4543 md_show_usage (stream
)
4546 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4547 fprintf (stream
, _("\
4549 -V print assembler version number\n\
4551 -q quieten some warnings\n\
4554 fprintf (stream
, _("\
4555 -q quieten some warnings\n"));
4559 #ifdef BFD_ASSEMBLER
4560 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
4561 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
4563 /* Pick the target format to use. */
4566 i386_target_format ()
4568 if (!strcmp (default_arch
, "x86_64"))
4569 set_code_flag (CODE_64BIT
);
4570 else if (!strcmp (default_arch
, "i386"))
4571 set_code_flag (CODE_32BIT
);
4573 as_fatal (_("Unknown architecture"));
4574 switch (OUTPUT_FLAVOR
)
4576 #ifdef OBJ_MAYBE_AOUT
4577 case bfd_target_aout_flavour
:
4578 return AOUT_TARGET_FORMAT
;
4580 #ifdef OBJ_MAYBE_COFF
4581 case bfd_target_coff_flavour
:
4584 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
4585 case bfd_target_elf_flavour
:
4587 if (flag_code
== CODE_64BIT
)
4588 use_rela_relocations
= 1;
4589 return flag_code
== CODE_64BIT
? "elf64-x86-64" : "elf32-i386";
4598 #endif /* OBJ_MAYBE_ more than one */
4599 #endif /* BFD_ASSEMBLER */
4602 md_undefined_symbol (name
)
4605 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
4606 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
4607 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
4608 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
4612 if (symbol_find (name
))
4613 as_bad (_("GOT already in symbol table"));
4614 GOT_symbol
= symbol_new (name
, undefined_section
,
4615 (valueT
) 0, &zero_address_frag
);
4622 /* Round up a section size to the appropriate boundary. */
4625 md_section_align (segment
, size
)
4626 segT segment ATTRIBUTE_UNUSED
;
4629 #ifdef BFD_ASSEMBLER
4630 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4631 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
4633 /* For a.out, force the section size to be aligned. If we don't do
4634 this, BFD will align it for us, but it will not write out the
4635 final bytes of the section. This may be a bug in BFD, but it is
4636 easier to fix it here since that is how the other a.out targets
4640 align
= bfd_get_section_alignment (stdoutput
, segment
);
4641 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
4649 /* On the i386, PC-relative offsets are relative to the start of the
4650 next instruction. That is, the address of the offset, plus its
4651 size, since the offset is always the last part of the insn. */
4654 md_pcrel_from (fixP
)
4657 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4664 int ignore ATTRIBUTE_UNUSED
;
4668 temp
= get_absolute_expression ();
4669 subseg_set (bss_section
, (subsegT
) temp
);
4670 demand_empty_rest_of_line ();
4675 #ifdef BFD_ASSEMBLER
4678 i386_validate_fix (fixp
)
4681 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
4683 /* GOTOFF relocation are nonsense in 64bit mode. */
4684 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
4686 if (flag_code
!= CODE_64BIT
)
4688 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
4692 if (flag_code
== CODE_64BIT
)
4694 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
4701 tc_gen_reloc (section
, fixp
)
4702 asection
*section ATTRIBUTE_UNUSED
;
4706 bfd_reloc_code_real_type code
;
4708 switch (fixp
->fx_r_type
)
4710 case BFD_RELOC_X86_64_PLT32
:
4711 case BFD_RELOC_X86_64_GOT32
:
4712 case BFD_RELOC_X86_64_GOTPCREL
:
4713 case BFD_RELOC_386_PLT32
:
4714 case BFD_RELOC_386_GOT32
:
4715 case BFD_RELOC_386_GOTOFF
:
4716 case BFD_RELOC_386_GOTPC
:
4717 case BFD_RELOC_X86_64_32S
:
4719 case BFD_RELOC_VTABLE_ENTRY
:
4720 case BFD_RELOC_VTABLE_INHERIT
:
4721 code
= fixp
->fx_r_type
;
4726 switch (fixp
->fx_size
)
4729 as_bad (_("can not do %d byte pc-relative relocation"),
4731 code
= BFD_RELOC_32_PCREL
;
4733 case 1: code
= BFD_RELOC_8_PCREL
; break;
4734 case 2: code
= BFD_RELOC_16_PCREL
; break;
4735 case 4: code
= BFD_RELOC_32_PCREL
; break;
4740 switch (fixp
->fx_size
)
4743 as_bad (_("can not do %d byte relocation"), fixp
->fx_size
);
4744 code
= BFD_RELOC_32
;
4746 case 1: code
= BFD_RELOC_8
; break;
4747 case 2: code
= BFD_RELOC_16
; break;
4748 case 4: code
= BFD_RELOC_32
; break;
4749 case 8: code
= BFD_RELOC_64
; break;
4755 if (code
== BFD_RELOC_32
4757 && fixp
->fx_addsy
== GOT_symbol
)
4759 /* We don't support GOTPC on 64bit targets. */
4760 if (flag_code
== CODE_64BIT
)
4762 code
= BFD_RELOC_386_GOTPC
;
4765 rel
= (arelent
*) xmalloc (sizeof (arelent
));
4766 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
4767 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
4769 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
4770 if (!use_rela_relocations
)
4772 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
4773 vtable entry to be used in the relocation's section offset. */
4774 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
4775 rel
->address
= fixp
->fx_offset
;
4778 rel
->addend
= fixp
->fx_addnumber
;
4782 /* Use the rela in 64bit mode. */
4785 rel
->addend
= fixp
->fx_offset
;
4787 rel
->addend
-= fixp
->fx_size
;
4790 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
4791 if (rel
->howto
== NULL
)
4793 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
4794 _("cannot represent relocation type %s"),
4795 bfd_get_reloc_code_name (code
));
4796 /* Set howto to a garbage value so that we can keep going. */
4797 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
4798 assert (rel
->howto
!= NULL
);
4804 #else /* ! BFD_ASSEMBLER */
4806 #if (defined(OBJ_AOUT) | defined(OBJ_BOUT))
4808 tc_aout_fix_to_chars (where
, fixP
, segment_address_in_file
)
4811 relax_addressT segment_address_in_file
;
4813 /* In: length of relocation (or of address) in chars: 1, 2 or 4.
4814 Out: GNU LD relocation length code: 0, 1, or 2. */
4816 static const unsigned char nbytes_r_length
[] = { 42, 0, 1, 42, 2 };
4819 know (fixP
->fx_addsy
!= NULL
);
4821 md_number_to_chars (where
,
4822 (valueT
) (fixP
->fx_frag
->fr_address
4823 + fixP
->fx_where
- segment_address_in_file
),
4826 r_symbolnum
= (S_IS_DEFINED (fixP
->fx_addsy
)
4827 ? S_GET_TYPE (fixP
->fx_addsy
)
4828 : fixP
->fx_addsy
->sy_number
);
4830 where
[6] = (r_symbolnum
>> 16) & 0x0ff;
4831 where
[5] = (r_symbolnum
>> 8) & 0x0ff;
4832 where
[4] = r_symbolnum
& 0x0ff;
4833 where
[7] = ((((!S_IS_DEFINED (fixP
->fx_addsy
)) << 3) & 0x08)
4834 | ((nbytes_r_length
[fixP
->fx_size
] << 1) & 0x06)
4835 | (((fixP
->fx_pcrel
<< 0) & 0x01) & 0x0f));
4838 #endif /* OBJ_AOUT or OBJ_BOUT. */
4840 #if defined (I386COFF)
4843 tc_coff_fix2rtype (fixP
)
4846 if (fixP
->fx_r_type
== R_IMAGEBASE
)
4849 return (fixP
->fx_pcrel
?
4850 (fixP
->fx_size
== 1 ? R_PCRBYTE
:
4851 fixP
->fx_size
== 2 ? R_PCRWORD
:
4853 (fixP
->fx_size
== 1 ? R_RELBYTE
:
4854 fixP
->fx_size
== 2 ? R_RELWORD
:
4859 tc_coff_sizemachdep (frag
)
4863 return (frag
->fr_next
->fr_address
- frag
->fr_address
);
4868 #endif /* I386COFF */
4870 #endif /* ! BFD_ASSEMBLER */
4872 /* Parse operands using Intel syntax. This implements a recursive descent
4873 parser based on the BNF grammar published in Appendix B of the MASM 6.1
4876 FIXME: We do not recognize the full operand grammar defined in the MASM
4877 documentation. In particular, all the structure/union and
4878 high-level macro operands are missing.
4880 Uppercase words are terminals, lower case words are non-terminals.
4881 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
4882 bars '|' denote choices. Most grammar productions are implemented in
4883 functions called 'intel_<production>'.
4885 Initial production is 'expr'.
4891 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
4893 constant digits [[ radixOverride ]]
4895 dataType BYTE | WORD | DWORD | QWORD | XWORD
4928 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
4929 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
4931 hexdigit a | b | c | d | e | f
4932 | A | B | C | D | E | F
4942 register specialRegister
4946 segmentRegister CS | DS | ES | FS | GS | SS
4948 specialRegister CR0 | CR2 | CR3
4949 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
4950 | TR3 | TR4 | TR5 | TR6 | TR7
4952 We simplify the grammar in obvious places (e.g., register parsing is
4953 done by calling parse_register) and eliminate immediate left recursion
4954 to implement a recursive-descent parser.
4994 /* Parsing structure for the intel syntax parser. Used to implement the
4995 semantic actions for the operand grammar. */
4996 struct intel_parser_s
4998 char *op_string
; /* The string being parsed. */
4999 int got_a_float
; /* Whether the operand is a float. */
5000 int op_modifier
; /* Operand modifier. */
5001 int is_mem
; /* 1 if operand is memory reference. */
5002 const reg_entry
*reg
; /* Last register reference found. */
5003 char *disp
; /* Displacement string being built. */
5006 static struct intel_parser_s intel_parser
;
5008 /* Token structure for parsing intel syntax. */
5011 int code
; /* Token code. */
5012 const reg_entry
*reg
; /* Register entry for register tokens. */
5013 char *str
; /* String representation. */
5016 static struct intel_token cur_token
, prev_token
;
5018 /* Token codes for the intel parser. Since T_SHORT is already used
5019 by COFF, undefine it first to prevent a warning. */
5034 /* Prototypes for intel parser functions. */
5035 static int intel_match_token
PARAMS ((int code
));
5036 static void intel_get_token
PARAMS ((void));
5037 static void intel_putback_token
PARAMS ((void));
5038 static int intel_expr
PARAMS ((void));
5039 static int intel_e05
PARAMS ((void));
5040 static int intel_e05_1
PARAMS ((void));
5041 static int intel_e06
PARAMS ((void));
5042 static int intel_e06_1
PARAMS ((void));
5043 static int intel_e09
PARAMS ((void));
5044 static int intel_e09_1
PARAMS ((void));
5045 static int intel_e10
PARAMS ((void));
5046 static int intel_e10_1
PARAMS ((void));
5047 static int intel_e11
PARAMS ((void));
5050 i386_intel_operand (operand_string
, got_a_float
)
5051 char *operand_string
;
5057 /* Initialize token holders. */
5058 cur_token
.code
= prev_token
.code
= T_NIL
;
5059 cur_token
.reg
= prev_token
.reg
= NULL
;
5060 cur_token
.str
= prev_token
.str
= NULL
;
5062 /* Initialize parser structure. */
5063 p
= intel_parser
.op_string
= (char *) malloc (strlen (operand_string
) + 1);
5066 strcpy (intel_parser
.op_string
, operand_string
);
5067 intel_parser
.got_a_float
= got_a_float
;
5068 intel_parser
.op_modifier
= -1;
5069 intel_parser
.is_mem
= 0;
5070 intel_parser
.reg
= NULL
;
5071 intel_parser
.disp
= (char *) malloc (strlen (operand_string
) + 1);
5072 if (intel_parser
.disp
== NULL
)
5074 intel_parser
.disp
[0] = '\0';
5076 /* Read the first token and start the parser. */
5078 ret
= intel_expr ();
5082 /* If we found a memory reference, hand it over to i386_displacement
5083 to fill in the rest of the operand fields. */
5084 if (intel_parser
.is_mem
)
5086 if ((i
.mem_operands
== 1
5087 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
5088 || i
.mem_operands
== 2)
5090 as_bad (_("too many memory references for '%s'"),
5091 current_templates
->start
->name
);
5096 char *s
= intel_parser
.disp
;
5099 /* Add the displacement expression. */
5101 ret
= i386_displacement (s
, s
+ strlen (s
))
5102 && i386_index_check (s
);
5106 /* Constant and OFFSET expressions are handled by i386_immediate. */
5107 else if (intel_parser
.op_modifier
== OFFSET_FLAT
5108 || intel_parser
.reg
== NULL
)
5109 ret
= i386_immediate (intel_parser
.disp
);
5113 free (intel_parser
.disp
);
5123 /* expr SHORT e05 */
5124 if (cur_token
.code
== T_SHORT
)
5126 intel_parser
.op_modifier
= SHORT
;
5127 intel_match_token (T_SHORT
);
5129 return (intel_e05 ());
5134 return intel_e05 ();
5144 return (intel_e06 () && intel_e05_1 ());
5150 /* e05' addOp e06 e05' */
5151 if (cur_token
.code
== '+' || cur_token
.code
== '-')
5153 strcat (intel_parser
.disp
, cur_token
.str
);
5154 intel_match_token (cur_token
.code
);
5156 return (intel_e06 () && intel_e05_1 ());
5171 return (intel_e09 () && intel_e06_1 ());
5177 /* e06' mulOp e09 e06' */
5178 if (cur_token
.code
== '*' || cur_token
.code
== '/')
5180 strcat (intel_parser
.disp
, cur_token
.str
);
5181 intel_match_token (cur_token
.code
);
5183 return (intel_e09 () && intel_e06_1 ());
5191 /* e09 OFFSET e10 e09'
5200 /* e09 OFFSET e10 e09' */
5201 if (cur_token
.code
== T_OFFSET
)
5203 intel_parser
.is_mem
= 0;
5204 intel_parser
.op_modifier
= OFFSET_FLAT
;
5205 intel_match_token (T_OFFSET
);
5207 return (intel_e10 () && intel_e09_1 ());
5212 return (intel_e10 () && intel_e09_1 ());
5218 /* e09' PTR e10 e09' */
5219 if (cur_token
.code
== T_PTR
)
5221 if (prev_token
.code
== T_BYTE
)
5222 i
.suffix
= BYTE_MNEM_SUFFIX
;
5224 else if (prev_token
.code
== T_WORD
)
5226 if (intel_parser
.got_a_float
== 2) /* "fi..." */
5227 i
.suffix
= SHORT_MNEM_SUFFIX
;
5229 i
.suffix
= WORD_MNEM_SUFFIX
;
5232 else if (prev_token
.code
== T_DWORD
)
5234 if (intel_parser
.got_a_float
== 1) /* "f..." */
5235 i
.suffix
= SHORT_MNEM_SUFFIX
;
5237 i
.suffix
= LONG_MNEM_SUFFIX
;
5240 else if (prev_token
.code
== T_QWORD
)
5242 if (intel_parser
.got_a_float
== 1) /* "f..." */
5243 i
.suffix
= LONG_MNEM_SUFFIX
;
5245 i
.suffix
= QWORD_MNEM_SUFFIX
;
5248 else if (prev_token
.code
== T_XWORD
)
5249 i
.suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
5253 as_bad (_("Unknown operand modifier `%s'\n"), prev_token
.str
);
5257 intel_match_token (T_PTR
);
5259 return (intel_e10 () && intel_e09_1 ());
5262 /* e09 : e10 e09' */
5263 else if (cur_token
.code
== ':')
5265 /* Mark as a memory operand only if it's not already known to be an
5266 offset expression. */
5267 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5268 intel_parser
.is_mem
= 1;
5270 return (intel_match_token (':') && intel_e10 () && intel_e09_1 ());
5285 return (intel_e11 () && intel_e10_1 ());
5291 /* e10' [ expr ] e10' */
5292 if (cur_token
.code
== '[')
5294 intel_match_token ('[');
5296 /* Mark as a memory operand only if it's not already known to be an
5297 offset expression. If it's an offset expression, we need to keep
5299 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5300 intel_parser
.is_mem
= 1;
5302 strcat (intel_parser
.disp
, "[");
5304 /* Add a '+' to the displacement string if necessary. */
5305 if (*intel_parser
.disp
!= '\0'
5306 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
5307 strcat (intel_parser
.disp
, "+");
5309 if (intel_expr () && intel_match_token (']'))
5311 /* Preserve brackets when the operand is an offset expression. */
5312 if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5313 strcat (intel_parser
.disp
, "]");
5315 return intel_e10_1 ();
5342 if (cur_token
.code
== '(')
5344 intel_match_token ('(');
5345 strcat (intel_parser
.disp
, "(");
5347 if (intel_expr () && intel_match_token (')'))
5349 strcat (intel_parser
.disp
, ")");
5357 else if (cur_token
.code
== '[')
5359 intel_match_token ('[');
5361 /* Mark as a memory operand only if it's not already known to be an
5362 offset expression. If it's an offset expression, we need to keep
5364 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5365 intel_parser
.is_mem
= 1;
5367 strcat (intel_parser
.disp
, "[");
5369 /* Operands for jump/call inside brackets denote absolute addresses. */
5370 if (current_templates
->start
->opcode_modifier
& Jump
5371 || current_templates
->start
->opcode_modifier
& JumpDword
5372 || current_templates
->start
->opcode_modifier
& JumpByte
5373 || current_templates
->start
->opcode_modifier
& JumpInterSegment
)
5374 i
.types
[this_operand
] |= JumpAbsolute
;
5376 /* Add a '+' to the displacement string if necessary. */
5377 if (*intel_parser
.disp
!= '\0'
5378 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
5379 strcat (intel_parser
.disp
, "+");
5381 if (intel_expr () && intel_match_token (']'))
5383 /* Preserve brackets when the operand is an offset expression. */
5384 if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5385 strcat (intel_parser
.disp
, "]");
5398 else if (cur_token
.code
== T_BYTE
5399 || cur_token
.code
== T_WORD
5400 || cur_token
.code
== T_DWORD
5401 || cur_token
.code
== T_QWORD
5402 || cur_token
.code
== T_XWORD
)
5404 intel_match_token (cur_token
.code
);
5411 else if (cur_token
.code
== '$' || cur_token
.code
== '.')
5413 strcat (intel_parser
.disp
, cur_token
.str
);
5414 intel_match_token (cur_token
.code
);
5416 /* Mark as a memory operand only if it's not already known to be an
5417 offset expression. */
5418 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5419 intel_parser
.is_mem
= 1;
5425 else if (cur_token
.code
== T_REG
)
5427 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
5429 intel_match_token (T_REG
);
5431 /* Check for segment change. */
5432 if (cur_token
.code
== ':')
5434 if (reg
->reg_type
& (SReg2
| SReg3
))
5436 switch (reg
->reg_num
)
5439 i
.seg
[i
.mem_operands
] = &es
;
5442 i
.seg
[i
.mem_operands
] = &cs
;
5445 i
.seg
[i
.mem_operands
] = &ss
;
5448 i
.seg
[i
.mem_operands
] = &ds
;
5451 i
.seg
[i
.mem_operands
] = &fs
;
5454 i
.seg
[i
.mem_operands
] = &gs
;
5460 as_bad (_("`%s' is not a valid segment register"), reg
->reg_name
);
5465 /* Not a segment register. Check for register scaling. */
5466 else if (cur_token
.code
== '*')
5468 if (!intel_parser
.is_mem
)
5470 as_bad (_("Register scaling only allowed in memory operands."));
5474 /* What follows must be a valid scale. */
5475 if (intel_match_token ('*')
5476 && strchr ("01248", *cur_token
.str
))
5479 i
.types
[this_operand
] |= BaseIndex
;
5481 /* Set the scale after setting the register (otherwise,
5482 i386_scale will complain) */
5483 i386_scale (cur_token
.str
);
5484 intel_match_token (T_CONST
);
5488 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5494 /* No scaling. If this is a memory operand, the register is either a
5495 base register (first occurrence) or an index register (second
5497 else if (intel_parser
.is_mem
&& !(reg
->reg_type
& (SReg2
| SReg3
)))
5499 if (i
.base_reg
&& i
.index_reg
)
5501 as_bad (_("Too many register references in memory operand.\n"));
5505 if (i
.base_reg
== NULL
)
5510 i
.types
[this_operand
] |= BaseIndex
;
5513 /* Offset modifier. Add the register to the displacement string to be
5514 parsed as an immediate expression after we're done. */
5515 else if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5516 strcat (intel_parser
.disp
, reg
->reg_name
);
5518 /* It's neither base nor index nor offset. */
5521 i
.types
[this_operand
] |= reg
->reg_type
& ~BaseIndex
;
5522 i
.op
[this_operand
].regs
= reg
;
5526 /* Since registers are not part of the displacement string (except
5527 when we're parsing offset operands), we may need to remove any
5528 preceding '+' from the displacement string. */
5529 if (*intel_parser
.disp
!= '\0'
5530 && intel_parser
.op_modifier
!= OFFSET_FLAT
)
5532 char *s
= intel_parser
.disp
;
5533 s
+= strlen (s
) - 1;
5542 else if (cur_token
.code
== T_ID
)
5544 /* Add the identifier to the displacement string. */
5545 strcat (intel_parser
.disp
, cur_token
.str
);
5546 intel_match_token (T_ID
);
5548 /* The identifier represents a memory reference only if it's not
5549 preceded by an offset modifier. */
5550 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5551 intel_parser
.is_mem
= 1;
5557 else if (cur_token
.code
== T_CONST
5558 || cur_token
.code
== '-'
5559 || cur_token
.code
== '+')
5563 /* Allow constants that start with `+' or `-'. */
5564 if (cur_token
.code
== '-' || cur_token
.code
== '+')
5566 strcat (intel_parser
.disp
, cur_token
.str
);
5567 intel_match_token (cur_token
.code
);
5568 if (cur_token
.code
!= T_CONST
)
5570 as_bad (_("Syntax error. Expecting a constant. Got `%s'.\n"),
5576 save_str
= (char *) malloc (strlen (cur_token
.str
) + 1);
5577 if (save_str
== NULL
)
5579 strcpy (save_str
, cur_token
.str
);
5581 /* Get the next token to check for register scaling. */
5582 intel_match_token (cur_token
.code
);
5584 /* Check if this constant is a scaling factor for an index register. */
5585 if (cur_token
.code
== '*')
5587 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
5589 if (!intel_parser
.is_mem
)
5591 as_bad (_("Register scaling only allowed in memory operands."));
5595 /* The constant is followed by `* reg', so it must be
5597 if (strchr ("01248", *save_str
))
5599 i
.index_reg
= cur_token
.reg
;
5600 i
.types
[this_operand
] |= BaseIndex
;
5602 /* Set the scale after setting the register (otherwise,
5603 i386_scale will complain) */
5604 i386_scale (save_str
);
5605 intel_match_token (T_REG
);
5607 /* Since registers are not part of the displacement
5608 string, we may need to remove any preceding '+' from
5609 the displacement string. */
5610 if (*intel_parser
.disp
!= '\0')
5612 char *s
= intel_parser
.disp
;
5613 s
+= strlen (s
) - 1;
5626 /* The constant was not used for register scaling. Since we have
5627 already consumed the token following `*' we now need to put it
5628 back in the stream. */
5630 intel_putback_token ();
5633 /* Add the constant to the displacement string. */
5634 strcat (intel_parser
.disp
, save_str
);
5640 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
5644 /* Match the given token against cur_token. If they match, read the next
5645 token from the operand string. */
5647 intel_match_token (code
)
5650 if (cur_token
.code
== code
)
5657 as_bad (_("Unexpected token `%s'\n"), cur_token
.str
);
5662 /* Read a new token from intel_parser.op_string and store it in cur_token. */
5667 const reg_entry
*reg
;
5668 struct intel_token new_token
;
5670 new_token
.code
= T_NIL
;
5671 new_token
.reg
= NULL
;
5672 new_token
.str
= NULL
;
5674 /* Free the memory allocated to the previous token and move
5675 cur_token to prev_token. */
5677 free (prev_token
.str
);
5679 prev_token
= cur_token
;
5681 /* Skip whitespace. */
5682 while (is_space_char (*intel_parser
.op_string
))
5683 intel_parser
.op_string
++;
5685 /* Return an empty token if we find nothing else on the line. */
5686 if (*intel_parser
.op_string
== '\0')
5688 cur_token
= new_token
;
5692 /* The new token cannot be larger than the remainder of the operand
5694 new_token
.str
= (char *) malloc (strlen (intel_parser
.op_string
) + 1);
5695 if (new_token
.str
== NULL
)
5697 new_token
.str
[0] = '\0';
5699 if (strchr ("0123456789", *intel_parser
.op_string
))
5701 char *p
= new_token
.str
;
5702 char *q
= intel_parser
.op_string
;
5703 new_token
.code
= T_CONST
;
5705 /* Allow any kind of identifier char to encompass floating point and
5706 hexadecimal numbers. */
5707 while (is_identifier_char (*q
))
5711 /* Recognize special symbol names [0-9][bf]. */
5712 if (strlen (intel_parser
.op_string
) == 2
5713 && (intel_parser
.op_string
[1] == 'b'
5714 || intel_parser
.op_string
[1] == 'f'))
5715 new_token
.code
= T_ID
;
5718 else if (strchr ("+-/*:[]()", *intel_parser
.op_string
))
5720 new_token
.code
= *intel_parser
.op_string
;
5721 new_token
.str
[0] = *intel_parser
.op_string
;
5722 new_token
.str
[1] = '\0';
5725 else if ((*intel_parser
.op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
5726 && ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
))
5728 new_token
.code
= T_REG
;
5729 new_token
.reg
= reg
;
5731 if (*intel_parser
.op_string
== REGISTER_PREFIX
)
5733 new_token
.str
[0] = REGISTER_PREFIX
;
5734 new_token
.str
[1] = '\0';
5737 strcat (new_token
.str
, reg
->reg_name
);
5740 else if (is_identifier_char (*intel_parser
.op_string
))
5742 char *p
= new_token
.str
;
5743 char *q
= intel_parser
.op_string
;
5745 /* A '.' or '$' followed by an identifier char is an identifier.
5746 Otherwise, it's operator '.' followed by an expression. */
5747 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
5749 new_token
.code
= *q
;
5750 new_token
.str
[0] = *q
;
5751 new_token
.str
[1] = '\0';
5755 while (is_identifier_char (*q
) || *q
== '@')
5759 if (strcasecmp (new_token
.str
, "BYTE") == 0)
5760 new_token
.code
= T_BYTE
;
5762 else if (strcasecmp (new_token
.str
, "WORD") == 0)
5763 new_token
.code
= T_WORD
;
5765 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
5766 new_token
.code
= T_DWORD
;
5768 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
5769 new_token
.code
= T_QWORD
;
5771 else if (strcasecmp (new_token
.str
, "XWORD") == 0)
5772 new_token
.code
= T_XWORD
;
5774 else if (strcasecmp (new_token
.str
, "PTR") == 0)
5775 new_token
.code
= T_PTR
;
5777 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
5778 new_token
.code
= T_SHORT
;
5780 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
5782 new_token
.code
= T_OFFSET
;
5784 /* ??? This is not mentioned in the MASM grammar but gcc
5785 makes use of it with -mintel-syntax. OFFSET may be
5786 followed by FLAT: */
5787 if (strncasecmp (q
, " FLAT:", 6) == 0)
5788 strcat (new_token
.str
, " FLAT:");
5791 /* ??? This is not mentioned in the MASM grammar. */
5792 else if (strcasecmp (new_token
.str
, "FLAT") == 0)
5793 new_token
.code
= T_OFFSET
;
5796 new_token
.code
= T_ID
;
5801 as_bad (_("Unrecognized token `%s'\n"), intel_parser
.op_string
);
5803 intel_parser
.op_string
+= strlen (new_token
.str
);
5804 cur_token
= new_token
;
5807 /* Put cur_token back into the token stream and make cur_token point to
5810 intel_putback_token ()
5812 intel_parser
.op_string
-= strlen (cur_token
.str
);
5813 free (cur_token
.str
);
5814 cur_token
= prev_token
;
5816 /* Forget prev_token. */
5817 prev_token
.code
= T_NIL
;
5818 prev_token
.reg
= NULL
;
5819 prev_token
.str
= NULL
;