From 368910707c60c2008cf241959caec68968ea78ed Mon Sep 17 00:00:00 2001 From: Andrew Carlotti Date: Fri, 12 Jan 2024 01:44:10 +0000 Subject: [PATCH] aarch64: Add +rcpc2 flag for existing instructions --- gas/config/tc-aarch64.c | 1 + gas/testsuite/gas/aarch64/armv8_4-a.d | 2 +- gas/testsuite/gas/aarch64/{armv8_4-a.d => rcpc2.d} | 119 +---------------- gas/testsuite/gas/aarch64/rcpc2.s | 143 +++++++++++++++++++++ include/opcode/aarch64.h | 3 + opcodes/aarch64-tbl.h | 31 +++-- 6 files changed, 167 insertions(+), 132 deletions(-) copy gas/testsuite/gas/aarch64/{armv8_4-a.d => rcpc2.d} (95%) create mode 100644 gas/testsuite/gas/aarch64/rcpc2.s diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 63c649a2fad..df71e67a5a6 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -10286,6 +10286,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = { AARCH64_FEATURES (2, F16, SIMD)}, {"jscvt", AARCH64_FEATURE (JSCVT), AARCH64_FEATURE (FP)}, {"rcpc", AARCH64_FEATURE (RCPC), AARCH64_NO_FEATURES}, + {"rcpc2", AARCH64_FEATURE (RCPC2), AARCH64_FEATURE (RCPC)}, {"dotprod", AARCH64_FEATURE (DOTPROD), AARCH64_FEATURE (SIMD)}, {"sha2", AARCH64_FEATURE (SHA2), AARCH64_FEATURE (FP)}, {"frintts", AARCH64_FEATURE (FRINTTS), AARCH64_FEATURE (SIMD)}, diff --git a/gas/testsuite/gas/aarch64/armv8_4-a.d b/gas/testsuite/gas/aarch64/armv8_4-a.d index 4b1a4e37757..ae0a27f0b4b 100644 --- a/gas/testsuite/gas/aarch64/armv8_4-a.d +++ b/gas/testsuite/gas/aarch64/armv8_4-a.d @@ -2202,4 +2202,4 @@ Disassembly of section \.text: [^:]+:\s+998033fe ldapursw x30, \[sp, #3\] [^:]+:\s+998523fe ldapursw x30, \[sp, #82\] [^:]+:\s+9980d3fe ldapursw x30, \[sp, #13\] -[^:]+:\s+d500401f cfinv \ No newline at end of file +[^:]+:\s+d500401f cfinv diff --git a/gas/testsuite/gas/aarch64/armv8_4-a.d b/gas/testsuite/gas/aarch64/rcpc2.d similarity index 95% copy from gas/testsuite/gas/aarch64/armv8_4-a.d copy to gas/testsuite/gas/aarch64/rcpc2.d index 4b1a4e37757..3de4be7b347 100644 --- a/gas/testsuite/gas/aarch64/armv8_4-a.d +++ b/gas/testsuite/gas/aarch64/rcpc2.d @@ -1,4 +1,4 @@ -#as: -march=armv8.4-a +#as: -march=armv8-a+rcpc2 #objdump: -dr .*: file format .* @@ -6,122 +6,6 @@ Disassembly of section \.text: 0+ <.*>: -[^:]+:\s+ba000443 rmif x2, #0, #3 -[^:]+:\s+ba00044b rmif x2, #0, #11 -[^:]+:\s+ba00044f rmif x2, #0, #15 -[^:]+:\s+ba040443 rmif x2, #8, #3 -[^:]+:\s+ba04044b rmif x2, #8, #11 -[^:]+:\s+ba04044f rmif x2, #8, #15 -[^:]+:\s+ba060443 rmif x2, #12, #3 -[^:]+:\s+ba06044b rmif x2, #12, #11 -[^:]+:\s+ba06044f rmif x2, #12, #15 -[^:]+:\s+ba0005e3 rmif x15, #0, #3 -[^:]+:\s+ba0005eb rmif x15, #0, #11 -[^:]+:\s+ba0005ef rmif x15, #0, #15 -[^:]+:\s+ba0405e3 rmif x15, #8, #3 -[^:]+:\s+ba0405eb rmif x15, #8, #11 -[^:]+:\s+ba0405ef rmif x15, #8, #15 -[^:]+:\s+ba0605e3 rmif x15, #12, #3 -[^:]+:\s+ba0605eb rmif x15, #12, #11 -[^:]+:\s+ba0605ef rmif x15, #12, #15 -[^:]+:\s+ba0007c3 rmif x30, #0, #3 -[^:]+:\s+ba0007cb rmif x30, #0, #11 -[^:]+:\s+ba0007cf rmif x30, #0, #15 -[^:]+:\s+ba0407c3 rmif x30, #8, #3 -[^:]+:\s+ba0407cb rmif x30, #8, #11 -[^:]+:\s+ba0407cf rmif x30, #8, #15 -[^:]+:\s+ba0607c3 rmif x30, #12, #3 -[^:]+:\s+ba0607cb rmif x30, #12, #11 -[^:]+:\s+ba0607cf rmif x30, #12, #15 -[^:]+:\s+ba000443 rmif x2, #0, #3 -[^:]+:\s+ba00044b rmif x2, #0, #11 -[^:]+:\s+ba00044f rmif x2, #0, #15 -[^:]+:\s+ba040443 rmif x2, #8, #3 -[^:]+:\s+ba04044b rmif x2, #8, #11 -[^:]+:\s+ba04044f rmif x2, #8, #15 -[^:]+:\s+ba060443 rmif x2, #12, #3 -[^:]+:\s+ba06044b rmif x2, #12, #11 -[^:]+:\s+ba06044f rmif x2, #12, #15 -[^:]+:\s+ba0005e3 rmif x15, #0, #3 -[^:]+:\s+ba0005eb rmif x15, #0, #11 -[^:]+:\s+ba0005ef rmif x15, #0, #15 -[^:]+:\s+ba0405e3 rmif x15, #8, #3 -[^:]+:\s+ba0405eb rmif x15, #8, #11 -[^:]+:\s+ba0405ef rmif x15, #8, #15 -[^:]+:\s+ba0605e3 rmif x15, #12, #3 -[^:]+:\s+ba0605eb rmif x15, #12, #11 -[^:]+:\s+ba0605ef rmif x15, #12, #15 -[^:]+:\s+ba0007c3 rmif x30, #0, #3 -[^:]+:\s+ba0007cb rmif x30, #0, #11 -[^:]+:\s+ba0007cf rmif x30, #0, #15 -[^:]+:\s+ba0407c3 rmif x30, #8, #3 -[^:]+:\s+ba0407cb rmif x30, #8, #11 -[^:]+:\s+ba0407cf rmif x30, #8, #15 -[^:]+:\s+ba0607c3 rmif x30, #12, #3 -[^:]+:\s+ba0607cb rmif x30, #12, #11 -[^:]+:\s+ba0607cf rmif x30, #12, #15 -[^:]+:\s+ba000443 rmif x2, #0, #3 -[^:]+:\s+ba00044b rmif x2, #0, #11 -[^:]+:\s+ba00044f rmif x2, #0, #15 -[^:]+:\s+ba040443 rmif x2, #8, #3 -[^:]+:\s+ba04044b rmif x2, #8, #11 -[^:]+:\s+ba04044f rmif x2, #8, #15 -[^:]+:\s+ba060443 rmif x2, #12, #3 -[^:]+:\s+ba06044b rmif x2, #12, #11 -[^:]+:\s+ba06044f rmif x2, #12, #15 -[^:]+:\s+ba0005e3 rmif x15, #0, #3 -[^:]+:\s+ba0005eb rmif x15, #0, #11 -[^:]+:\s+ba0005ef rmif x15, #0, #15 -[^:]+:\s+ba0405e3 rmif x15, #8, #3 -[^:]+:\s+ba0405eb rmif x15, #8, #11 -[^:]+:\s+ba0405ef rmif x15, #8, #15 -[^:]+:\s+ba0605e3 rmif x15, #12, #3 -[^:]+:\s+ba0605eb rmif x15, #12, #11 -[^:]+:\s+ba0605ef rmif x15, #12, #15 -[^:]+:\s+ba0007c3 rmif x30, #0, #3 -[^:]+:\s+ba0007cb rmif x30, #0, #11 -[^:]+:\s+ba0007cf rmif x30, #0, #15 -[^:]+:\s+ba0407c3 rmif x30, #8, #3 -[^:]+:\s+ba0407cb rmif x30, #8, #11 -[^:]+:\s+ba0407cf rmif x30, #8, #15 -[^:]+:\s+ba0607c3 rmif x30, #12, #3 -[^:]+:\s+ba0607cb rmif x30, #12, #11 -[^:]+:\s+ba0607cf rmif x30, #12, #15 -[^:]+:\s+ba000443 rmif x2, #0, #3 -[^:]+:\s+ba00044b rmif x2, #0, #11 -[^:]+:\s+ba00044f rmif x2, #0, #15 -[^:]+:\s+ba040443 rmif x2, #8, #3 -[^:]+:\s+ba04044b rmif x2, #8, #11 -[^:]+:\s+ba04044f rmif x2, #8, #15 -[^:]+:\s+ba060443 rmif x2, #12, #3 -[^:]+:\s+ba06044b rmif x2, #12, #11 -[^:]+:\s+ba06044f rmif x2, #12, #15 -[^:]+:\s+ba0005e3 rmif x15, #0, #3 -[^:]+:\s+ba0005eb rmif x15, #0, #11 -[^:]+:\s+ba0005ef rmif x15, #0, #15 -[^:]+:\s+ba0405e3 rmif x15, #8, #3 -[^:]+:\s+ba0405eb rmif x15, #8, #11 -[^:]+:\s+ba0405ef rmif x15, #8, #15 -[^:]+:\s+ba0605e3 rmif x15, #12, #3 -[^:]+:\s+ba0605eb rmif x15, #12, #11 -[^:]+:\s+ba0605ef rmif x15, #12, #15 -[^:]+:\s+ba0007c3 rmif x30, #0, #3 -[^:]+:\s+ba0007cb rmif x30, #0, #11 -[^:]+:\s+ba0007cf rmif x30, #0, #15 -[^:]+:\s+ba0407c3 rmif x30, #8, #3 -[^:]+:\s+ba0407cb rmif x30, #8, #11 -[^:]+:\s+ba0407cf rmif x30, #8, #15 -[^:]+:\s+ba0607c3 rmif x30, #12, #3 -[^:]+:\s+ba0607cb rmif x30, #12, #11 -[^:]+:\s+ba0607cf rmif x30, #12, #15 -[^:]+:\s+3a00080d setf8 w0 -[^:]+:\s+3a0008ed setf8 w7 -[^:]+:\s+3a000a0d setf8 w16 -[^:]+:\s+3a000bcd setf8 w30 -[^:]+:\s+3a00480d setf16 w0 -[^:]+:\s+3a0048ed setf16 w7 -[^:]+:\s+3a004a0d setf16 w16 -[^:]+:\s+3a004bcd setf16 w30 [^:]+:\s+19000060 stlurb w0, \[x3\] [^:]+:\s+19000160 stlurb w0, \[x11\] [^:]+:\s+190001e0 stlurb w0, \[x15\] @@ -2202,4 +2086,3 @@ Disassembly of section \.text: [^:]+:\s+998033fe ldapursw x30, \[sp, #3\] [^:]+:\s+998523fe ldapursw x30, \[sp, #82\] [^:]+:\s+9980d3fe ldapursw x30, \[sp, #13\] -[^:]+:\s+d500401f cfinv \ No newline at end of file diff --git a/gas/testsuite/gas/aarch64/rcpc2.s b/gas/testsuite/gas/aarch64/rcpc2.s new file mode 100644 index 00000000000..8496dbe1987 --- /dev/null +++ b/gas/testsuite/gas/aarch64/rcpc2.s @@ -0,0 +1,143 @@ + # Print a 4 operand instruction + .macro print_gen4reg op, d, pd1=, pd2=, n, pn1=, pn2=, m, pm1=, pm2=, w , pw1=, pw2= + .ifnb \d + \op \pd1\d\()\pd2, \pn1\n\()\pn2, \pm1\m\()\pm2, \pw1\w\()\pw2 + .else + .ifnb \n + \op \pn1\n\()\pn2, \pm1\m\()\pm2, \pw1\w\()\pw2 + .else + \op \pm1\m\()\pm2, \pw1\w\()\pw2 + .endif + .endif + .endm + + .macro gen4reg_iter_d_offset op, d, pd1=, pd2=, r + .irp m, 03, 82, 13 + \op \pd1\d\()\pd2, [\r, \m] + .endr + .endm + + .macro gen4reg_iter_d_n_w op, d, pd1=, pd2=, n, pn1=, pn2=, m, pm1=, pm2=, pw1=, pw2= + .irp w, 3, 11, 15 + print_gen4reg \op, \d, \pd1, \pd2, \n, \pn1, \pn2, \m, \pm1, \pm2, \w, \pw1, \pw2 + .endr + .endm + + .macro gen4reg_iter_d_n op, d, pd1=, pd2=, n, pn1=, pn2=, pm1=, pm2=, pw1=, pw2= + .irp m, 0, 8, 12 + gen4reg_iter_d_n_w \op, \d, \pd1, \pd2, \n, \pn1, \pn2, \m, \pm1, \pm2, \pw1, \pw2 + .endr + .endm + + .macro gen4reg_iter_d op, d, pd1=, pd2=, pn1=, pn2=, pm1=, pm2=, pw1=, pw2= + .irp n, 2, 15, 30 + gen4reg_iter_d_n \op, \d, \pd1, \pd2, \n, \pn1, \pn2, \pm1, \pm2, \pw1, \pw2 + .endr + .endm + + .macro gen4reg_iter op, pd1=, pd2=, pn1=, pn2=, pm1=, pm2=, pw1=, pw2= + .irp d, 0, 7, 16, 30 + gen4reg_iter_d \op, \d, \pd1, \pd2, \pn1, \pn2, \pm1, \pm2, \pw1, \pw2 + .endr + .endm + + # Print a 3 operand instruction + .macro gen3reg_iter op, pd1=, pd2=, pn1=, pn2=, pm1=, pm2= + .irp d, 0, 7, 16, 30 + gen4reg_iter_d \op,,, \d, \pd1, \pd2, \pn1, \pn2, \pm1, \pm2 + .endr + .endm + + .macro gen3reg_iter_lane op, pn1=, pn2=, pm1=, pm2=, pw1=, pw2=, x:vararg + .irp l, \x + gen4reg_iter_d \op,,,, \pn1, \pn2, \pm1, \pm2, \pw1, \pw2[\l] + .endr + .endm + + # Print a 2 operand instruction + .macro gen2reg_iter op, pd1=, pd2=, pn1=, pn2= + .irp d, 0, 7, 16, 30 + gen4reg_iter_d_n \op,,,,,, \d, \pd1, \pd2, \pn1, \pn2 + .endr + .endm + + .macro gen2reg_iter_offset op, pd1=, pd2=, r + .irp d, 0, 7, 16, 30 + gen4reg_iter_d_offset \op, \d, \pd1, \pd2, \r, + .endr + .endm + + # Print a 1 operand instruction + .macro gen1reg_iter op, pd1=, pd2= + .irp d, 0, 7, 16, 30 + \op \pd1\d\()\pd2 + .endr + .endm + + .text +func: + gen2reg_iter stlurb w,,[x,] + gen1reg_iter stlurb w,", [sp]" + gen3reg_iter stlurb w,, [x,,,] + gen2reg_iter_offset stlurb w,,sp + + gen2reg_iter ldapurb w,,[x,] + gen1reg_iter ldapurb w,", [sp]" + gen3reg_iter ldapurb w,, [x,,,] + gen2reg_iter_offset ldapurb w,,sp + + gen2reg_iter ldapursb w,,[x,] + gen1reg_iter ldapursb w,", [sp]" + gen3reg_iter ldapursb w,, [x,,,] + gen2reg_iter_offset ldapursb w,,sp + + gen2reg_iter ldapursb x,,[x,] + gen1reg_iter ldapursb x,", [sp]" + gen3reg_iter ldapursb x,, [x,,,] + gen2reg_iter_offset ldapursb x,,sp + + gen2reg_iter stlurh w,,[x,] + gen1reg_iter stlurh w,", [sp]" + gen3reg_iter stlurh w,, [x,,,] + gen2reg_iter_offset stlurh w,,sp + + gen2reg_iter ldapurh w,,[x,] + gen1reg_iter ldapurh w,", [sp]" + gen3reg_iter ldapurh w,, [x,,,] + gen2reg_iter_offset ldapurh w,,sp + + gen2reg_iter ldapursh w,,[x,] + gen1reg_iter ldapursh w,", [sp]" + gen3reg_iter ldapursh w,, [x,,,] + gen2reg_iter_offset ldapursh w,,sp + + gen2reg_iter ldapursh x,,[x,] + gen1reg_iter ldapursh x,", [sp]" + gen3reg_iter ldapursh x,, [x,,,] + gen2reg_iter_offset ldapursh x,,sp + + gen2reg_iter stlur w,,[x,] + gen1reg_iter stlur w,", [sp]" + gen3reg_iter stlur w,, [x,,,] + gen2reg_iter_offset stlur w,,sp + + gen2reg_iter stlur x,,[x,] + gen1reg_iter stlur x,", [sp]" + gen3reg_iter stlur x,, [x,,,] + gen2reg_iter_offset stlur x,,sp + + gen2reg_iter ldapur w,,[x,] + gen1reg_iter ldapur w,", [sp]" + gen3reg_iter ldapur w,, [x,,,] + gen2reg_iter_offset ldapur w,,sp + + gen2reg_iter ldapur x,,[x,] + gen1reg_iter ldapur x,", [sp]" + gen3reg_iter ldapur x,, [x,,,] + gen2reg_iter_offset ldapur x,,sp + + gen2reg_iter ldapursw x,,[x,] + gen1reg_iter ldapursw x,", [sp]" + gen3reg_iter ldapursw x,, [x,,,] + gen2reg_iter_offset ldapursw x,,sp + diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index eb42b87a002..6674f34ab29 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -97,6 +97,8 @@ enum aarch64_feature_bit { AARCH64_FEATURE_SVE, /* RCPC instructions. */ AARCH64_FEATURE_RCPC, + /* RCPC2 instructions. */ + AARCH64_FEATURE_RCPC2, /* Complex # instructions. */ AARCH64_FEATURE_COMPNUM, /* JavaScript conversion instructions. */ @@ -251,6 +253,7 @@ enum aarch64_feature_bit { | AARCH64_FEATBIT (X, COMPNUM) \ | AARCH64_FEATBIT (X, JSCVT)) #define AARCH64_ARCH_V8_4A_FEATURES(X) (AARCH64_FEATBIT (X, V8_4A) \ + | AARCH64_FEATBIT (X, RCPC2) \ | AARCH64_FEATBIT (X, DOTPROD) \ | AARCH64_FEATBIT (X, FLAGM) \ | AARCH64_FEATBIT (X, F16_FML)) diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 007bf018af8..1838f99a960 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -2522,6 +2522,8 @@ static const aarch64_feature_set aarch64_feature_jscvt = AARCH64_FEATURE (JSCVT); static const aarch64_feature_set aarch64_feature_rcpc = AARCH64_FEATURE (RCPC); +static const aarch64_feature_set aarch64_feature_rcpc2 = + AARCH64_FEATURE (RCPC2); static const aarch64_feature_set aarch64_feature_dotprod = AARCH64_FEATURE (DOTPROD); static const aarch64_feature_set aarch64_feature_sha2 = @@ -2635,6 +2637,7 @@ static const aarch64_feature_set aarch64_feature_d128_the = #define COMPNUM &aarch64_feature_compnum #define JSCVT &aarch64_feature_jscvt #define RCPC &aarch64_feature_rcpc +#define RCPC2 &aarch64_feature_rcpc2 #define SHA2 &aarch64_feature_sha2 #define AES &aarch64_feature_aes #define ARMV8_4A &aarch64_feature_v8_4a @@ -2724,6 +2727,8 @@ static const aarch64_feature_set aarch64_feature_d128_the = { NAME, OPCODE, MASK, CLASS, 0, JSCVT, OPS, QUALS, FLAGS, 0, 0, NULL } #define RCPC_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, RCPC, OPS, QUALS, FLAGS, 0, 0, NULL } +#define RCPC2_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ + { NAME, OPCODE, MASK, CLASS, 0, RCPC2, OPS, QUALS, FLAGS, 0, 0, NULL } #define SHA2_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, SHA2, OPS, QUALS, FLAGS, 0, 0, NULL } #define AES_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ @@ -6040,19 +6045,19 @@ const struct aarch64_opcode aarch64_opcode_table[] = FLAGM_INSN ("setf8", 0x3a00080d, 0xfffffc1f, ic_system, OP1 (Rn), QL_SETF, 0), FLAGM_INSN ("setf16", 0x3a00480d, 0xfffffc1f, ic_system, OP1 (Rn), QL_SETF, 0), /* Memory access instructions ARMv8.4-a. */ - V8_4A_INSN ("stlurb" , 0x19000000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0), - V8_4A_INSN ("ldapurb", 0x19400000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0), - V8_4A_INSN ("ldapursb", 0x19c00000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0), - V8_4A_INSN ("ldapursb", 0x19800000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLX, 0), - V8_4A_INSN ("stlurh", 0x59000000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0), - V8_4A_INSN ("ldapurh", 0x59400000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0), - V8_4A_INSN ("ldapursh", 0x59c00000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0), - V8_4A_INSN ("ldapursh", 0x59800000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLX, 0), - V8_4A_INSN ("stlur", 0x99000000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0), - V8_4A_INSN ("ldapur", 0x99400000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0), - V8_4A_INSN ("ldapursw", 0x99800000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLX, 0), - V8_4A_INSN ("stlur", 0xd9000000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLX, 0), - V8_4A_INSN ("ldapur", 0xd9400000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLX, 0), + RCPC2_INSN ("stlurb" , 0x19000000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0), + RCPC2_INSN ("ldapurb", 0x19400000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0), + RCPC2_INSN ("ldapursb", 0x19c00000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0), + RCPC2_INSN ("ldapursb", 0x19800000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLX, 0), + RCPC2_INSN ("stlurh", 0x59000000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0), + RCPC2_INSN ("ldapurh", 0x59400000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0), + RCPC2_INSN ("ldapursh", 0x59c00000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0), + RCPC2_INSN ("ldapursh", 0x59800000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLX, 0), + RCPC2_INSN ("stlur", 0x99000000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0), + RCPC2_INSN ("ldapur", 0x99400000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0), + RCPC2_INSN ("ldapursw", 0x99800000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLX, 0), + RCPC2_INSN ("stlur", 0xd9000000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLX, 0), + RCPC2_INSN ("ldapur", 0xd9400000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLX, 0), /* Matrix Multiply instructions. */ INT8MATMUL_SVE_INSNC ("smmla", 0x45009800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SBB, 0, C_SCAN_MOVPRFX, 0), -- 2.11.4.GIT