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[gdb/testsuite] Don't use string cat in gdb.dwarf2/dw2-abs-hi-pc.exp
[binutils-gdb.git] / sim / v850 / simops.c
blob326745efcb268d647cc583948ad239be8fb72f56
1 /* This must come before any other includes. */
2 #include "defs.h"
3
4 #include "sim-main.h"
5 #include "sim-signal.h"
6 #include "v850-sim.h"
7 #include "simops.h"
8
9 #include <sys/types.h>
10
11 #ifdef HAVE_UTIME_H
12 #include <utime.h>
13 #endif
14 #include <time.h>
15 #include <unistd.h>
16 #include <stdlib.h>
17 #include <string.h>
18
19 #include "libiberty.h"
20
21 #include <errno.h>
22 #if !defined(__GO32__) && !defined(_WIN32)
23 #include <sys/stat.h>
24 #include <sys/times.h>
25 #include <sys/time.h>
26 #endif
27
28 #include "target-newlib-syscall.h"
29
30 /* This is an array of the bit positions of registers r20 .. r31 in
31 that order in a prepare/dispose instruction. */
32 int type1_regs[12] = { 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 0, 21 };
33 /* This is an array of the bit positions of registers r16 .. r31 in
34 that order in a push/pop instruction. */
35 int type2_regs[16] = { 3, 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 20, 21};
36 /* This is an array of the bit positions of registers r1 .. r15 in
37 that order in a push/pop instruction. */
38 int type3_regs[15] = { 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 20, 21};
39
40 #if WITH_TRACE_ANY_P
41 #ifndef SIZE_INSTRUCTION
42 #define SIZE_INSTRUCTION 18
43 #endif
44
45 #ifndef SIZE_VALUES
46 #define SIZE_VALUES 11
47 #endif
48
49 /* TODO: This file largely assumes a single CPU. */
50 #define CPU STATE_CPU (sd, 0)
51
52
53 uint32_t trace_values[3];
54 int trace_num_values;
55 uint32_t trace_pc;
56 const char * trace_name;
57 int trace_module;
58
59
60 void
61 trace_input (char *name, enum op_types type, int size)
62 {
63 if (!TRACE_ALU_P (STATE_CPU (simulator, 0)))
64 return;
65
66 trace_pc = PC;
67 trace_name = name;
68 trace_module = TRACE_ALU_IDX;
69
70 switch (type)
71 {
72 default:
73 case OP_UNKNOWN:
74 case OP_NONE:
75 case OP_TRAP:
76 trace_num_values = 0;
77 break;
78
79 case OP_REG:
80 case OP_REG_REG_MOVE:
81 trace_values[0] = State.regs[OP[0]];
82 trace_num_values = 1;
83 break;
84
85 case OP_BIT_CHANGE:
86 case OP_REG_REG:
87 case OP_REG_REG_CMP:
88 trace_values[0] = State.regs[OP[1]];
89 trace_values[1] = State.regs[OP[0]];
90 trace_num_values = 2;
91 break;
92
93 case OP_IMM_REG:
94 case OP_IMM_REG_CMP:
95 trace_values[0] = SEXT5 (OP[0]);
96 trace_values[1] = OP[1];
97 trace_num_values = 2;
98 break;
99
100 case OP_IMM_REG_MOVE:
101 trace_values[0] = SEXT5 (OP[0]);
102 trace_num_values = 1;
103 break;
104
105 case OP_COND_BR:
106 trace_values[0] = State.pc;
107 trace_values[1] = SEXT9 (OP[0]);
108 trace_values[2] = PSW;
109 trace_num_values = 3;
110 break;
111
112 case OP_LOAD16:
113 trace_values[0] = OP[1] * size;
114 trace_values[1] = State.regs[30];
115 trace_num_values = 2;
116 break;
117
118 case OP_STORE16:
119 trace_values[0] = State.regs[OP[0]];
120 trace_values[1] = OP[1] * size;
121 trace_values[2] = State.regs[30];
122 trace_num_values = 3;
123 break;
124
125 case OP_LOAD32:
126 trace_values[0] = EXTEND16 (OP[2]);
127 trace_values[1] = State.regs[OP[0]];
128 trace_num_values = 2;
129 break;
130
131 case OP_STORE32:
132 trace_values[0] = State.regs[OP[1]];
133 trace_values[1] = EXTEND16 (OP[2]);
134 trace_values[2] = State.regs[OP[0]];
135 trace_num_values = 3;
136 break;
137
138 case OP_JUMP:
139 trace_values[0] = SEXT22 (OP[0]);
140 trace_values[1] = State.pc;
141 trace_num_values = 2;
142 break;
143
144 case OP_IMM_REG_REG:
145 trace_values[0] = EXTEND16 (OP[0]) << size;
146 trace_values[1] = State.regs[OP[1]];
147 trace_num_values = 2;
148 break;
149
150 case OP_IMM16_REG_REG:
151 trace_values[0] = EXTEND16 (OP[2]) << size;
152 trace_values[1] = State.regs[OP[1]];
153 trace_num_values = 2;
154 break;
155
156 case OP_UIMM_REG_REG:
157 trace_values[0] = (OP[0] & 0xffff) << size;
158 trace_values[1] = State.regs[OP[1]];
159 trace_num_values = 2;
160 break;
161
162 case OP_UIMM16_REG_REG:
163 trace_values[0] = (OP[2]) << size;
164 trace_values[1] = State.regs[OP[1]];
165 trace_num_values = 2;
166 break;
167
168 case OP_BIT:
169 trace_num_values = 0;
170 break;
171
172 case OP_EX1:
173 trace_values[0] = PSW;
174 trace_num_values = 1;
175 break;
176
177 case OP_EX2:
178 trace_num_values = 0;
179 break;
180
181 case OP_LDSR:
182 trace_values[0] = State.regs[OP[0]];
183 trace_num_values = 1;
184 break;
185
186 case OP_STSR:
187 trace_values[0] = State.sregs[OP[1]];
188 trace_num_values = 1;
189 }
190
191 }
192
193 void
194 trace_result (int has_result, uint32_t result)
195 {
196 char buf[1000];
197 char *chp;
198
199 buf[0] = '\0';
200 chp = buf;
201
202 /* write out the values saved during the trace_input call */
203 {
204 int i;
205 for (i = 0; i < trace_num_values; i++)
206 {
207 sprintf (chp, "%*s0x%.8lx", SIZE_VALUES - 10, "",
208 (long) trace_values[i]);
209 chp = strchr (chp, '\0');
210 }
211 while (i++ < 3)
212 {
213 sprintf (chp, "%*s", SIZE_VALUES, "");
214 chp = strchr (chp, '\0');
215 }
216 }
217
218 /* append any result to the end of the buffer */
219 if (has_result)
220 sprintf (chp, " :: 0x%.8lx", (unsigned long) result);
221
222 trace_generic (simulator, STATE_CPU (simulator, 0), trace_module, "%s", buf);
223 }
224
225 void
226 trace_output (enum op_types result)
227 {
228 if (!TRACE_ALU_P (STATE_CPU (simulator, 0)))
229 return;
230
231 switch (result)
232 {
233 default:
234 case OP_UNKNOWN:
235 case OP_NONE:
236 case OP_TRAP:
237 case OP_REG:
238 case OP_REG_REG_CMP:
239 case OP_IMM_REG_CMP:
240 case OP_COND_BR:
241 case OP_STORE16:
242 case OP_STORE32:
243 case OP_BIT:
244 case OP_EX2:
245 trace_result (0, 0);
246 break;
247
248 case OP_LOAD16:
249 case OP_STSR:
250 trace_result (1, State.regs[OP[0]]);
251 break;
252
253 case OP_REG_REG:
254 case OP_REG_REG_MOVE:
255 case OP_IMM_REG:
256 case OP_IMM_REG_MOVE:
257 case OP_LOAD32:
258 case OP_EX1:
259 trace_result (1, State.regs[OP[1]]);
260 break;
261
262 case OP_IMM_REG_REG:
263 case OP_UIMM_REG_REG:
264 case OP_IMM16_REG_REG:
265 case OP_UIMM16_REG_REG:
266 trace_result (1, State.regs[OP[1]]);
267 break;
268
269 case OP_JUMP:
270 if (OP[1] != 0)
271 trace_result (1, State.regs[OP[1]]);
272 else
273 trace_result (0, 0);
274 break;
275
276 case OP_LDSR:
277 trace_result (1, State.sregs[OP[1]]);
278 break;
279 }
280 }
281 #endif
282
283 \f
284 /* Returns 1 if the specific condition is met, returns 0 otherwise. */
285 int
286 condition_met (unsigned code)
287 {
288 unsigned int psw = PSW;
289
290 switch (code & 0xf)
291 {
292 case 0x0: return ((psw & PSW_OV) != 0);
293 case 0x1: return ((psw & PSW_CY) != 0);
294 case 0x2: return ((psw & PSW_Z) != 0);
295 case 0x3: return ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) != 0);
296 case 0x4: return ((psw & PSW_S) != 0);
297 /*case 0x5: return 1;*/
298 case 0x6: return ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) != 0);
299 case 0x7: return (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) || ((psw & PSW_Z) != 0)) != 0);
300 case 0x8: return ((psw & PSW_OV) == 0);
301 case 0x9: return ((psw & PSW_CY) == 0);
302 case 0xa: return ((psw & PSW_Z) == 0);
303 case 0xb: return ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) == 0);
304 case 0xc: return ((psw & PSW_S) == 0);
305 case 0xd: return ((psw & PSW_SAT) != 0);
306 case 0xe: return ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) == 0);
307 case 0xf: return (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) || ((psw & PSW_Z) != 0)) == 0);
308 }
309
310 return 1;
311 }
312
313 unsigned long
314 Add32 (unsigned long a1, unsigned long a2, int * carry)
315 {
316 unsigned long result = (a1 + a2);
317
318 * carry = (result < a1);
319
320 return result;
321 }
322
323 static void
324 Multiply64 (int sign, unsigned long op0)
325 {
326 unsigned long op1;
327 unsigned long lo;
328 unsigned long mid1;
329 unsigned long mid2;
330 unsigned long hi;
331 unsigned long RdLo;
332 unsigned long RdHi;
333 int carry;
334
335 op1 = State.regs[ OP[1] ];
336
337 if (sign)
338 {
339 /* Compute sign of result and adjust operands if necessary. */
340
341 sign = (op0 ^ op1) & 0x80000000;
342
343 if (op0 & 0x80000000)
344 op0 = - op0;
345
346 if (op1 & 0x80000000)
347 op1 = - op1;
348 }
349
350 /* We can split the 32x32 into four 16x16 operations. This ensures
351 that we do not lose precision on 32bit only hosts: */
352 lo = ( (op0 & 0xFFFF) * (op1 & 0xFFFF));
353 mid1 = ( (op0 & 0xFFFF) * ((op1 >> 16) & 0xFFFF));
354 mid2 = (((op0 >> 16) & 0xFFFF) * (op1 & 0xFFFF));
355 hi = (((op0 >> 16) & 0xFFFF) * ((op1 >> 16) & 0xFFFF));
356
357 /* We now need to add all of these results together, taking care
358 to propogate the carries from the additions: */
359 RdLo = Add32 (lo, (mid1 << 16), & carry);
360 RdHi = carry;
361 RdLo = Add32 (RdLo, (mid2 << 16), & carry);
362 RdHi += (carry + ((mid1 >> 16) & 0xFFFF) + ((mid2 >> 16) & 0xFFFF) + hi);
363
364 if (sign)
365 {
366 /* Negate result if necessary. */
367
368 RdLo = ~ RdLo;
369 RdHi = ~ RdHi;
370 if (RdLo == 0xFFFFFFFF)
371 {
372 RdLo = 0;
373 RdHi += 1;
374 }
375 else
376 RdLo += 1;
377 }
378
379 /* Don't store into register 0. */
380 if (OP[1])
381 State.regs[ OP[1] ] = RdLo;
382 if (OP[2] >> 11)
383 State.regs[ OP[2] >> 11 ] = RdHi;
384
385 return;
386 }
387
388 \f
389 /* Read a null terminated string from memory, return in a buffer. */
390
391 static char *
392 fetch_str (SIM_DESC sd, address_word addr)
393 {
394 char *buf;
395 int nr = 0;
396
397 while (sim_core_read_1 (STATE_CPU (sd, 0),
398 PC, read_map, addr + nr) != 0)
399 nr++;
400
401 buf = NZALLOC (char, nr + 1);
402 sim_read (simulator, addr, buf, nr);
403
404 return buf;
405 }
406
407 /* Read a null terminated argument vector from memory, return in a
408 buffer. */
409
410 static char **
411 fetch_argv (SIM_DESC sd, address_word addr)
412 {
413 int max_nr = 64;
414 int nr = 0;
415 char **buf = xmalloc (max_nr * sizeof (char*));
416
417 while (1)
418 {
419 uint32_t a = sim_core_read_4 (STATE_CPU (sd, 0),
420 PC, read_map, addr + nr * 4);
421 if (a == 0) break;
422 buf[nr] = fetch_str (sd, a);
423 nr ++;
424 if (nr == max_nr - 1)
425 {
426 max_nr += 50;
427 buf = xrealloc (buf, max_nr * sizeof (char*));
428 }
429 }
430 buf[nr] = 0;
431 return buf;
432 }
433
434 \f
435 /* sst.b */
436 int
437 OP_380 (void)
438 {
439 trace_input ("sst.b", OP_STORE16, 1);
440
441 store_mem (State.regs[30] + (OP[3] & 0x7f), 1, State.regs[ OP[1] ]);
442
443 trace_output (OP_STORE16);
444
445 return 2;
446 }
447
448 /* sst.h */
449 int
450 OP_480 (void)
451 {
452 trace_input ("sst.h", OP_STORE16, 2);
453
454 store_mem (State.regs[30] + ((OP[3] & 0x7f) << 1), 2, State.regs[ OP[1] ]);
455
456 trace_output (OP_STORE16);
457
458 return 2;
459 }
460
461 /* sst.w */
462 int
463 OP_501 (void)
464 {
465 trace_input ("sst.w", OP_STORE16, 4);
466
467 store_mem (State.regs[30] + ((OP[3] & 0x7e) << 1), 4, State.regs[ OP[1] ]);
468
469 trace_output (OP_STORE16);
470
471 return 2;
472 }
473
474 /* ld.b */
475 int
476 OP_700 (void)
477 {
478 int adr;
479
480 trace_input ("ld.b", OP_LOAD32, 1);
481
482 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2]);
483
484 State.regs[ OP[1] ] = EXTEND8 (load_mem (adr, 1));
485
486 trace_output (OP_LOAD32);
487
488 return 4;
489 }
490
491 /* ld.h */
492 int
493 OP_720 (void)
494 {
495 int adr;
496
497 trace_input ("ld.h", OP_LOAD32, 2);
498
499 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2]);
500 adr &= ~0x1;
501
502 State.regs[ OP[1] ] = EXTEND16 (load_mem (adr, 2));
503
504 trace_output (OP_LOAD32);
505
506 return 4;
507 }
508
509 /* ld.w */
510 int
511 OP_10720 (void)
512 {
513 int adr;
514
515 trace_input ("ld.w", OP_LOAD32, 4);
516
517 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2] & ~1);
518 adr &= ~0x3;
519
520 State.regs[ OP[1] ] = load_mem (adr, 4);
521
522 trace_output (OP_LOAD32);
523
524 return 4;
525 }
526
527 /* st.b */
528 int
529 OP_740 (void)
530 {
531 trace_input ("st.b", OP_STORE32, 1);
532
533 store_mem (State.regs[ OP[0] ] + EXTEND16 (OP[2]), 1, State.regs[ OP[1] ]);
534
535 trace_output (OP_STORE32);
536
537 return 4;
538 }
539
540 /* st.h */
541 int
542 OP_760 (void)
543 {
544 int adr;
545
546 trace_input ("st.h", OP_STORE32, 2);
547
548 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2]);
549 adr &= ~1;
550
551 store_mem (adr, 2, State.regs[ OP[1] ]);
552
553 trace_output (OP_STORE32);
554
555 return 4;
556 }
557
558 /* st.w */
559 int
560 OP_10760 (void)
561 {
562 int adr;
563
564 trace_input ("st.w", OP_STORE32, 4);
565
566 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2] & ~1);
567 adr &= ~3;
568
569 store_mem (adr, 4, State.regs[ OP[1] ]);
570
571 trace_output (OP_STORE32);
572
573 return 4;
574 }
575
576 /* add reg, reg */
577 int
578 OP_1C0 (void)
579 {
580 unsigned int op0, op1, result, z, s, cy, ov;
581
582 trace_input ("add", OP_REG_REG, 0);
583
584 /* Compute the result. */
585
586 op0 = State.regs[ OP[0] ];
587 op1 = State.regs[ OP[1] ];
588
589 result = op0 + op1;
590
591 /* Compute the condition codes. */
592 z = (result == 0);
593 s = (result & 0x80000000);
594 cy = (result < op0 || result < op1);
595 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
596 && (op0 & 0x80000000) != (result & 0x80000000));
597
598 /* Store the result and condition codes. */
599 State.regs[OP[1]] = result;
600 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
601 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
602 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
603 trace_output (OP_REG_REG);
604
605 return 2;
606 }
607
608 /* add sign_extend(imm5), reg */
609 int
610 OP_240 (void)
611 {
612 unsigned int op0, op1, result, z, s, cy, ov;
613 int temp;
614
615 trace_input ("add", OP_IMM_REG, 0);
616
617 /* Compute the result. */
618 temp = SEXT5 (OP[0]);
619 op0 = temp;
620 op1 = State.regs[OP[1]];
621 result = op0 + op1;
622
623 /* Compute the condition codes. */
624 z = (result == 0);
625 s = (result & 0x80000000);
626 cy = (result < op0 || result < op1);
627 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
628 && (op0 & 0x80000000) != (result & 0x80000000));
629
630 /* Store the result and condition codes. */
631 State.regs[OP[1]] = result;
632 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
633 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
634 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
635 trace_output (OP_IMM_REG);
636
637 return 2;
638 }
639
640 /* addi sign_extend(imm16), reg, reg */
641 int
642 OP_600 (void)
643 {
644 unsigned int op0, op1, result, z, s, cy, ov;
645
646 trace_input ("addi", OP_IMM16_REG_REG, 0);
647
648 /* Compute the result. */
649
650 op0 = EXTEND16 (OP[2]);
651 op1 = State.regs[ OP[0] ];
652 result = op0 + op1;
653
654 /* Compute the condition codes. */
655 z = (result == 0);
656 s = (result & 0x80000000);
657 cy = (result < op0 || result < op1);
658 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
659 && (op0 & 0x80000000) != (result & 0x80000000));
660
661 /* Store the result and condition codes. */
662 State.regs[OP[1]] = result;
663 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
664 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
665 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
666 trace_output (OP_IMM16_REG_REG);
667
668 return 4;
669 }
670
671 /* sub reg1, reg2 */
672 int
673 OP_1A0 (void)
674 {
675 unsigned int op0, op1, result, z, s, cy, ov;
676
677 trace_input ("sub", OP_REG_REG, 0);
678 /* Compute the result. */
679 op0 = State.regs[ OP[0] ];
680 op1 = State.regs[ OP[1] ];
681 result = op1 - op0;
682
683 /* Compute the condition codes. */
684 z = (result == 0);
685 s = (result & 0x80000000);
686 cy = (op1 < op0);
687 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
688 && (op1 & 0x80000000) != (result & 0x80000000));
689
690 /* Store the result and condition codes. */
691 State.regs[OP[1]] = result;
692 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
693 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
694 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
695 trace_output (OP_REG_REG);
696
697 return 2;
698 }
699
700 /* subr reg1, reg2 */
701 int
702 OP_180 (void)
703 {
704 unsigned int op0, op1, result, z, s, cy, ov;
705
706 trace_input ("subr", OP_REG_REG, 0);
707 /* Compute the result. */
708 op0 = State.regs[ OP[0] ];
709 op1 = State.regs[ OP[1] ];
710 result = op0 - op1;
711
712 /* Compute the condition codes. */
713 z = (result == 0);
714 s = (result & 0x80000000);
715 cy = (op0 < op1);
716 ov = ((op0 & 0x80000000) != (op1 & 0x80000000)
717 && (op0 & 0x80000000) != (result & 0x80000000));
718
719 /* Store the result and condition codes. */
720 State.regs[OP[1]] = result;
721 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
722 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
723 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
724 trace_output (OP_REG_REG);
725
726 return 2;
727 }
728
729 /* sxh reg1 */
730 int
731 OP_E0 (void)
732 {
733 trace_input ("mulh", OP_REG_REG, 0);
734
735 State.regs[ OP[1] ] = (EXTEND16 (State.regs[ OP[1] ]) * EXTEND16 (State.regs[ OP[0] ]));
736
737 trace_output (OP_REG_REG);
738
739 return 2;
740 }
741
742 /* mulh sign_extend(imm5), reg2 */
743 int
744 OP_2E0 (void)
745 {
746 trace_input ("mulh", OP_IMM_REG, 0);
747
748 State.regs[ OP[1] ] = EXTEND16 (State.regs[ OP[1] ]) * SEXT5 (OP[0]);
749
750 trace_output (OP_IMM_REG);
751
752 return 2;
753 }
754
755 /* mulhi imm16, reg1, reg2 */
756 int
757 OP_6E0 (void)
758 {
759 trace_input ("mulhi", OP_IMM16_REG_REG, 0);
760
761 State.regs[ OP[1] ] = EXTEND16 (State.regs[ OP[0] ]) * EXTEND16 (OP[2]);
762
763 trace_output (OP_IMM16_REG_REG);
764
765 return 4;
766 }
767
768 /* cmp reg, reg */
769 int
770 OP_1E0 (void)
771 {
772 unsigned int op0, op1, result, z, s, cy, ov;
773
774 trace_input ("cmp", OP_REG_REG_CMP, 0);
775 /* Compute the result. */
776 op0 = State.regs[ OP[0] ];
777 op1 = State.regs[ OP[1] ];
778 result = op1 - op0;
779
780 /* Compute the condition codes. */
781 z = (result == 0);
782 s = (result & 0x80000000);
783 cy = (op1 < op0);
784 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
785 && (op1 & 0x80000000) != (result & 0x80000000));
786
787 /* Set condition codes. */
788 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
789 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
790 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
791 trace_output (OP_REG_REG_CMP);
792
793 return 2;
794 }
795
796 /* cmp sign_extend(imm5), reg */
797 int
798 OP_260 (void)
799 {
800 unsigned int op0, op1, result, z, s, cy, ov;
801 int temp;
802
803 /* Compute the result. */
804 trace_input ("cmp", OP_IMM_REG_CMP, 0);
805 temp = SEXT5 (OP[0]);
806 op0 = temp;
807 op1 = State.regs[OP[1]];
808 result = op1 - op0;
809
810 /* Compute the condition codes. */
811 z = (result == 0);
812 s = (result & 0x80000000);
813 cy = (op1 < op0);
814 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
815 && (op1 & 0x80000000) != (result & 0x80000000));
816
817 /* Set condition codes. */
818 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
819 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
820 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
821 trace_output (OP_IMM_REG_CMP);
822
823 return 2;
824 }
825
826 /* setf cccc,reg2 */
827 int
828 OP_7E0 (void)
829 {
830 trace_input ("setf", OP_EX1, 0);
831
832 State.regs[ OP[1] ] = condition_met (OP[0]);
833
834 trace_output (OP_EX1);
835
836 return 4;
837 }
838
839 /* satadd reg,reg */
840 int
841 OP_C0 (void)
842 {
843 unsigned int op0, op1, result, z, s, cy, ov, sat;
844
845 trace_input ("satadd", OP_REG_REG, 0);
846 /* Compute the result. */
847 op0 = State.regs[ OP[0] ];
848 op1 = State.regs[ OP[1] ];
849 result = op0 + op1;
850
851 /* Compute the condition codes. */
852 z = (result == 0);
853 s = (result & 0x80000000);
854 cy = (result < op0 || result < op1);
855 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
856 && (op0 & 0x80000000) != (result & 0x80000000));
857 sat = ov;
858
859 /* Handle saturated results. */
860 if (sat && s)
861 {
862 /* An overflow that results in a negative result implies that we
863 became too positive. */
864 result = 0x7fffffff;
865 s = 0;
866 }
867 else if (sat)
868 {
869 /* Any other overflow must have thus been too negative. */
870 result = 0x80000000;
871 s = 1;
872 z = 0;
873 }
874
875 /* Store the result and condition codes. */
876 State.regs[OP[1]] = result;
877 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
878 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
879 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
880 | (sat ? PSW_SAT : 0));
881
882 trace_output (OP_REG_REG);
883
884 return 2;
885 }
886
887 /* satadd sign_extend(imm5), reg */
888 int
889 OP_220 (void)
890 {
891 unsigned int op0, op1, result, z, s, cy, ov, sat;
892
893 int temp;
894
895 trace_input ("satadd", OP_IMM_REG, 0);
896
897 /* Compute the result. */
898 temp = SEXT5 (OP[0]);
899 op0 = temp;
900 op1 = State.regs[OP[1]];
901 result = op0 + op1;
902
903 /* Compute the condition codes. */
904 z = (result == 0);
905 s = (result & 0x80000000);
906 cy = (result < op0 || result < op1);
907 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
908 && (op0 & 0x80000000) != (result & 0x80000000));
909 sat = ov;
910
911 /* Handle saturated results. */
912 if (sat && s)
913 {
914 /* An overflow that results in a negative result implies that we
915 became too positive. */
916 result = 0x7fffffff;
917 s = 0;
918 }
919 else if (sat)
920 {
921 /* Any other overflow must have thus been too negative. */
922 result = 0x80000000;
923 s = 1;
924 z = 0;
925 }
926
927 /* Store the result and condition codes. */
928 State.regs[OP[1]] = result;
929 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
930 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
931 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
932 | (sat ? PSW_SAT : 0));
933 trace_output (OP_IMM_REG);
934
935 return 2;
936 }
937
938 /* satsub reg1, reg2 */
939 int
940 OP_A0 (void)
941 {
942 unsigned int op0, op1, result, z, s, cy, ov, sat;
943
944 trace_input ("satsub", OP_REG_REG, 0);
945
946 /* Compute the result. */
947 op0 = State.regs[ OP[0] ];
948 op1 = State.regs[ OP[1] ];
949 result = op1 - op0;
950
951 /* Compute the condition codes. */
952 z = (result == 0);
953 s = (result & 0x80000000);
954 cy = (op1 < op0);
955 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
956 && (op1 & 0x80000000) != (result & 0x80000000));
957 sat = ov;
958
959 /* Handle saturated results. */
960 if (sat && s)
961 {
962 /* An overflow that results in a negative result implies that we
963 became too positive. */
964 result = 0x7fffffff;
965 s = 0;
966 }
967 else if (sat)
968 {
969 /* Any other overflow must have thus been too negative. */
970 result = 0x80000000;
971 s = 1;
972 z = 0;
973 }
974
975 /* Store the result and condition codes. */
976 State.regs[OP[1]] = result;
977 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
978 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
979 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
980 | (sat ? PSW_SAT : 0));
981
982 trace_output (OP_REG_REG);
983 return 2;
984 }
985
986 /* satsubi sign_extend(imm16), reg */
987 int
988 OP_660 (void)
989 {
990 unsigned int op0, op1, result, z, s, cy, ov, sat;
991 int temp;
992
993 trace_input ("satsubi", OP_IMM_REG, 0);
994
995 /* Compute the result. */
996 temp = EXTEND16 (OP[2]);
997 op0 = temp;
998 op1 = State.regs[ OP[0] ];
999 result = op1 - op0;
1000
1001 /* Compute the condition codes. */
1002 z = (result == 0);
1003 s = (result & 0x80000000);
1004 cy = (op1 < op0);
1005 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1006 && (op1 & 0x80000000) != (result & 0x80000000));
1007 sat = ov;
1008
1009 /* Handle saturated results. */
1010 if (sat && s)
1011 {
1012 /* An overflow that results in a negative result implies that we
1013 became too positive. */
1014 result = 0x7fffffff;
1015 s = 0;
1016 }
1017 else if (sat)
1018 {
1019 /* Any other overflow must have thus been too negative. */
1020 result = 0x80000000;
1021 s = 1;
1022 z = 0;
1023 }
1024
1025 /* Store the result and condition codes. */
1026 State.regs[OP[1]] = result;
1027 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1028 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1029 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1030 | (sat ? PSW_SAT : 0));
1031
1032 trace_output (OP_IMM_REG);
1033
1034 return 4;
1035 }
1036
1037 /* satsubr reg,reg */
1038 int
1039 OP_80 (void)
1040 {
1041 unsigned int op0, op1, result, z, s, cy, ov, sat;
1042
1043 trace_input ("satsubr", OP_REG_REG, 0);
1044
1045 /* Compute the result. */
1046 op0 = State.regs[ OP[0] ];
1047 op1 = State.regs[ OP[1] ];
1048 result = op0 - op1;
1049
1050 /* Compute the condition codes. */
1051 z = (result == 0);
1052 s = (result & 0x80000000);
1053 cy = (op0 < op1);
1054 ov = ((op0 & 0x80000000) != (op1 & 0x80000000)
1055 && (op0 & 0x80000000) != (result & 0x80000000));
1056 sat = ov;
1057
1058 /* Handle saturated results. */
1059 if (sat && s)
1060 {
1061 /* An overflow that results in a negative result implies that we
1062 became too positive. */
1063 result = 0x7fffffff;
1064 s = 0;
1065 }
1066 else if (sat)
1067 {
1068 /* Any other overflow must have thus been too negative. */
1069 result = 0x80000000;
1070 s = 1;
1071 z = 0;
1072 }
1073
1074 /* Store the result and condition codes. */
1075 State.regs[OP[1]] = result;
1076 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1077 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1078 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1079 | (sat ? PSW_SAT : 0));
1080
1081 trace_output (OP_REG_REG);
1082
1083 return 2;
1084 }
1085
1086 /* tst reg,reg */
1087 int
1088 OP_160 (void)
1089 {
1090 unsigned int op0, op1, result, z, s;
1091
1092 trace_input ("tst", OP_REG_REG_CMP, 0);
1093
1094 /* Compute the result. */
1095 op0 = State.regs[ OP[0] ];
1096 op1 = State.regs[ OP[1] ];
1097 result = op0 & op1;
1098
1099 /* Compute the condition codes. */
1100 z = (result == 0);
1101 s = (result & 0x80000000);
1102
1103 /* Store the condition codes. */
1104 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1105 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1106 trace_output (OP_REG_REG_CMP);
1107
1108 return 2;
1109 }
1110
1111 /* mov sign_extend(imm5), reg */
1112 int
1113 OP_200 (void)
1114 {
1115 int value = SEXT5 (OP[0]);
1116
1117 trace_input ("mov", OP_IMM_REG_MOVE, 0);
1118
1119 State.regs[ OP[1] ] = value;
1120
1121 trace_output (OP_IMM_REG_MOVE);
1122
1123 return 2;
1124 }
1125
1126 /* movhi imm16, reg, reg */
1127 int
1128 OP_640 (void)
1129 {
1130 trace_input ("movhi", OP_UIMM16_REG_REG, 16);
1131
1132 State.regs[ OP[1] ] = State.regs[ OP[0] ] + (OP[2] << 16);
1133
1134 trace_output (OP_UIMM16_REG_REG);
1135
1136 return 4;
1137 }
1138
1139 /* sar zero_extend(imm5),reg1 */
1140 int
1141 OP_2A0 (void)
1142 {
1143 unsigned int op0, op1, result, z, s, cy;
1144
1145 trace_input ("sar", OP_IMM_REG, 0);
1146 op0 = OP[0];
1147 op1 = State.regs[ OP[1] ];
1148 result = (signed)op1 >> op0;
1149
1150 /* Compute the condition codes. */
1151 z = (result == 0);
1152 s = (result & 0x80000000);
1153 cy = op0 ? (op1 & (1 << (op0 - 1))) : 0;
1154
1155 /* Store the result and condition codes. */
1156 State.regs[ OP[1] ] = result;
1157 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1158 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1159 | (cy ? PSW_CY : 0));
1160 trace_output (OP_IMM_REG);
1161
1162 return 2;
1163 }
1164
1165 /* sar reg1, reg2 */
1166 int
1167 OP_A007E0 (void)
1168 {
1169 unsigned int op0, op1, result, z, s, cy;
1170
1171 trace_input ("sar", OP_REG_REG, 0);
1172
1173 op0 = State.regs[ OP[0] ] & 0x1f;
1174 op1 = State.regs[ OP[1] ];
1175 result = (signed)op1 >> op0;
1176
1177 /* Compute the condition codes. */
1178 z = (result == 0);
1179 s = (result & 0x80000000);
1180 cy = op0 ? (op1 & (1 << (op0 - 1))) : 0;
1181
1182 /* Store the result and condition codes. */
1183 State.regs[OP[1]] = result;
1184 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1185 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1186 | (cy ? PSW_CY : 0));
1187 trace_output (OP_REG_REG);
1188
1189 return 4;
1190 }
1191
1192 /* shl zero_extend(imm5),reg1 */
1193 int
1194 OP_2C0 (void)
1195 {
1196 unsigned int op0, op1, result, z, s, cy;
1197
1198 trace_input ("shl", OP_IMM_REG, 0);
1199 op0 = OP[0];
1200 op1 = State.regs[ OP[1] ];
1201 result = op1 << op0;
1202
1203 /* Compute the condition codes. */
1204 z = (result == 0);
1205 s = (result & 0x80000000);
1206 cy = op0 ? (op1 & (1 << (32 - op0))) : 0;
1207
1208 /* Store the result and condition codes. */
1209 State.regs[OP[1]] = result;
1210 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1211 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1212 | (cy ? PSW_CY : 0));
1213 trace_output (OP_IMM_REG);
1214
1215 return 2;
1216 }
1217
1218 /* shl reg1, reg2 */
1219 int
1220 OP_C007E0 (void)
1221 {
1222 unsigned int op0, op1, result, z, s, cy;
1223
1224 trace_input ("shl", OP_REG_REG, 0);
1225 op0 = State.regs[ OP[0] ] & 0x1f;
1226 op1 = State.regs[ OP[1] ];
1227 result = op1 << op0;
1228
1229 /* Compute the condition codes. */
1230 z = (result == 0);
1231 s = (result & 0x80000000);
1232 cy = op0 ? (op1 & (1 << (32 - op0))) : 0;
1233
1234 /* Store the result and condition codes. */
1235 State.regs[OP[1]] = result;
1236 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1237 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1238 | (cy ? PSW_CY : 0));
1239 trace_output (OP_REG_REG);
1240
1241 return 4;
1242 }
1243
1244 /* shr zero_extend(imm5),reg1 */
1245 int
1246 OP_280 (void)
1247 {
1248 unsigned int op0, op1, result, z, s, cy;
1249
1250 trace_input ("shr", OP_IMM_REG, 0);
1251 op0 = OP[0];
1252 op1 = State.regs[ OP[1] ];
1253 result = op1 >> op0;
1254
1255 /* Compute the condition codes. */
1256 z = (result == 0);
1257 s = (result & 0x80000000);
1258 cy = op0 ? (op1 & (1 << (op0 - 1))) : 0;
1259
1260 /* Store the result and condition codes. */
1261 State.regs[OP[1]] = result;
1262 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1263 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1264 | (cy ? PSW_CY : 0));
1265 trace_output (OP_IMM_REG);
1266
1267 return 2;
1268 }
1269
1270 /* shr reg1, reg2 */
1271 int
1272 OP_8007E0 (void)
1273 {
1274 unsigned int op0, op1, result, z, s, cy;
1275
1276 trace_input ("shr", OP_REG_REG, 0);
1277 op0 = State.regs[ OP[0] ] & 0x1f;
1278 op1 = State.regs[ OP[1] ];
1279 result = op1 >> op0;
1280
1281 /* Compute the condition codes. */
1282 z = (result == 0);
1283 s = (result & 0x80000000);
1284 cy = op0 ? (op1 & (1 << (op0 - 1))) : 0;
1285
1286 /* Store the result and condition codes. */
1287 State.regs[OP[1]] = result;
1288 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1289 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1290 | (cy ? PSW_CY : 0));
1291 trace_output (OP_REG_REG);
1292
1293 return 4;
1294 }
1295
1296 /* or reg, reg */
1297 int
1298 OP_100 (void)
1299 {
1300 unsigned int op0, op1, result, z, s;
1301
1302 trace_input ("or", OP_REG_REG, 0);
1303
1304 /* Compute the result. */
1305 op0 = State.regs[ OP[0] ];
1306 op1 = State.regs[ OP[1] ];
1307 result = op0 | op1;
1308
1309 /* Compute the condition codes. */
1310 z = (result == 0);
1311 s = (result & 0x80000000);
1312
1313 /* Store the result and condition codes. */
1314 State.regs[OP[1]] = result;
1315 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1316 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1317 trace_output (OP_REG_REG);
1318
1319 return 2;
1320 }
1321
1322 /* ori zero_extend(imm16), reg, reg */
1323 int
1324 OP_680 (void)
1325 {
1326 unsigned int op0, op1, result, z, s;
1327
1328 trace_input ("ori", OP_UIMM16_REG_REG, 0);
1329 op0 = OP[2];
1330 op1 = State.regs[ OP[0] ];
1331 result = op0 | op1;
1332
1333 /* Compute the condition codes. */
1334 z = (result == 0);
1335 s = (result & 0x80000000);
1336
1337 /* Store the result and condition codes. */
1338 State.regs[OP[1]] = result;
1339 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1340 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1341 trace_output (OP_UIMM16_REG_REG);
1342
1343 return 4;
1344 }
1345
1346 /* and reg, reg */
1347 int
1348 OP_140 (void)
1349 {
1350 unsigned int op0, op1, result, z, s;
1351
1352 trace_input ("and", OP_REG_REG, 0);
1353
1354 /* Compute the result. */
1355 op0 = State.regs[ OP[0] ];
1356 op1 = State.regs[ OP[1] ];
1357 result = op0 & op1;
1358
1359 /* Compute the condition codes. */
1360 z = (result == 0);
1361 s = (result & 0x80000000);
1362
1363 /* Store the result and condition codes. */
1364 State.regs[OP[1]] = result;
1365 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1366 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1367 trace_output (OP_REG_REG);
1368
1369 return 2;
1370 }
1371
1372 /* andi zero_extend(imm16), reg, reg */
1373 int
1374 OP_6C0 (void)
1375 {
1376 unsigned int result, z;
1377
1378 trace_input ("andi", OP_UIMM16_REG_REG, 0);
1379
1380 result = OP[2] & State.regs[ OP[0] ];
1381
1382 /* Compute the condition codes. */
1383 z = (result == 0);
1384
1385 /* Store the result and condition codes. */
1386 State.regs[ OP[1] ] = result;
1387
1388 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1389 PSW |= (z ? PSW_Z : 0);
1390
1391 trace_output (OP_UIMM16_REG_REG);
1392
1393 return 4;
1394 }
1395
1396 /* xor reg, reg */
1397 int
1398 OP_120 (void)
1399 {
1400 unsigned int op0, op1, result, z, s;
1401
1402 trace_input ("xor", OP_REG_REG, 0);
1403
1404 /* Compute the result. */
1405 op0 = State.regs[ OP[0] ];
1406 op1 = State.regs[ OP[1] ];
1407 result = op0 ^ op1;
1408
1409 /* Compute the condition codes. */
1410 z = (result == 0);
1411 s = (result & 0x80000000);
1412
1413 /* Store the result and condition codes. */
1414 State.regs[OP[1]] = result;
1415 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1416 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1417 trace_output (OP_REG_REG);
1418
1419 return 2;
1420 }
1421
1422 /* xori zero_extend(imm16), reg, reg */
1423 int
1424 OP_6A0 (void)
1425 {
1426 unsigned int op0, op1, result, z, s;
1427
1428 trace_input ("xori", OP_UIMM16_REG_REG, 0);
1429 op0 = OP[2];
1430 op1 = State.regs[ OP[0] ];
1431 result = op0 ^ op1;
1432
1433 /* Compute the condition codes. */
1434 z = (result == 0);
1435 s = (result & 0x80000000);
1436
1437 /* Store the result and condition codes. */
1438 State.regs[OP[1]] = result;
1439 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1440 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1441 trace_output (OP_UIMM16_REG_REG);
1442
1443 return 4;
1444 }
1445
1446 /* not reg1, reg2 */
1447 int
1448 OP_20 (void)
1449 {
1450 unsigned int op0, result, z, s;
1451
1452 trace_input ("not", OP_REG_REG_MOVE, 0);
1453 /* Compute the result. */
1454 op0 = State.regs[ OP[0] ];
1455 result = ~op0;
1456
1457 /* Compute the condition codes. */
1458 z = (result == 0);
1459 s = (result & 0x80000000);
1460
1461 /* Store the result and condition codes. */
1462 State.regs[OP[1]] = result;
1463 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1464 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1465 trace_output (OP_REG_REG_MOVE);
1466
1467 return 2;
1468 }
1469
1470 /* set1 */
1471 int
1472 OP_7C0 (void)
1473 {
1474 unsigned int op0, op1, op2;
1475 int temp;
1476
1477 trace_input ("set1", OP_BIT, 0);
1478 op0 = State.regs[ OP[0] ];
1479 op1 = OP[1] & 0x7;
1480 temp = EXTEND16 (OP[2]);
1481 op2 = temp;
1482 temp = load_mem (op0 + op2, 1);
1483 PSW &= ~PSW_Z;
1484 if ((temp & (1 << op1)) == 0)
1485 PSW |= PSW_Z;
1486 temp |= (1 << op1);
1487 store_mem (op0 + op2, 1, temp);
1488 trace_output (OP_BIT);
1489
1490 return 4;
1491 }
1492
1493 /* not1 */
1494 int
1495 OP_47C0 (void)
1496 {
1497 unsigned int op0, op1, op2;
1498 int temp;
1499
1500 trace_input ("not1", OP_BIT, 0);
1501 op0 = State.regs[ OP[0] ];
1502 op1 = OP[1] & 0x7;
1503 temp = EXTEND16 (OP[2]);
1504 op2 = temp;
1505 temp = load_mem (op0 + op2, 1);
1506 PSW &= ~PSW_Z;
1507 if ((temp & (1 << op1)) == 0)
1508 PSW |= PSW_Z;
1509 temp ^= (1 << op1);
1510 store_mem (op0 + op2, 1, temp);
1511 trace_output (OP_BIT);
1512
1513 return 4;
1514 }
1515
1516 /* clr1 */
1517 int
1518 OP_87C0 (void)
1519 {
1520 unsigned int op0, op1, op2;
1521 int temp;
1522
1523 trace_input ("clr1", OP_BIT, 0);
1524 op0 = State.regs[ OP[0] ];
1525 op1 = OP[1] & 0x7;
1526 temp = EXTEND16 (OP[2]);
1527 op2 = temp;
1528 temp = load_mem (op0 + op2, 1);
1529 PSW &= ~PSW_Z;
1530 if ((temp & (1 << op1)) == 0)
1531 PSW |= PSW_Z;
1532 temp &= ~(1 << op1);
1533 store_mem (op0 + op2, 1, temp);
1534 trace_output (OP_BIT);
1535
1536 return 4;
1537 }
1538
1539 /* tst1 */
1540 int
1541 OP_C7C0 (void)
1542 {
1543 unsigned int op0, op1, op2;
1544 int temp;
1545
1546 trace_input ("tst1", OP_BIT, 0);
1547 op0 = State.regs[ OP[0] ];
1548 op1 = OP[1] & 0x7;
1549 temp = EXTEND16 (OP[2]);
1550 op2 = temp;
1551 temp = load_mem (op0 + op2, 1);
1552 PSW &= ~PSW_Z;
1553 if ((temp & (1 << op1)) == 0)
1554 PSW |= PSW_Z;
1555 trace_output (OP_BIT);
1556
1557 return 4;
1558 }
1559
1560 /* di */
1561 int
1562 OP_16007E0 (void)
1563 {
1564 trace_input ("di", OP_NONE, 0);
1565 PSW |= PSW_ID;
1566 trace_output (OP_NONE);
1567
1568 return 4;
1569 }
1570
1571 /* ei */
1572 int
1573 OP_16087E0 (void)
1574 {
1575 trace_input ("ei", OP_NONE, 0);
1576 PSW &= ~PSW_ID;
1577 trace_output (OP_NONE);
1578
1579 return 4;
1580 }
1581
1582 /* halt */
1583 int
1584 OP_12007E0 (void)
1585 {
1586 trace_input ("halt", OP_NONE, 0);
1587 /* FIXME this should put processor into a mode where NMI still handled */
1588 trace_output (OP_NONE);
1589 sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
1590 sim_stopped, SIM_SIGTRAP);
1591 return 0;
1592 }
1593
1594 /* trap */
1595 int
1596 OP_10007E0 (void)
1597 {
1598 trace_input ("trap", OP_TRAP, 0);
1599 trace_output (OP_TRAP);
1600
1601 /* Trap 31 is used for simulating OS I/O functions */
1602
1603 if (OP[0] == 31)
1604 {
1605 int save_errno = errno;
1606 errno = 0;
1607
1608 /* Registers passed to trap 0 */
1609
1610 #define FUNC State.regs[6] /* function number, return value */
1611 #define PARM1 State.regs[7] /* optional parm 1 */
1612 #define PARM2 State.regs[8] /* optional parm 2 */
1613 #define PARM3 State.regs[9] /* optional parm 3 */
1614
1615 /* Registers set by trap 0 */
1616
1617 #define RETVAL State.regs[10] /* return value */
1618 #define RETERR State.regs[11] /* return error code */
1619
1620 /* Turn a pointer in a register into a pointer into real memory. */
1621
1622 #define MEMPTR(x) (map (x))
1623
1624 RETERR = 0;
1625
1626 switch (FUNC)
1627 {
1628
1629 #ifdef HAVE_FORK
1630 case TARGET_NEWLIB_V850_SYS_fork:
1631 RETVAL = fork ();
1632 RETERR = errno;
1633 break;
1634 #endif
1635
1636 #ifdef HAVE_EXECVE
1637 case TARGET_NEWLIB_V850_SYS_execve:
1638 {
1639 char *path = fetch_str (simulator, PARM1);
1640 char **argv = fetch_argv (simulator, PARM2);
1641 char **envp = fetch_argv (simulator, PARM3);
1642 RETVAL = execve (path, (void *)argv, (void *)envp);
1643 free (path);
1644 freeargv (argv);
1645 freeargv (envp);
1646 RETERR = errno;
1647 break;
1648 }
1649 #endif
1650
1651 #if HAVE_EXECV
1652 case TARGET_NEWLIB_V850_SYS_execv:
1653 {
1654 char *path = fetch_str (simulator, PARM1);
1655 char **argv = fetch_argv (simulator, PARM2);
1656 RETVAL = execv (path, (void *)argv);
1657 free (path);
1658 freeargv (argv);
1659 RETERR = errno;
1660 break;
1661 }
1662 #endif
1663
1664 #if 0
1665 case TARGET_NEWLIB_V850_SYS_pipe:
1666 {
1667 reg_t buf;
1668 int host_fd[2];
1669
1670 buf = PARM1;
1671 RETVAL = pipe (host_fd);
1672 SW (buf, host_fd[0]);
1673 buf += sizeof (uint16_t);
1674 SW (buf, host_fd[1]);
1675 RETERR = errno;
1676 }
1677 break;
1678 #endif
1679
1680 #if 0
1681 case TARGET_NEWLIB_V850_SYS_wait:
1682 {
1683 int status;
1684
1685 RETVAL = wait (&status);
1686 SW (PARM1, status);
1687 RETERR = errno;
1688 }
1689 break;
1690 #endif
1691
1692 case TARGET_NEWLIB_V850_SYS_read:
1693 {
1694 char *buf = zalloc (PARM3);
1695 RETVAL = sim_io_read (simulator, PARM1, buf, PARM3);
1696 sim_write (simulator, PARM2, buf, PARM3);
1697 free (buf);
1698 if ((int) RETVAL < 0)
1699 RETERR = sim_io_get_errno (simulator);
1700 break;
1701 }
1702
1703 case TARGET_NEWLIB_V850_SYS_write:
1704 {
1705 char *buf = zalloc (PARM3);
1706 sim_read (simulator, PARM2, buf, PARM3);
1707 if (PARM1 == 1)
1708 RETVAL = sim_io_write_stdout (simulator, buf, PARM3);
1709 else
1710 RETVAL = sim_io_write (simulator, PARM1, buf, PARM3);
1711 free (buf);
1712 if ((int) RETVAL < 0)
1713 RETERR = sim_io_get_errno (simulator);
1714 break;
1715 }
1716
1717 case TARGET_NEWLIB_V850_SYS_lseek:
1718 RETVAL = sim_io_lseek (simulator, PARM1, PARM2, PARM3);
1719 if ((int) RETVAL < 0)
1720 RETERR = sim_io_get_errno (simulator);
1721 break;
1722
1723 case TARGET_NEWLIB_V850_SYS_close:
1724 RETVAL = sim_io_close (simulator, PARM1);
1725 if ((int) RETVAL < 0)
1726 RETERR = sim_io_get_errno (simulator);
1727 break;
1728
1729 case TARGET_NEWLIB_V850_SYS_open:
1730 {
1731 char *buf = fetch_str (simulator, PARM1);
1732 RETVAL = sim_io_open (simulator, buf, PARM2);
1733 free (buf);
1734 if ((int) RETVAL < 0)
1735 RETERR = sim_io_get_errno (simulator);
1736 break;
1737 }
1738
1739 case TARGET_NEWLIB_V850_SYS_exit:
1740 if ((PARM1 & 0xffff0000) == 0xdead0000 && (PARM1 & 0xffff) != 0)
1741 /* get signal encoded by kill */
1742 sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
1743 sim_signalled, PARM1 & 0xffff);
1744 else if (PARM1 == 0xdead)
1745 /* old libraries */
1746 sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
1747 sim_stopped, SIM_SIGABRT);
1748 else
1749 /* PARM1 has exit status */
1750 sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
1751 sim_exited, PARM1);
1752 break;
1753
1754 case TARGET_NEWLIB_V850_SYS_stat: /* added at hmsi */
1755 /* stat system call */
1756 {
1757 struct stat host_stat;
1758 reg_t buf;
1759 char *path = fetch_str (simulator, PARM1);
1760
1761 RETVAL = sim_io_stat (simulator, path, &host_stat);
1762
1763 free (path);
1764 buf = PARM2;
1765
1766 /* Just wild-assed guesses. */
1767 store_mem (buf, 2, host_stat.st_dev);
1768 store_mem (buf + 2, 2, host_stat.st_ino);
1769 store_mem (buf + 4, 4, host_stat.st_mode);
1770 store_mem (buf + 8, 2, host_stat.st_nlink);
1771 store_mem (buf + 10, 2, host_stat.st_uid);
1772 store_mem (buf + 12, 2, host_stat.st_gid);
1773 store_mem (buf + 14, 2, host_stat.st_rdev);
1774 store_mem (buf + 16, 4, host_stat.st_size);
1775 store_mem (buf + 20, 4, host_stat.st_atime);
1776 store_mem (buf + 28, 4, host_stat.st_mtime);
1777 store_mem (buf + 36, 4, host_stat.st_ctime);
1778
1779 if ((int) RETVAL < 0)
1780 RETERR = sim_io_get_errno (simulator);
1781 }
1782 break;
1783
1784 case TARGET_NEWLIB_V850_SYS_fstat:
1785 /* fstat system call */
1786 {
1787 struct stat host_stat;
1788 reg_t buf;
1789
1790 RETVAL = sim_io_fstat (simulator, PARM1, &host_stat);
1791
1792 buf = PARM2;
1793
1794 /* Just wild-assed guesses. */
1795 store_mem (buf, 2, host_stat.st_dev);
1796 store_mem (buf + 2, 2, host_stat.st_ino);
1797 store_mem (buf + 4, 4, host_stat.st_mode);
1798 store_mem (buf + 8, 2, host_stat.st_nlink);
1799 store_mem (buf + 10, 2, host_stat.st_uid);
1800 store_mem (buf + 12, 2, host_stat.st_gid);
1801 store_mem (buf + 14, 2, host_stat.st_rdev);
1802 store_mem (buf + 16, 4, host_stat.st_size);
1803 store_mem (buf + 20, 4, host_stat.st_atime);
1804 store_mem (buf + 28, 4, host_stat.st_mtime);
1805 store_mem (buf + 36, 4, host_stat.st_ctime);
1806
1807 if ((int) RETVAL < 0)
1808 RETERR = sim_io_get_errno (simulator);
1809 }
1810 break;
1811
1812 case TARGET_NEWLIB_V850_SYS_rename:
1813 {
1814 char *oldpath = fetch_str (simulator, PARM1);
1815 char *newpath = fetch_str (simulator, PARM2);
1816 RETVAL = sim_io_rename (simulator, oldpath, newpath);
1817 free (oldpath);
1818 free (newpath);
1819 if ((int) RETVAL < 0)
1820 RETERR = sim_io_get_errno (simulator);
1821 }
1822 break;
1823
1824 case TARGET_NEWLIB_V850_SYS_unlink:
1825 {
1826 char *path = fetch_str (simulator, PARM1);
1827 RETVAL = sim_io_unlink (simulator, path);
1828 free (path);
1829 if ((int) RETVAL < 0)
1830 RETERR = sim_io_get_errno (simulator);
1831 }
1832 break;
1833
1834 case TARGET_NEWLIB_V850_SYS_chown:
1835 {
1836 char *path = fetch_str (simulator, PARM1);
1837 RETVAL = chown (path, PARM2, PARM3);
1838 free (path);
1839 RETERR = errno;
1840 }
1841 break;
1842
1843 #if HAVE_CHMOD
1844 case TARGET_NEWLIB_V850_SYS_chmod:
1845 {
1846 char *path = fetch_str (simulator, PARM1);
1847 RETVAL = chmod (path, PARM2);
1848 free (path);
1849 RETERR = errno;
1850 }
1851 break;
1852 #endif
1853
1854 #if HAVE_TIME
1855 case TARGET_NEWLIB_V850_SYS_time:
1856 {
1857 time_t now;
1858 RETVAL = time (&now);
1859 store_mem (PARM1, 4, now);
1860 RETERR = errno;
1861 }
1862 break;
1863 #endif
1864
1865 #if !defined(__GO32__) && !defined(_WIN32)
1866 case TARGET_NEWLIB_V850_SYS_times:
1867 {
1868 struct tms tms;
1869 RETVAL = times (&tms);
1870 store_mem (PARM1, 4, tms.tms_utime);
1871 store_mem (PARM1 + 4, 4, tms.tms_stime);
1872 store_mem (PARM1 + 8, 4, tms.tms_cutime);
1873 store_mem (PARM1 + 12, 4, tms.tms_cstime);
1874 RETERR = errno;
1875 break;
1876 }
1877 #endif
1878
1879 #if !defined(__GO32__) && !defined(_WIN32)
1880 case TARGET_NEWLIB_V850_SYS_gettimeofday:
1881 {
1882 struct timeval t;
1883 struct timezone tz;
1884 RETVAL = gettimeofday (&t, &tz);
1885 store_mem (PARM1, 4, t.tv_sec);
1886 store_mem (PARM1 + 4, 4, t.tv_usec);
1887 store_mem (PARM2, 4, tz.tz_minuteswest);
1888 store_mem (PARM2 + 4, 4, tz.tz_dsttime);
1889 RETERR = errno;
1890 break;
1891 }
1892 #endif
1893
1894 #if HAVE_UTIME
1895 case TARGET_NEWLIB_V850_SYS_utime:
1896 {
1897 /* Cast the second argument to void *, to avoid type mismatch
1898 if a prototype is present. */
1899 sim_io_error (simulator, "Utime not supported");
1900 /* RETVAL = utime (path, (void *) MEMPTR (PARM2)); */
1901 }
1902 break;
1903 #endif
1904
1905 default:
1906 abort ();
1907 }
1908 errno = save_errno;
1909
1910 return 4;
1911 }
1912 else
1913 { /* Trap 0 -> 30 */
1914 EIPC = PC + 4;
1915 EIPSW = PSW;
1916 /* Mask out EICC */
1917 ECR &= 0xffff0000;
1918 ECR |= 0x40 + OP[0];
1919 /* Flag that we are now doing exception processing. */
1920 PSW |= PSW_EP | PSW_ID;
1921 PC = (OP[0] < 0x10) ? 0x40 : 0x50;
1922
1923 return 0;
1924 }
1925 }
1926
1927 /* tst1 reg2, [reg1] */
1928 int
1929 OP_E607E0 (void)
1930 {
1931 int temp;
1932
1933 trace_input ("tst1", OP_BIT, 1);
1934
1935 temp = load_mem (State.regs[ OP[0] ], 1);
1936
1937 PSW &= ~PSW_Z;
1938 if ((temp & (1 << (State.regs[ OP[1] ] & 0x7))) == 0)
1939 PSW |= PSW_Z;
1940
1941 trace_output (OP_BIT);
1942
1943 return 4;
1944 }
1945
1946 /* mulu reg1, reg2, reg3 */
1947 int
1948 OP_22207E0 (void)
1949 {
1950 trace_input ("mulu", OP_REG_REG_REG, 0);
1951
1952 Multiply64 (0, State.regs[ OP[0] ]);
1953
1954 trace_output (OP_REG_REG_REG);
1955
1956 return 4;
1957 }
1958
1959 #define BIT_CHANGE_OP( name, binop ) \
1960 unsigned int bit; \
1961 unsigned int temp; \
1962 \
1963 trace_input (name, OP_BIT_CHANGE, 0); \
1964 \
1965 bit = 1 << (State.regs[ OP[1] ] & 0x7); \
1966 temp = load_mem (State.regs[ OP[0] ], 1); \
1967 \
1968 PSW &= ~PSW_Z; \
1969 if ((temp & bit) == 0) \
1970 PSW |= PSW_Z; \
1971 temp binop bit; \
1972 \
1973 store_mem (State.regs[ OP[0] ], 1, temp); \
1974 \
1975 trace_output (OP_BIT_CHANGE); \
1976 \
1977 return 4;
1978
1979 /* clr1 reg2, [reg1] */
1980 int
1981 OP_E407E0 (void)
1982 {
1983 BIT_CHANGE_OP ("clr1", &= ~ );
1984 }
1985
1986 /* not1 reg2, [reg1] */
1987 int
1988 OP_E207E0 (void)
1989 {
1990 BIT_CHANGE_OP ("not1", ^= );
1991 }
1992
1993 /* set1 */
1994 int
1995 OP_E007E0 (void)
1996 {
1997 BIT_CHANGE_OP ("set1", |= );
1998 }
1999
2000 /* sasf */
2001 int
2002 OP_20007E0 (void)
2003 {
2004 trace_input ("sasf", OP_EX1, 0);
2005
2006 State.regs[ OP[1] ] = (State.regs[ OP[1] ] << 1) | condition_met (OP[0]);
2007
2008 trace_output (OP_EX1);
2009
2010 return 4;
2011 }
2012
2013 /* This function is courtesy of Sugimoto at NEC, via Seow Tan
2014 (Soew_Tan@el.nec.com) */
2015 void
2016 divun
2017 (
2018 unsigned int N,
2019 unsigned long int als,
2020 unsigned long int sfi,
2021 uint32_t /*unsigned long int*/ * quotient_ptr,
2022 uint32_t /*unsigned long int*/ * remainder_ptr,
2023 int * overflow_ptr
2024 )
2025 {
2026 unsigned long ald = sfi >> (N - 1);
2027 unsigned long alo = als;
2028 unsigned int Q = 1;
2029 unsigned int C;
2030 unsigned int S = 0;
2031 unsigned int i;
2032 unsigned int R1 = 1;
2033 unsigned int DBZ = (als == 0) ? 1 : 0;
2034 unsigned long alt = Q ? ~als : als;
2035
2036 /* 1st Loop */
2037 alo = ald + alt + Q;
2038 C = (((alt >> 31) & (ald >> 31))
2039 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2040 C = C ^ Q;
2041 Q = ~(C ^ S) & 1;
2042 R1 = (alo == 0) ? 0 : (R1 & Q);
2043 if ((S ^ (alo>>31)) && !C)
2044 {
2045 DBZ = 1;
2046 }
2047 S = alo >> 31;
2048 sfi = (sfi << (32-N+1)) | Q;
2049 ald = (alo << 1) | (sfi >> 31);
2050
2051 /* 2nd - N-1th Loop */
2052 for (i = 2; i < N; i++)
2053 {
2054 alt = Q ? ~als : als;
2055 alo = ald + alt + Q;
2056 C = (((alt >> 31) & (ald >> 31))
2057 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2058 C = C ^ Q;
2059 Q = ~(C ^ S) & 1;
2060 R1 = (alo == 0) ? 0 : (R1 & Q);
2061 if ((S ^ (alo>>31)) && !C && !DBZ)
2062 {
2063 DBZ = 1;
2064 }
2065 S = alo >> 31;
2066 sfi = (sfi << 1) | Q;
2067 ald = (alo << 1) | (sfi >> 31);
2068 }
2069
2070 /* Nth Loop */
2071 alt = Q ? ~als : als;
2072 alo = ald + alt + Q;
2073 C = (((alt >> 31) & (ald >> 31))
2074 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2075 C = C ^ Q;
2076 Q = ~(C ^ S) & 1;
2077 R1 = (alo == 0) ? 0 : (R1 & Q);
2078 if ((S ^ (alo>>31)) && !C)
2079 {
2080 DBZ = 1;
2081 }
2082
2083 * quotient_ptr = (sfi << 1) | Q;
2084 * remainder_ptr = Q ? alo : (alo + als);
2085 * overflow_ptr = DBZ | R1;
2086 }
2087
2088 /* This function is courtesy of Sugimoto at NEC, via Seow Tan (Soew_Tan@el.nec.com) */
2089 void
2090 divn
2091 (
2092 unsigned int N,
2093 unsigned long int als,
2094 unsigned long int sfi,
2095 int32_t /*signed long int*/ * quotient_ptr,
2096 int32_t /*signed long int*/ * remainder_ptr,
2097 int * overflow_ptr
2098 )
2099 {
2100 unsigned long ald = (signed long) sfi >> (N - 1);
2101 unsigned long alo = als;
2102 unsigned int SS = als >> 31;
2103 unsigned int SD = sfi >> 31;
2104 unsigned int R1 = 1;
2105 unsigned int OV;
2106 unsigned int DBZ = als == 0 ? 1 : 0;
2107 unsigned int Q = ~(SS ^ SD) & 1;
2108 unsigned int C;
2109 unsigned int S;
2110 unsigned int i;
2111 unsigned long alt = Q ? ~als : als;
2112
2113
2114 /* 1st Loop */
2115
2116 alo = ald + alt + Q;
2117 C = (((alt >> 31) & (ald >> 31))
2118 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2119 Q = C ^ SS;
2120 R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD)));
2121 S = alo >> 31;
2122 sfi = (sfi << (32-N+1)) | Q;
2123 ald = (alo << 1) | (sfi >> 31);
2124 if ((alo >> 31) ^ (ald >> 31))
2125 {
2126 DBZ = 1;
2127 }
2128
2129 /* 2nd - N-1th Loop */
2130
2131 for (i = 2; i < N; i++)
2132 {
2133 alt = Q ? ~als : als;
2134 alo = ald + alt + Q;
2135 C = (((alt >> 31) & (ald >> 31))
2136 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2137 Q = C ^ SS;
2138 R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD)));
2139 S = alo >> 31;
2140 sfi = (sfi << 1) | Q;
2141 ald = (alo << 1) | (sfi >> 31);
2142 if ((alo >> 31) ^ (ald >> 31))
2143 {
2144 DBZ = 1;
2145 }
2146 }
2147
2148 /* Nth Loop */
2149 alt = Q ? ~als : als;
2150 alo = ald + alt + Q;
2151 C = (((alt >> 31) & (ald >> 31))
2152 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2153 Q = C ^ SS;
2154 R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD)));
2155 sfi = (sfi << (32-N+1));
2156 ald = alo;
2157
2158 /* End */
2159 if (alo != 0)
2160 {
2161 alt = Q ? ~als : als;
2162 alo = ald + alt + Q;
2163 }
2164 R1 = R1 & ((~alo >> 31) ^ SD);
2165 if ((alo != 0) && ((Q ^ (SS ^ SD)) ^ R1)) alo = ald;
2166 if (N != 32)
2167 ald = sfi = (long) ((sfi >> 1) | (SS ^ SD) << 31) >> (32-N-1) | Q;
2168 else
2169 ald = sfi = sfi | Q;
2170
2171 OV = DBZ | ((alo == 0) ? 0 : R1);
2172
2173 * remainder_ptr = alo;
2174
2175 /* Adj */
2176 if (((alo != 0) && ((SS ^ SD) ^ R1))
2177 || ((alo == 0) && (SS ^ R1)))
2178 alo = ald + 1;
2179 else
2180 alo = ald;
2181
2182 OV = (DBZ | R1) ? OV : ((alo >> 31) & (~ald >> 31));
2183
2184 * quotient_ptr = alo;
2185 * overflow_ptr = OV;
2186 }
2187
2188 /* sdivun imm5, reg1, reg2, reg3 */
2189 int
2190 OP_1C207E0 (void)
2191 {
2192 uint32_t /*unsigned long int*/ quotient;
2193 uint32_t /*unsigned long int*/ remainder;
2194 unsigned long int divide_by;
2195 unsigned long int divide_this;
2196 int overflow = 0;
2197 unsigned int imm5;
2198
2199 trace_input ("sdivun", OP_IMM_REG_REG_REG, 0);
2200
2201 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2202
2203 divide_by = State.regs[ OP[0] ];
2204 divide_this = State.regs[ OP[1] ] << imm5;
2205
2206 divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2207
2208 State.regs[ OP[1] ] = quotient;
2209 State.regs[ OP[2] >> 11 ] = remainder;
2210
2211 /* Set condition codes. */
2212 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2213
2214 if (overflow) PSW |= PSW_OV;
2215 if (quotient == 0) PSW |= PSW_Z;
2216 if (quotient & 0x80000000) PSW |= PSW_S;
2217
2218 trace_output (OP_IMM_REG_REG_REG);
2219
2220 return 4;
2221 }
2222
2223 /* sdivn imm5, reg1, reg2, reg3 */
2224 int
2225 OP_1C007E0 (void)
2226 {
2227 int32_t /*signed long int*/ quotient;
2228 int32_t /*signed long int*/ remainder;
2229 signed long int divide_by;
2230 signed long int divide_this;
2231 int overflow = 0;
2232 unsigned int imm5;
2233
2234 trace_input ("sdivn", OP_IMM_REG_REG_REG, 0);
2235
2236 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2237
2238 divide_by = (int32_t) State.regs[ OP[0] ];
2239 divide_this = (int32_t) (State.regs[ OP[1] ] << imm5);
2240
2241 divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2242
2243 State.regs[ OP[1] ] = quotient;
2244 State.regs[ OP[2] >> 11 ] = remainder;
2245
2246 /* Set condition codes. */
2247 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2248
2249 if (overflow) PSW |= PSW_OV;
2250 if (quotient == 0) PSW |= PSW_Z;
2251 if (quotient < 0) PSW |= PSW_S;
2252
2253 trace_output (OP_IMM_REG_REG_REG);
2254
2255 return 4;
2256 }
2257
2258 /* sdivhun imm5, reg1, reg2, reg3 */
2259 int
2260 OP_18207E0 (void)
2261 {
2262 uint32_t /*unsigned long int*/ quotient;
2263 uint32_t /*unsigned long int*/ remainder;
2264 unsigned long int divide_by;
2265 unsigned long int divide_this;
2266 int overflow = 0;
2267 unsigned int imm5;
2268
2269 trace_input ("sdivhun", OP_IMM_REG_REG_REG, 0);
2270
2271 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2272
2273 divide_by = State.regs[ OP[0] ] & 0xffff;
2274 divide_this = State.regs[ OP[1] ] << imm5;
2275
2276 divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2277
2278 State.regs[ OP[1] ] = quotient;
2279 State.regs[ OP[2] >> 11 ] = remainder;
2280
2281 /* Set condition codes. */
2282 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2283
2284 if (overflow) PSW |= PSW_OV;
2285 if (quotient == 0) PSW |= PSW_Z;
2286 if (quotient & 0x80000000) PSW |= PSW_S;
2287
2288 trace_output (OP_IMM_REG_REG_REG);
2289
2290 return 4;
2291 }
2292
2293 /* sdivhn imm5, reg1, reg2, reg3 */
2294 int
2295 OP_18007E0 (void)
2296 {
2297 int32_t /*signed long int*/ quotient;
2298 int32_t /*signed long int*/ remainder;
2299 signed long int divide_by;
2300 signed long int divide_this;
2301 int overflow = 0;
2302 unsigned int imm5;
2303
2304 trace_input ("sdivhn", OP_IMM_REG_REG_REG, 0);
2305
2306 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2307
2308 divide_by = EXTEND16 (State.regs[ OP[0] ]);
2309 divide_this = (int32_t) (State.regs[ OP[1] ] << imm5);
2310
2311 divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2312
2313 State.regs[ OP[1] ] = quotient;
2314 State.regs[ OP[2] >> 11 ] = remainder;
2315
2316 /* Set condition codes. */
2317 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2318
2319 if (overflow) PSW |= PSW_OV;
2320 if (quotient == 0) PSW |= PSW_Z;
2321 if (quotient < 0) PSW |= PSW_S;
2322
2323 trace_output (OP_IMM_REG_REG_REG);
2324
2325 return 4;
2326 }
2327
2328 /* divu reg1, reg2, reg3 */
2329 int
2330 OP_2C207E0 (void)
2331 {
2332 unsigned long int quotient;
2333 unsigned long int remainder;
2334 unsigned long int divide_by;
2335 unsigned long int divide_this;
2336 int overflow = 0;
2337
2338 trace_input ("divu", OP_REG_REG_REG, 0);
2339
2340 /* Compute the result. */
2341
2342 divide_by = State.regs[ OP[0] ];
2343 divide_this = State.regs[ OP[1] ];
2344
2345 if (divide_by == 0)
2346 {
2347 PSW |= PSW_OV;
2348 }
2349 else
2350 {
2351 State.regs[ OP[1] ] = quotient = divide_this / divide_by;
2352 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
2353
2354 /* Set condition codes. */
2355 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2356
2357 if (overflow) PSW |= PSW_OV;
2358 if (quotient == 0) PSW |= PSW_Z;
2359 if (quotient & 0x80000000) PSW |= PSW_S;
2360 }
2361
2362 trace_output (OP_REG_REG_REG);
2363
2364 return 4;
2365 }
2366
2367 /* div reg1, reg2, reg3 */
2368 int
2369 OP_2C007E0 (void)
2370 {
2371 signed long int quotient;
2372 signed long int remainder;
2373 signed long int divide_by;
2374 signed long int divide_this;
2375
2376 trace_input ("div", OP_REG_REG_REG, 0);
2377
2378 /* Compute the result. */
2379
2380 divide_by = (int32_t) State.regs[ OP[0] ];
2381 divide_this = State.regs[ OP[1] ];
2382
2383 if (divide_by == 0)
2384 {
2385 PSW |= PSW_OV;
2386 }
2387 else if (divide_by == -1 && divide_this == (1L << 31))
2388 {
2389 PSW &= ~PSW_Z;
2390 PSW |= PSW_OV | PSW_S;
2391 State.regs[ OP[1] ] = (1 << 31);
2392 State.regs[ OP[2] >> 11 ] = 0;
2393 }
2394 else
2395 {
2396 divide_this = (int32_t) divide_this;
2397 State.regs[ OP[1] ] = quotient = divide_this / divide_by;
2398 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
2399
2400 /* Set condition codes. */
2401 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2402
2403 if (quotient == 0) PSW |= PSW_Z;
2404 if (quotient < 0) PSW |= PSW_S;
2405 }
2406
2407 trace_output (OP_REG_REG_REG);
2408
2409 return 4;
2410 }
2411
2412 /* divhu reg1, reg2, reg3 */
2413 int
2414 OP_28207E0 (void)
2415 {
2416 unsigned long int quotient;
2417 unsigned long int remainder;
2418 unsigned long int divide_by;
2419 unsigned long int divide_this;
2420 int overflow = 0;
2421
2422 trace_input ("divhu", OP_REG_REG_REG, 0);
2423
2424 /* Compute the result. */
2425
2426 divide_by = State.regs[ OP[0] ] & 0xffff;
2427 divide_this = State.regs[ OP[1] ];
2428
2429 if (divide_by == 0)
2430 {
2431 PSW |= PSW_OV;
2432 }
2433 else
2434 {
2435 State.regs[ OP[1] ] = quotient = divide_this / divide_by;
2436 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
2437
2438 /* Set condition codes. */
2439 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2440
2441 if (overflow) PSW |= PSW_OV;
2442 if (quotient == 0) PSW |= PSW_Z;
2443 if (quotient & 0x80000000) PSW |= PSW_S;
2444 }
2445
2446 trace_output (OP_REG_REG_REG);
2447
2448 return 4;
2449 }
2450
2451 /* divh reg1, reg2, reg3 */
2452 int
2453 OP_28007E0 (void)
2454 {
2455 signed long int quotient;
2456 signed long int remainder;
2457 signed long int divide_by;
2458 signed long int divide_this;
2459 int overflow = 0;
2460
2461 trace_input ("divh", OP_REG_REG_REG, 0);
2462
2463 /* Compute the result. */
2464
2465 divide_by = EXTEND16 (State.regs[ OP[0] ]);
2466 divide_this = State.regs[ OP[1] ];
2467
2468 if (divide_by == 0)
2469 {
2470 PSW |= PSW_OV;
2471 }
2472 else if (divide_by == -1 && divide_this == (1L << 31))
2473 {
2474 PSW &= ~PSW_Z;
2475 PSW |= PSW_OV | PSW_S;
2476 State.regs[ OP[1] ] = (1 << 31);
2477 State.regs[ OP[2] >> 11 ] = 0;
2478 }
2479 else
2480 {
2481 divide_this = (int32_t) divide_this;
2482 State.regs[ OP[1] ] = quotient = divide_this / divide_by;
2483 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
2484
2485 /* Set condition codes. */
2486 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2487
2488 if (quotient == 0) PSW |= PSW_Z;
2489 if (quotient < 0) PSW |= PSW_S;
2490 }
2491
2492 trace_output (OP_REG_REG_REG);
2493
2494 return 4;
2495 }
2496
2497 /* mulu imm9, reg2, reg3 */
2498 int
2499 OP_24207E0 (void)
2500 {
2501 trace_input ("mulu", OP_IMM_REG_REG, 0);
2502
2503 Multiply64 (0, (OP[3] & 0x1f) | ((OP[3] >> 13) & 0x1e0));
2504
2505 trace_output (OP_IMM_REG_REG);
2506
2507 return 4;
2508 }
2509
2510 /* mul imm9, reg2, reg3 */
2511 int
2512 OP_24007E0 (void)
2513 {
2514 trace_input ("mul", OP_IMM_REG_REG, 0);
2515
2516 Multiply64 (1, SEXT9 ((OP[3] & 0x1f) | ((OP[3] >> 13) & 0x1e0)));
2517
2518 trace_output (OP_IMM_REG_REG);
2519
2520 return 4;
2521 }
2522
2523 /* ld.hu */
2524 int
2525 OP_107E0 (void)
2526 {
2527 int adr;
2528
2529 trace_input ("ld.hu", OP_LOAD32, 2);
2530
2531 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2] & ~1);
2532 adr &= ~0x1;
2533
2534 State.regs[ OP[1] ] = load_mem (adr, 2);
2535
2536 trace_output (OP_LOAD32);
2537
2538 return 4;
2539 }
2540
2541
2542 /* ld.bu */
2543 int
2544 OP_10780 (void)
2545 {
2546 int adr;
2547
2548 trace_input ("ld.bu", OP_LOAD32, 1);
2549
2550 adr = (State.regs[ OP[0] ]
2551 + (EXTEND16 (OP[2] & ~1) | ((OP[3] >> 5) & 1)));
2552
2553 State.regs[ OP[1] ] = load_mem (adr, 1);
2554
2555 trace_output (OP_LOAD32);
2556
2557 return 4;
2558 }
2559
2560 /* prepare list12, imm5, imm32 */
2561 int
2562 OP_1B0780 (void)
2563 {
2564 int i;
2565
2566 trace_input ("prepare", OP_PUSHPOP1, 0);
2567
2568 /* Store the registers with lower number registers being placed at higher addresses. */
2569 for (i = 0; i < 12; i++)
2570 if ((OP[3] & (1 << type1_regs[ i ])))
2571 {
2572 SP -= 4;
2573 store_mem (SP, 4, State.regs[ 20 + i ]);
2574 }
2575
2576 SP -= (OP[3] & 0x3e) << 1;
2577
2578 EP = load_mem (PC + 4, 4);
2579
2580 trace_output (OP_PUSHPOP1);
2581
2582 return 8;
2583 }
2584
2585 /* prepare list12, imm5, imm16-32 */
2586 int
2587 OP_130780 (void)
2588 {
2589 int i;
2590
2591 trace_input ("prepare", OP_PUSHPOP1, 0);
2592
2593 /* Store the registers with lower number registers being placed at higher addresses. */
2594 for (i = 0; i < 12; i++)
2595 if ((OP[3] & (1 << type1_regs[ i ])))
2596 {
2597 SP -= 4;
2598 store_mem (SP, 4, State.regs[ 20 + i ]);
2599 }
2600
2601 SP -= (OP[3] & 0x3e) << 1;
2602
2603 EP = load_mem (PC + 4, 2) << 16;
2604
2605 trace_output (OP_PUSHPOP1);
2606
2607 return 6;
2608 }
2609
2610 /* prepare list12, imm5, imm16 */
2611 int
2612 OP_B0780 (void)
2613 {
2614 int i;
2615
2616 trace_input ("prepare", OP_PUSHPOP1, 0);
2617
2618 /* Store the registers with lower number registers being placed at higher addresses. */
2619 for (i = 0; i < 12; i++)
2620 if ((OP[3] & (1 << type1_regs[ i ])))
2621 {
2622 SP -= 4;
2623 store_mem (SP, 4, State.regs[ 20 + i ]);
2624 }
2625
2626 SP -= (OP[3] & 0x3e) << 1;
2627
2628 EP = EXTEND16 (load_mem (PC + 4, 2));
2629
2630 trace_output (OP_PUSHPOP1);
2631
2632 return 6;
2633 }
2634
2635 /* prepare list12, imm5, sp */
2636 int
2637 OP_30780 (void)
2638 {
2639 int i;
2640
2641 trace_input ("prepare", OP_PUSHPOP1, 0);
2642
2643 /* Store the registers with lower number registers being placed at higher addresses. */
2644 for (i = 0; i < 12; i++)
2645 if ((OP[3] & (1 << type1_regs[ i ])))
2646 {
2647 SP -= 4;
2648 store_mem (SP, 4, State.regs[ 20 + i ]);
2649 }
2650
2651 SP -= (OP[3] & 0x3e) << 1;
2652
2653 EP = SP;
2654
2655 trace_output (OP_PUSHPOP1);
2656
2657 return 4;
2658 }
2659
2660 /* mul reg1, reg2, reg3 */
2661 int
2662 OP_22007E0 (void)
2663 {
2664 trace_input ("mul", OP_REG_REG_REG, 0);
2665
2666 Multiply64 (1, State.regs[ OP[0] ]);
2667
2668 trace_output (OP_REG_REG_REG);
2669
2670 return 4;
2671 }
2672
2673 /* popmh list18 */
2674 int
2675 OP_307F0 (void)
2676 {
2677 int i;
2678
2679 trace_input ("popmh", OP_PUSHPOP2, 0);
2680
2681 if (OP[3] & (1 << 19))
2682 {
2683 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
2684 {
2685 FEPSW = load_mem ( SP & ~ 3, 4);
2686 FEPC = load_mem ((SP + 4) & ~ 3, 4);
2687 }
2688 else
2689 {
2690 EIPSW = load_mem ( SP & ~ 3, 4);
2691 EIPC = load_mem ((SP + 4) & ~ 3, 4);
2692 }
2693
2694 SP += 8;
2695 }
2696
2697 /* Load the registers with lower number registers being retrieved from higher addresses. */
2698 for (i = 16; i--;)
2699 if ((OP[3] & (1 << type2_regs[ i ])))
2700 {
2701 State.regs[ i + 16 ] = load_mem (SP & ~ 3, 4);
2702 SP += 4;
2703 }
2704
2705 trace_output (OP_PUSHPOP2);
2706
2707 return 4;
2708 }
2709
2710 /* popml lsit18 */
2711 int
2712 OP_107F0 (void)
2713 {
2714 int i;
2715
2716 trace_input ("popml", OP_PUSHPOP3, 0);
2717
2718 if (OP[3] & (1 << 19))
2719 {
2720 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
2721 {
2722 FEPSW = load_mem ( SP & ~ 3, 4);
2723 FEPC = load_mem ((SP + 4) & ~ 3, 4);
2724 }
2725 else
2726 {
2727 EIPSW = load_mem ( SP & ~ 3, 4);
2728 EIPC = load_mem ((SP + 4) & ~ 3, 4);
2729 }
2730
2731 SP += 8;
2732 }
2733
2734 if (OP[3] & (1 << 3))
2735 {
2736 PSW = load_mem (SP & ~ 3, 4);
2737 SP += 4;
2738 }
2739
2740 /* Load the registers with lower number registers being retrieved from higher addresses. */
2741 for (i = 15; i--;)
2742 if ((OP[3] & (1 << type3_regs[ i ])))
2743 {
2744 State.regs[ i + 1 ] = load_mem (SP & ~ 3, 4);
2745 SP += 4;
2746 }
2747
2748 trace_output (OP_PUSHPOP2);
2749
2750 return 4;
2751 }
2752
2753 /* pushmh list18 */
2754 int
2755 OP_307E0 (void)
2756 {
2757 int i;
2758
2759 trace_input ("pushmh", OP_PUSHPOP2, 0);
2760
2761 /* Store the registers with lower number registers being placed at higher addresses. */
2762 for (i = 0; i < 16; i++)
2763 if ((OP[3] & (1 << type2_regs[ i ])))
2764 {
2765 SP -= 4;
2766 store_mem (SP & ~ 3, 4, State.regs[ i + 16 ]);
2767 }
2768
2769 if (OP[3] & (1 << 19))
2770 {
2771 SP -= 8;
2772
2773 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
2774 {
2775 store_mem ((SP + 4) & ~ 3, 4, FEPC);
2776 store_mem ( SP & ~ 3, 4, FEPSW);
2777 }
2778 else
2779 {
2780 store_mem ((SP + 4) & ~ 3, 4, EIPC);
2781 store_mem ( SP & ~ 3, 4, EIPSW);
2782 }
2783 }
2784
2785 trace_output (OP_PUSHPOP2);
2786
2787 return 4;
2788 }
2789
2790 /* V850E2R FPU functions */
2791 /*
2792 sim_fpu_status_invalid_snan = 1, -V--- (sim spec.)
2793 sim_fpu_status_invalid_qnan = 2, ----- (sim spec.)
2794 sim_fpu_status_invalid_isi = 4, (inf - inf) -V---
2795 sim_fpu_status_invalid_idi = 8, (inf / inf) -V---
2796 sim_fpu_status_invalid_zdz = 16, (0 / 0) -V---
2797 sim_fpu_status_invalid_imz = 32, (inf * 0) -V---
2798 sim_fpu_status_invalid_cvi = 64, convert to integer -V---
2799 sim_fpu_status_invalid_div0 = 128, (X / 0) --Z--
2800 sim_fpu_status_invalid_cmp = 256, compare ----- (sim spec.)
2801 sim_fpu_status_invalid_sqrt = 512, -V---
2802 sim_fpu_status_rounded = 1024, I----
2803 sim_fpu_status_inexact = 2048, I---- (sim spec.)
2804 sim_fpu_status_overflow = 4096, I--O-
2805 sim_fpu_status_underflow = 8192, I---U
2806 sim_fpu_status_denorm = 16384, ----U (sim spec.)
2807 */
2808
2809 void
2810 update_fpsr (SIM_DESC sd, sim_fpu_status status, unsigned int mask, unsigned int double_op_p)
2811 {
2812 unsigned int fpsr = FPSR & mask;
2813
2814 unsigned int flags = 0;
2815
2816 if (fpsr & FPSR_XEI
2817 && ((status & (sim_fpu_status_rounded
2818 | sim_fpu_status_overflow
2819 | sim_fpu_status_inexact))
2820 || (status & sim_fpu_status_underflow
2821 && (fpsr & (FPSR_XEU | FPSR_XEI)) == 0
2822 && fpsr & FPSR_FS)))
2823 {
2824 flags |= FPSR_XCI | FPSR_XPI;
2825 }
2826
2827 if (fpsr & FPSR_XEV
2828 && (status & (sim_fpu_status_invalid_isi
2829 | sim_fpu_status_invalid_imz
2830 | sim_fpu_status_invalid_zdz
2831 | sim_fpu_status_invalid_idi
2832 | sim_fpu_status_invalid_cvi
2833 | sim_fpu_status_invalid_sqrt
2834 | sim_fpu_status_invalid_snan)))
2835 {
2836 flags |= FPSR_XCV | FPSR_XPV;
2837 }
2838
2839 if (fpsr & FPSR_XEZ
2840 && (status & sim_fpu_status_invalid_div0))
2841 {
2842 flags |= FPSR_XCV | FPSR_XPV;
2843 }
2844
2845 if (fpsr & FPSR_XEO
2846 && (status & sim_fpu_status_overflow))
2847 {
2848 flags |= FPSR_XCO | FPSR_XPO;
2849 }
2850
2851 if (((fpsr & FPSR_XEU) || (fpsr & FPSR_FS) == 0)
2852 && (status & (sim_fpu_status_underflow
2853 | sim_fpu_status_denorm)))
2854 {
2855 flags |= FPSR_XCU | FPSR_XPU;
2856 }
2857
2858 if (flags)
2859 {
2860 FPSR &= ~FPSR_XC;
2861 FPSR |= flags;
2862
2863 SignalExceptionFPE (sd, double_op_p);
2864 }
2865 }
2866
2867 /* Exception. */
2868
2869 void
2870 SignalException (SIM_DESC sd)
2871 {
2872 if (MPM & MPM_AUE)
2873 {
2874 PSW = PSW & ~(PSW_NPV | PSW_DMP | PSW_IMP);
2875 }
2876 }
2877
2878 void
2879 SignalExceptionFPE (SIM_DESC sd, unsigned int double_op_p)
2880 {
2881 if (((PSW & (PSW_NP|PSW_ID)) == 0)
2882 || !(FPSR & (double_op_p ? FPSR_DEM : FPSR_SEM)))
2883 {
2884 EIPC = PC;
2885 EIPSW = PSW;
2886 EIIC = (FPSR & (double_op_p ? FPSR_DEM : FPSR_SEM))
2887 ? 0x71 : 0x72;
2888 PSW |= (PSW_EP | PSW_ID);
2889 PC = 0x70;
2890
2891 SignalException (sd);
2892 }
2893 }
2894
2895 void
2896 check_invalid_snan (SIM_DESC sd, sim_fpu_status status, unsigned int double_op_p)
2897 {
2898 if ((FPSR & FPSR_XEI)
2899 && (status & sim_fpu_status_invalid_snan))
2900 {
2901 FPSR &= ~FPSR_XC;
2902 FPSR |= FPSR_XCV;
2903 FPSR |= FPSR_XPV;
2904 SignalExceptionFPE (sd, double_op_p);
2905 }
2906 }
2907
2908 int
2909 v850_float_compare (SIM_DESC sd, int cmp, sim_fpu wop1, sim_fpu wop2, int double_op_p)
2910 {
2911 int result = -1;
2912
2913 if (sim_fpu_is_nan (&wop1) || sim_fpu_is_nan (&wop2))
2914 {
2915 if (cmp & 0x8)
2916 {
2917 if (FPSR & FPSR_XEV)
2918 {
2919 FPSR |= FPSR_XCV | FPSR_XPV;
2920 SignalExceptionFPE (sd, double_op_p);
2921 }
2922 }
2923
2924 switch (cmp)
2925 {
2926 case FPU_CMP_F:
2927 result = 0;
2928 break;
2929 case FPU_CMP_UN:
2930 result = 1;
2931 break;
2932 case FPU_CMP_EQ:
2933 result = 0;
2934 break;
2935 case FPU_CMP_UEQ:
2936 result = 1;
2937 break;
2938 case FPU_CMP_OLT:
2939 result = 0;
2940 break;
2941 case FPU_CMP_ULT:
2942 result = 1;
2943 break;
2944 case FPU_CMP_OLE:
2945 result = 0;
2946 break;
2947 case FPU_CMP_ULE:
2948 result = 1;
2949 break;
2950 case FPU_CMP_SF:
2951 result = 0;
2952 break;
2953 case FPU_CMP_NGLE:
2954 result = 1;
2955 break;
2956 case FPU_CMP_SEQ:
2957 result = 0;
2958 break;
2959 case FPU_CMP_NGL:
2960 result = 1;
2961 break;
2962 case FPU_CMP_LT:
2963 result = 0;
2964 break;
2965 case FPU_CMP_NGE:
2966 result = 1;
2967 break;
2968 case FPU_CMP_LE:
2969 result = 0;
2970 break;
2971 case FPU_CMP_NGT:
2972 result = 1;
2973 break;
2974 default:
2975 abort ();
2976 }
2977 }
2978 else if (sim_fpu_is_infinity (&wop1) && sim_fpu_is_infinity (&wop2)
2979 && sim_fpu_sign (&wop1) == sim_fpu_sign (&wop2))
2980 {
2981 switch (cmp)
2982 {
2983 case FPU_CMP_F:
2984 result = 0;
2985 break;
2986 case FPU_CMP_UN:
2987 result = 0;
2988 break;
2989 case FPU_CMP_EQ:
2990 result = 1;
2991 break;
2992 case FPU_CMP_UEQ:
2993 result = 1;
2994 break;
2995 case FPU_CMP_OLT:
2996 result = 0;
2997 break;
2998 case FPU_CMP_ULT:
2999 result = 0;
3000 break;
3001 case FPU_CMP_OLE:
3002 result = 1;
3003 break;
3004 case FPU_CMP_ULE:
3005 result = 1;
3006 break;
3007 case FPU_CMP_SF:
3008 result = 0;
3009 break;
3010 case FPU_CMP_NGLE:
3011 result = 0;
3012 break;
3013 case FPU_CMP_SEQ:
3014 result = 1;
3015 break;
3016 case FPU_CMP_NGL:
3017 result = 1;
3018 break;
3019 case FPU_CMP_LT:
3020 result = 0;
3021 break;
3022 case FPU_CMP_NGE:
3023 result = 0;
3024 break;
3025 case FPU_CMP_LE:
3026 result = 1;
3027 break;
3028 case FPU_CMP_NGT:
3029 result = 1;
3030 break;
3031 default:
3032 abort ();
3033 }
3034 }
3035 else
3036 {
3037 int gt = 0,lt = 0,eq = 0, status;
3038
3039 status = sim_fpu_cmp (&wop1, &wop2);
3040
3041 switch (status)
3042 {
3043 case SIM_FPU_IS_SNAN:
3044 case SIM_FPU_IS_QNAN:
3045 abort ();
3046 break;
3047
3048 case SIM_FPU_IS_NINF:
3049 lt = 1;
3050 break;
3051 case SIM_FPU_IS_PINF:
3052 gt = 1;
3053 break;
3054 case SIM_FPU_IS_NNUMBER:
3055 lt = 1;
3056 break;
3057 case SIM_FPU_IS_PNUMBER:
3058 gt = 1;
3059 break;
3060 case SIM_FPU_IS_NDENORM:
3061 lt = 1;
3062 break;
3063 case SIM_FPU_IS_PDENORM:
3064 gt = 1;
3065 break;
3066 case SIM_FPU_IS_NZERO:
3067 case SIM_FPU_IS_PZERO:
3068 eq = 1;
3069 break;
3070 }
3071
3072 switch (cmp)
3073 {
3074 case FPU_CMP_F:
3075 result = 0;
3076 break;
3077 case FPU_CMP_UN:
3078 result = 0;
3079 break;
3080 case FPU_CMP_EQ:
3081 result = eq;
3082 break;
3083 case FPU_CMP_UEQ:
3084 result = eq;
3085 break;
3086 case FPU_CMP_OLT:
3087 result = lt;
3088 break;
3089 case FPU_CMP_ULT:
3090 result = lt;
3091 break;
3092 case FPU_CMP_OLE:
3093 result = lt || eq;
3094 break;
3095 case FPU_CMP_ULE:
3096 result = lt || eq;
3097 break;
3098 case FPU_CMP_SF:
3099 result = 0;
3100 break;
3101 case FPU_CMP_NGLE:
3102 result = 0;
3103 break;
3104 case FPU_CMP_SEQ:
3105 result = eq;
3106 break;
3107 case FPU_CMP_NGL:
3108 result = eq;
3109 break;
3110 case FPU_CMP_LT:
3111 result = lt;
3112 break;
3113 case FPU_CMP_NGE:
3114 result = lt;
3115 break;
3116 case FPU_CMP_LE:
3117 result = lt || eq;
3118 break;
3119 case FPU_CMP_NGT:
3120 result = lt || eq;
3121 break;
3122 }
3123 }
3124
3125 ASSERT (result != -1);
3126 return result;
3127 }
3128
3129 void
3130 v850_div (SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p, unsigned int *op3p)
3131 {
3132 signed long int quotient;
3133 signed long int remainder;
3134 signed long int divide_by;
3135 signed long int divide_this;
3136 bfd_boolean overflow = FALSE;
3137
3138 /* Compute the result. */
3139 divide_by = (int32_t)op0;
3140 divide_this = (int32_t)op1;
3141
3142 if (divide_by == 0 || (divide_by == -1 && divide_this == (1 << 31)))
3143 {
3144 overflow = TRUE;
3145 divide_by = 1;
3146 }
3147
3148 quotient = divide_this / divide_by;
3149 remainder = divide_this % divide_by;
3150
3151 /* Set condition codes. */
3152 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
3153
3154 if (overflow) PSW |= PSW_OV;
3155 if (quotient == 0) PSW |= PSW_Z;
3156 if (quotient < 0) PSW |= PSW_S;
3157
3158 *op2p = quotient;
3159 *op3p = remainder;
3160 }
3161
3162 void
3163 v850_divu (SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p, unsigned int *op3p)
3164 {
3165 unsigned long int quotient;
3166 unsigned long int remainder;
3167 unsigned long int divide_by;
3168 unsigned long int divide_this;
3169 bfd_boolean overflow = FALSE;
3170
3171 /* Compute the result. */
3172
3173 divide_by = op0;
3174 divide_this = op1;
3175
3176 if (divide_by == 0)
3177 {
3178 overflow = TRUE;
3179 divide_by = 1;
3180 }
3181
3182 quotient = divide_this / divide_by;
3183 remainder = divide_this % divide_by;
3184
3185 /* Set condition codes. */
3186 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
3187
3188 if (overflow) PSW |= PSW_OV;
3189 if (quotient == 0) PSW |= PSW_Z;
3190 if (quotient & 0x80000000) PSW |= PSW_S;
3191
3192 *op2p = quotient;
3193 *op3p = remainder;
3194 }
3195
3196 void
3197 v850_sar (SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p)
3198 {
3199 unsigned int result, z, s, cy;
3200
3201 op0 &= 0x1f;
3202 result = (signed)op1 >> op0;
3203
3204 /* Compute the condition codes. */
3205 z = (result == 0);
3206 s = (result & 0x80000000);
3207 cy = (op1 & (1 << (op0 - 1)));
3208
3209 /* Store the result and condition codes. */
3210 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
3211 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
3212 | (cy ? PSW_CY : 0));
3213
3214 *op2p = result;
3215 }
3216
3217 void
3218 v850_shl (SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p)
3219 {
3220 unsigned int result, z, s, cy;
3221
3222 op0 &= 0x1f;
3223 result = op1 << op0;
3224
3225 /* Compute the condition codes. */
3226 z = (result == 0);
3227 s = (result & 0x80000000);
3228 cy = (op1 & (1 << (32 - op0)));
3229
3230 /* Store the result and condition codes. */
3231 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
3232 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
3233 | (cy ? PSW_CY : 0));
3234
3235 *op2p = result;
3236 }
3237
3238 void
3239 v850_rotl (SIM_DESC sd, unsigned int amount, unsigned int src, unsigned int * dest)
3240 {
3241 unsigned int result, z, s, cy;
3242
3243 amount &= 0x1f;
3244 result = src << amount;
3245 result |= src >> (32 - amount);
3246
3247 /* Compute the condition codes. */
3248 z = (result == 0);
3249 s = (result & 0x80000000);
3250 cy = ! (result & 1);
3251
3252 /* Store the result and condition codes. */
3253 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
3254 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
3255 | (cy ? PSW_CY : 0));
3256
3257 * dest = result;
3258 }
3259
3260 void
3261 v850_bins (SIM_DESC sd, unsigned int source, unsigned int lsb, unsigned int msb,
3262 unsigned int * dest)
3263 {
3264 unsigned int mask;
3265 unsigned int result, pos, width;
3266 unsigned int z, s;
3267
3268 pos = lsb;
3269 width = (msb - lsb) + 1;
3270
3271 /* A width of 32 exhibits undefined behavior on the shift. The easiest
3272 way to make this code safe is to just avoid that case and set the mask
3273 to the right value. */
3274 if (width >= 32)
3275 mask = 0xffffffff;
3276 else
3277 mask = ~ (-(1 << width));
3278
3279 source &= mask;
3280 mask <<= pos;
3281 result = (* dest) & ~ mask;
3282 result |= source << pos;
3283
3284 /* Compute the condition codes. */
3285 z = (result == 0);
3286 s = result & 0x80000000;
3287
3288 /* Store the result and condition codes. */
3289 PSW &= ~(PSW_Z | PSW_S | PSW_OV );
3290 PSW |= (z ? PSW_Z : 0) | (s ? PSW_S : 0);
3291
3292 * dest = result;
3293 }
3294
3295 void
3296 v850_shr (SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p)
3297 {
3298 unsigned int result, z, s, cy;
3299
3300 op0 &= 0x1f;
3301 result = op1 >> op0;
3302
3303 /* Compute the condition codes. */
3304 z = (result == 0);
3305 s = (result & 0x80000000);
3306 cy = (op1 & (1 << (op0 - 1)));
3307
3308 /* Store the result and condition codes. */
3309 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
3310 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
3311 | (cy ? PSW_CY : 0));
3312
3313 *op2p = result;
3314 }
3315
3316 void
3317 v850_satadd (SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p)
3318 {
3319 unsigned int result, z, s, cy, ov, sat;
3320
3321 result = op0 + op1;
3322
3323 /* Compute the condition codes. */
3324 z = (result == 0);
3325 s = (result & 0x80000000);
3326 cy = (result < op0 || result < op1);
3327 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
3328 && (op0 & 0x80000000) != (result & 0x80000000));
3329 sat = ov;
3330
3331 /* Store the result and condition codes. */
3332 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
3333 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
3334 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
3335 | (sat ? PSW_SAT : 0));
3336
3337 /* Handle saturated results. */
3338 if (sat && s)
3339 {
3340 result = 0x7fffffff;
3341 PSW &= ~PSW_S;
3342 }
3343 else if (sat)
3344 {
3345 result = 0x80000000;
3346 PSW |= PSW_S;
3347 }
3348
3349 *op2p = result;
3350 }
3351
3352 void
3353 v850_satsub (SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p)
3354 {
3355 unsigned int result, z, s, cy, ov, sat;
3356
3357 /* Compute the result. */
3358 result = op1 - op0;
3359
3360 /* Compute the condition codes. */
3361 z = (result == 0);
3362 s = (result & 0x80000000);
3363 cy = (op1 < op0);
3364 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
3365 && (op1 & 0x80000000) != (result & 0x80000000));
3366 sat = ov;
3367
3368 /* Store the result and condition codes. */
3369 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
3370 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
3371 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
3372 | (sat ? PSW_SAT : 0));
3373
3374 /* Handle saturated results. */
3375 if (sat && s)
3376 {
3377 result = 0x7fffffff;
3378 PSW &= ~PSW_S;
3379 }
3380 else if (sat)
3381 {
3382 result = 0x80000000;
3383 PSW |= PSW_S;
3384 }
3385
3386 *op2p = result;
3387 }
3388
3389 uint32_t
3390 load_data_mem (SIM_DESC sd,
3391 address_word addr,
3392 int len)
3393 {
3394 uint32_t data;
3395
3396 switch (len)
3397 {
3398 case 1:
3399 data = sim_core_read_unaligned_1 (STATE_CPU (sd, 0),
3400 PC, read_map, addr);
3401 break;
3402 case 2:
3403 data = sim_core_read_unaligned_2 (STATE_CPU (sd, 0),
3404 PC, read_map, addr);
3405 break;
3406 case 4:
3407 data = sim_core_read_unaligned_4 (STATE_CPU (sd, 0),
3408 PC, read_map, addr);
3409 break;
3410 default:
3411 abort ();
3412 }
3413 return data;
3414 }
3415
3416 void
3417 store_data_mem (SIM_DESC sd,
3418 address_word addr,
3419 int len,
3420 uint32_t data)
3421 {
3422 switch (len)
3423 {
3424 case 1:
3425 store_mem (addr, 1, data);
3426 break;
3427 case 2:
3428 store_mem (addr, 2, data);
3429 break;
3430 case 4:
3431 store_mem (addr, 4, data);
3432 break;
3433 default:
3434 abort ();
3435 }
3436 }
3437
3438 int
3439 mpu_load_mem_test (SIM_DESC sd, unsigned int addr, int size, int base_reg)
3440 {
3441 int result = 1;
3442
3443 if (PSW & PSW_DMP)
3444 {
3445 if (IPE0 && addr >= IPA2ADDR (IPA0L) && addr <= IPA2ADDR (IPA0L) && IPR0)
3446 {
3447 /* text area */
3448 }
3449 else if (IPE1 && addr >= IPA2ADDR (IPA1L) && addr <= IPA2ADDR (IPA1L) && IPR1)
3450 {
3451 /* text area */
3452 }
3453 else if (IPE2 && addr >= IPA2ADDR (IPA2L) && addr <= IPA2ADDR (IPA2L) && IPR2)
3454 {
3455 /* text area */
3456 }
3457 else if (IPE3 && addr >= IPA2ADDR (IPA3L) && addr <= IPA2ADDR (IPA3L) && IPR3)
3458 {
3459 /* text area */
3460 }
3461 else if (addr >= PPA2ADDR (PPA & ~PPM) && addr <= DPA2ADDR (PPA | PPM))
3462 {
3463 /* preifarallel area */
3464 }
3465 else if (addr >= PPA2ADDR (SPAL) && addr <= DPA2ADDR (SPAU))
3466 {
3467 /* stack area */
3468 }
3469 else if (DPE0 && addr >= DPA2ADDR (DPA0L) && addr <= DPA2ADDR (DPA0L) && DPR0
3470 && ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1))
3471 {
3472 /* data area */
3473 }
3474 else if (DPE1 && addr >= DPA2ADDR (DPA1L) && addr <= DPA2ADDR (DPA1L) && DPR1
3475 && ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1))
3476 {
3477 /* data area */
3478 }
3479 else if (DPE2 && addr >= DPA2ADDR (DPA2L) && addr <= DPA2ADDR (DPA2L) && DPR2
3480 && ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1))
3481 {
3482 /* data area */
3483 }
3484 else if (DPE3 && addr >= DPA2ADDR (DPA3L) && addr <= DPA2ADDR (DPA3L) && DPR3
3485 && ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1))
3486 {
3487 /* data area */
3488 }
3489 else
3490 {
3491 VMECR &= ~(VMECR_VMW | VMECR_VMX);
3492 VMECR |= VMECR_VMR;
3493 VMADR = addr;
3494 VMTID = TID;
3495 FEIC = 0x431;
3496
3497 PC = 0x30;
3498
3499 SignalException (sd);
3500 result = 0;
3501 }
3502 }
3503
3504 return result;
3505 }
3506
3507 int
3508 mpu_store_mem_test (SIM_DESC sd, unsigned int addr, int size, int base_reg)
3509 {
3510 int result = 1;
3511
3512 if (PSW & PSW_DMP)
3513 {
3514 if (addr >= PPA2ADDR (PPA & ~PPM) && addr <= DPA2ADDR (PPA | PPM))
3515 {
3516 /* preifarallel area */
3517 }
3518 else if (addr >= PPA2ADDR (SPAL) && addr <= DPA2ADDR (SPAU))
3519 {
3520 /* stack area */
3521 }
3522 else if (DPE0 && addr >= DPA2ADDR (DPA0L) && addr <= DPA2ADDR (DPA0L) && DPW0
3523 && ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1))
3524 {
3525 /* data area */
3526 }
3527 else if (DPE1 && addr >= DPA2ADDR (DPA1L) && addr <= DPA2ADDR (DPA1L) && DPW1
3528 && ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1))
3529 {
3530 /* data area */
3531 }
3532 else if (DPE2 && addr >= DPA2ADDR (DPA2L) && addr <= DPA2ADDR (DPA2L) && DPW2
3533 && ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1))
3534 {
3535 /* data area */
3536 }
3537 else if (DPE3 && addr >= DPA2ADDR (DPA3L) && addr <= DPA2ADDR (DPA3L) && DPW3
3538 && ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1))
3539 {
3540 /* data area */
3541 }
3542 else
3543 {
3544 if (addr >= PPA2ADDR (PPA & ~PPM) && addr <= DPA2ADDR (PPA | PPM))
3545 {
3546 FEIC = 0x432;
3547 VPTID = TID;
3548 VPADR = PC;
3549 #ifdef NOT_YET
3550 VIP_PP;
3551 VPECR;
3552 #endif
3553 }
3554 else
3555 {
3556 FEIC = 0x431;
3557 VMTID = TID;
3558 VMADR = VMECR;
3559 VMECR &= ~(VMECR_VMW | VMECR_VMX);
3560 VMECR |= VMECR_VMR;
3561 PC = 0x30;
3562 }
3563 result = 0;
3564 }
3565 }
3566
3567 return result;
3568 }
3569
The GNU Binutils are a collection of binary tools.