| blob | 0852b38ae4cf12eb4c573ed3a782918043817a38 |
1 /* 32-bit ELF support for ARM
2 Copyright (C) 1998-2022 Free Software Foundation, Inc.
4 This file is part of BFD, the Binary File Descriptor library.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 #include <limits.h>
34 /* Return the relocation section associated with NAME. HTAB is the
35 bfd's elf32_arm_link_hash_entry. */
36 #define RELOC_SECTION(HTAB, NAME) \
39 /* Return size of a relocation entry. HTAB is the bfd's
40 elf32_arm_link_hash_entry. */
41 #define RELOC_SIZE(HTAB) \
42 ((HTAB)->use_rel \
43 ? sizeof (Elf32_External_Rel) \
44 : sizeof (Elf32_External_Rela))
46 /* Return function to swap relocations in. HTAB is the bfd's
47 elf32_arm_link_hash_entry. */
48 #define SWAP_RELOC_IN(HTAB) \
49 ((HTAB)->use_rel \
50 ? bfd_elf32_swap_reloc_in \
51 : bfd_elf32_swap_reloca_in)
53 /* Return function to swap relocations out. HTAB is the bfd's
54 elf32_arm_link_hash_entry. */
55 #define SWAP_RELOC_OUT(HTAB) \
56 ((HTAB)->use_rel \
57 ? bfd_elf32_swap_reloc_out \
58 : bfd_elf32_swap_reloca_out)
60 #define elf_info_to_howto NULL
61 #define elf_info_to_howto_rel elf32_arm_info_to_howto
63 #define ARM_ELF_ABI_VERSION 0
64 #define ARM_ELF_OS_ABI_VERSION ELFOSABI_ARM
66 /* The Adjusted Place, as defined by AAELF. */
67 #define Pa(X) ((X) & 0xfffffffc)
74 /* Note: code such as elf32_arm_reloc_type_lookup expect to use e.g.
75 R_ARM_PC24 as an index into this, and find the R_ARM_PC24 HOWTO
76 in that slot. */
79 {
80 /* No relocation. */
109 /* 32 bit absolute */
124 /* standard 32bit pc-relative reloc */
139 /* 8 bit absolute - R_ARM_LDR_PC_G0 in AAELF */
154 /* 16 bit absolute */
169 /* 12 bit absolute */
198 /* 8 bit absolute */
297 /* BLX instruction for the ARM. */
312 /* BLX instruction for the Thumb. */
327 /* Dynamic TLS relocations. */
371 /* Relocs used in ARM Linux */
835 /* These are declared as 13-bit signed relocations because we can
836 address -4095 .. 4095(base) by altering ADDW to SUBW or vice
837 versa. */
894 /* Group relocations. */
1274 /* End of group relocations. */
1488 /* GNU extension to record C++ vtable member usage */
1503 /* GNU extension to record C++ vtable hierarchy */
1546 /* TLS relocations */
1659 /* 112-127 private relocations. */
1677 /* R_ARM_ME_TOO, obsolete. */
1747 /* Relocations for Armv8.1-M Mainline. */
1787 };
1789 /* 160 onwards: */
1791 {
1896 };
1898 /* 249-255 extended, currently unused, relocations: */
1900 {
1956 };
1960 {
1973 }
1975 static bool
1978 {
1983 {
1984 /* xgettext:c-format */
1989 }
1991 }
1993 struct elf32_arm_reloc_map
1994 {
1995 bfd_reloc_code_real_type bfd_reloc_val;
1997 };
1999 /* All entries in this list must also be present in elf32_arm_howto_table. */
2001 {
2102 };
2106 bfd_reloc_code_real_type code)
2107 {
2115 }
2120 {
2139 }
2141 /* Support for core dump NOTE sections. */
2143 static bool
2145 {
2150 {
2155 /* pr_cursig */
2158 /* pr_pid */
2161 /* pr_reg */
2166 }
2168 /* Make a ".reg/999" section. */
2171 }
2173 static bool
2175 {
2177 {
2188 }
2190 /* Note that for some reason, a spurious space is tacked
2191 onto the end of the args in some (at least one anyway)
2192 implementations, so strip it off if it exists. */
2193 {
2199 }
2202 }
2207 {
2209 {
2214 {
2221 #if GCC_VERSION == 8000 || GCC_VERSION == 8001
2222 DIAGNOSTIC_PUSH;
2223 /* GCC 8.0 and 8.1 warn about 80 equals destination size with
2224 -Wstringop-truncation:
2225 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85643
2226 */
2227 DIAGNOSTIC_IGNORE_STRINGOP_TRUNCATION;
2228 #endif
2230 #if GCC_VERSION == 8000 || GCC_VERSION == 8001
2231 DIAGNOSTIC_POP;
2232 #endif
2237 }
2240 {
2259 }
2260 }
2261 }
2263 #define TARGET_LITTLE_SYM arm_elf32_le_vec
2265 #define TARGET_BIG_SYM arm_elf32_be_vec
2268 #define elf_backend_grok_prstatus elf32_arm_nabi_grok_prstatus
2269 #define elf_backend_grok_psinfo elf32_arm_nabi_grok_psinfo
2270 #define elf_backend_write_core_note elf32_arm_nabi_write_core_note
2275 /* In lieu of proper flags, assume all EABIv4 or later objects are
2276 interworkable. */
2277 #define INTERWORK_FLAG(abfd) \
2278 (EF_ARM_EABI_VERSION (elf_elfheader (abfd)->e_flags) >= EF_ARM_EABI_VER4 \
2279 || (elf_elfheader (abfd)->e_flags & EF_ARM_INTERWORK) \
2280 || ((abfd)->flags & BFD_LINKER_CREATED))
2282 /* The linker script knows the section names for placement.
2283 The entry_names are used to do simple name mangling on the stubs.
2284 Given a function name, and its type, the stub can be found. The
2285 name can be changed. The only requirement is the %s be present. */
2307 /* The name of the dynamic interpreter. This is put in the .interp
2308 section. */
2311 /* FDPIC default stack size. */
2312 #define DEFAULT_STACK_SIZE 0x8000
2315 {
2319 };
2322 {
2330 + dl_tlsdesc_lazy_resolver(GOT) */
2332 };
2334 /* NOTE: [Thumb nop sequence]
2335 When adding code that transitions from Thumb to Arm the instruction that
2336 should be used for the alignment padding should be 0xe7fd (b .-2) instead of
2337 a nop for performance reasons. */
2339 /* ARM FDPIC PLT entry. */
2340 /* The last 5 words contain PLT lazy fragment code and data. */
2342 {
2353 };
2355 /* Thumb FDPIC PLT entry. */
2356 /* The last 5 words contain PLT lazy fragment code and data. */
2358 {
2369 };
2371 #ifdef FOUR_WORD_PLT
2373 /* The first entry in a procedure linkage table looks like
2374 this. It is set up so that any shared library function that is
2375 called before the relocation has been set up calls the dynamic
2376 linker first. */
2378 {
2383 };
2385 /* Subsequent entries in a procedure linkage table look like
2386 this. */
2388 {
2393 };
2397 /* The first entry in a procedure linkage table looks like
2398 this. It is set up so that any shared library function that is
2399 called before the relocation has been set up calls the dynamic
2400 linker first. */
2402 {
2408 };
2410 /* By default subsequent entries in a procedure linkage table look like
2411 this. Offsets that don't fit into 28 bits will cause link error. */
2413 {
2417 };
2419 /* When explicitly asked, we'll use this "long" entry format
2420 which can cope with arbitrary displacements. */
2422 {
2427 };
2433 /* The first entry in a procedure linkage table looks like this.
2434 It is set up so that any shared library function that is called before the
2435 relocation has been set up calls the dynamic linker first. */
2437 {
2438 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2439 an instruction maybe encoded to one or two array elements. */
2442 /* add lr, pc */
2445 };
2447 /* Subsequent entries in a procedure linkage table for thumb only target
2448 look like this. */
2450 {
2451 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2452 an instruction maybe encoded to one or two array elements. */
2457 /* b .-4 */
2458 };
2460 /* The format of the first entry in the procedure linkage table
2461 for a VxWorks executable. */
2463 {
2468 };
2470 /* The format of subsequent entries in a VxWorks executable. */
2472 {
2479 };
2481 /* The format of entries in a VxWorks shared library. */
2483 {
2490 };
2492 /* An initial stub used if the PLT entry is referenced from Thumb code. */
2493 #define PLT_THUMB_STUB_SIZE 4
2495 {
2498 };
2500 /* The first entry in a procedure linkage table looks like
2501 this. It is set up so that any shared library function that is
2502 called before the relocation has been set up calls the dynamic
2503 linker first. */
2505 {
2506 /* First bundle: */
2511 /* Second bundle: */
2516 /* Third bundle: */
2520 /* .Lplt_tail: */
2522 /* Fourth bundle: */
2527 };
2528 #define ARM_NACL_PLT_TAIL_OFFSET (11 * 4)
2530 /* Subsequent entries in a procedure linkage table look like this. */
2532 {
2537 };
2539 /* PR 28924:
2540 There was a bug due to too high values of THM_MAX_FWD_BRANCH_OFFSET and
2541 THM2_MAX_FWD_BRANCH_OFFSET. The first macro concerns the case when Thumb-2
2542 is not available, and second macro when Thumb-2 is available. Among other
2543 things, they affect the range of branches represented as BLX instructions
2544 in Encoding T2 defined in Section A8.8.25 of the ARM Architecture
2545 Reference Manual ARMv7-A and ARMv7-R edition issue C.d. Such branches are
2546 specified there to have a maximum forward offset that is a multiple of 4.
2547 Previously, the respective values defined here were multiples of 2 but not
2548 4 and they are included in comments for reference. */
2549 #define ARM_MAX_FWD_BRANCH_OFFSET ((((1 << 23) - 1) << 2) + 8)
2550 #define ARM_MAX_BWD_BRANCH_OFFSET ((-((1 << 23) << 2)) + 8)
2551 #define THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) - 4 + 4)
2552 /* #def THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) - 2 + 4) */
2553 #define THM_MAX_BWD_BRANCH_OFFSET (-(1 << 22) + 4)
2554 #define THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 4) + 4)
2555 /* #def THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 2) + 4) */
2556 #define THM2_MAX_BWD_BRANCH_OFFSET (-(1 << 24) + 4)
2557 #define THM2_MAX_FWD_COND_BRANCH_OFFSET (((1 << 20) -2) + 4)
2558 #define THM2_MAX_BWD_COND_BRANCH_OFFSET (-(1 << 20) + 4)
2560 enum stub_insn_type
2561 {
2563 THUMB32_TYPE,
2564 ARM_TYPE,
2565 DATA_TYPE
2566 };
2568 #define THUMB16_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 0}
2569 /* A bit of a hack. A Thumb conditional branch, in which the proper condition
2570 is inserted in arm_build_one_stub(). */
2571 #define THUMB16_BCOND_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 1}
2572 #define THUMB32_INSN(X) {(X), THUMB32_TYPE, R_ARM_NONE, 0}
2573 #define THUMB32_MOVT(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVT_ABS, 0}
2574 #define THUMB32_MOVW(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVW_ABS_NC, 0}
2575 #define THUMB32_B_INSN(X, Z) {(X), THUMB32_TYPE, R_ARM_THM_JUMP24, (Z)}
2576 #define ARM_INSN(X) {(X), ARM_TYPE, R_ARM_NONE, 0}
2577 #define ARM_REL_INSN(X, Z) {(X), ARM_TYPE, R_ARM_JUMP24, (Z)}
2578 #define DATA_WORD(X,Y,Z) {(X), DATA_TYPE, (Y), (Z)}
2581 {
2582 bfd_vma data;
2588 /* See note [Thumb nop sequence] when adding a veneer. */
2590 /* Arm/Thumb -> Arm/Thumb long branch stub. On V5T and above, use blx
2591 to reach the stub if necessary. */
2593 {
2596 };
2598 /* V4T Arm -> Thumb long branch stub. Used on V4T where blx is not
2599 available. */
2601 {
2605 };
2607 /* Thumb -> Thumb long branch stub. Used on M-profile architectures. */
2609 {
2617 };
2619 /* Thumb -> Thumb long branch stub in thumb2 encoding. Used on armv7. */
2621 {
2624 };
2626 /* Thumb -> Thumb long branch stub. Used for PureCode sections on Thumb2
2627 M-profile architectures. */
2629 {
2633 };
2635 /* V4T Thumb -> Thumb long branch stub. Using the stack is not
2636 allowed. */
2638 {
2644 };
2646 /* V4T Thumb -> ARM long branch stub. Used on V4T where blx is not
2647 available. */
2649 {
2654 };
2656 /* V4T Thumb -> ARM short branch stub. Shorter variant of the above
2657 one, when the destination is close enough. */
2659 {
2663 };
2665 /* ARM/Thumb -> ARM long branch stub, PIC. On V5T and above, use
2666 blx to reach the stub if necessary. */
2668 {
2672 };
2674 /* ARM/Thumb -> Thumb long branch stub, PIC. On V5T and above, use
2675 blx to reach the stub if necessary. We can not add into pc;
2676 it is not guaranteed to mode switch (different in ARMv6 and
2677 ARMv7). */
2679 {
2684 };
2686 /* V4T ARM -> ARM long branch stub, PIC. */
2688 {
2693 };
2695 /* V4T Thumb -> ARM long branch stub, PIC. */
2697 {
2703 };
2705 /* Thumb -> Thumb long branch stub, PIC. Used on M-profile
2706 architectures. */
2708 {
2716 };
2718 /* V4T Thumb -> Thumb long branch stub, PIC. Using the stack is not
2719 allowed. */
2721 {
2728 };
2730 /* Thumb2/ARM -> TLS trampoline. Lowest common denominator, which is a
2731 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2733 {
2737 };
2739 /* V4T Thumb -> TLS trampoline. lowest common denominator, which is a
2740 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2742 {
2748 };
2750 /* NaCl ARM -> ARM long branch stub. */
2752 {
2761 };
2763 /* NaCl ARM -> ARM long branch stub, PIC. */
2765 {
2774 };
2776 /* Stub used for transition to secure state (aka SG veneer). */
2778 {
2781 };
2784 /* Cortex-A8 erratum-workaround stubs. */
2786 /* Stub used for conditional branches (which may be beyond +/-1MB away, so we
2787 can't use a conditional branch to reach this stub). */
2790 {
2794 };
2796 /* Stub used for b.w and bl.w instructions. */
2799 {
2801 };
2804 {
2806 };
2808 /* Stub used for Thumb-2 blx.w instructions. We modified the original blx.w
2809 instruction (which switches to ARM mode) to point to this stub. Jump to the
2810 real destination using an ARM-mode branch. */
2813 {
2815 };
2817 /* For each section group there can be a specially created linker section
2818 to hold the stubs for that group. The name of the stub section is based
2819 upon the name of another section within that group with the suffix below
2820 applied.
2822 PR 13049: STUB_SUFFIX used to be ".stub", but this allowed the user to
2823 create what appeared to be a linker stub section when it actually
2824 contained user code/data. For example, consider this fragment:
2826 const char * stubborn_problems[] = { "np" };
2828 If this is compiled with "-fPIC -fdata-sections" then gcc produces a
2829 section called:
2831 .data.rel.local.stubborn_problems
2833 This then causes problems in arm32_arm_build_stubs() as it triggers:
2835 // Ignore non-stub sections.
2836 if (!strstr (stub_sec->name, STUB_SUFFIX))
2837 continue;
2839 And so the section would be ignored instead of being processed. Hence
2840 the change in definition of STUB_SUFFIX to a name that cannot be a valid
2841 C identifier. */
2844 /* One entry per long/short branch stub defined above. */
2845 #define DEF_STUBS \
2846 DEF_STUB (long_branch_any_any) \
2847 DEF_STUB (long_branch_v4t_arm_thumb) \
2848 DEF_STUB (long_branch_thumb_only) \
2849 DEF_STUB (long_branch_v4t_thumb_thumb) \
2850 DEF_STUB (long_branch_v4t_thumb_arm) \
2851 DEF_STUB (short_branch_v4t_thumb_arm) \
2852 DEF_STUB (long_branch_any_arm_pic) \
2853 DEF_STUB (long_branch_any_thumb_pic) \
2854 DEF_STUB (long_branch_v4t_thumb_thumb_pic) \
2855 DEF_STUB (long_branch_v4t_arm_thumb_pic) \
2856 DEF_STUB (long_branch_v4t_thumb_arm_pic) \
2857 DEF_STUB (long_branch_thumb_only_pic) \
2858 DEF_STUB (long_branch_any_tls_pic) \
2859 DEF_STUB (long_branch_v4t_thumb_tls_pic) \
2860 DEF_STUB (long_branch_arm_nacl) \
2861 DEF_STUB (long_branch_arm_nacl_pic) \
2862 DEF_STUB (cmse_branch_thumb_only) \
2863 DEF_STUB (a8_veneer_b_cond) \
2864 DEF_STUB (a8_veneer_b) \
2865 DEF_STUB (a8_veneer_bl) \
2866 DEF_STUB (a8_veneer_blx) \
2867 DEF_STUB (long_branch_thumb2_only) \
2868 DEF_STUB (long_branch_thumb2_only_pure)
2870 #define DEF_STUB(x) arm_stub_##x,
2871 enum elf32_arm_stub_type
2872 {
2873 arm_stub_none,
2874 DEF_STUBS
2875 max_stub_type
2876 };
2877 #undef DEF_STUB
2879 /* Note the first a8_veneer type. */
2883 {
2888 #define DEF_STUB(x) {elf32_arm_stub_##x, ARRAY_SIZE(elf32_arm_stub_##x)},
2890 {
2892 DEF_STUBS
2893 };
2895 struct elf32_arm_stub_hash_entry
2896 {
2897 /* Base hash table entry structure. */
2900 /* The stub section. */
2903 /* Offset within stub_sec of the beginning of this stub. */
2904 bfd_vma stub_offset;
2906 /* Given the symbol's value and its section we can determine its final
2907 value when building the stubs (so the stub knows where to jump). */
2908 bfd_vma target_value;
2911 /* Same as above but for the source of the branch to the stub. Used for
2912 Cortex-A8 erratum workaround to patch it to branch to the stub. As
2913 such, source section does not need to be recorded since Cortex-A8 erratum
2914 workaround stubs are only generated when both source and target are in the
2915 same section. */
2916 bfd_vma source_value;
2918 /* The instruction which caused this stub to be generated (only valid for
2919 Cortex-A8 erratum workaround stubs at present). */
2922 /* The stub type. */
2924 /* Its encoding size in bytes. */
2926 /* Its template. */
2928 /* The size of the template (number of entries). */
2931 /* The symbol table entry, if any, that this was derived from. */
2934 /* Type of branch. */
2937 /* Where this stub is being called from, or, in the case of combined
2938 stub sections, the first input section in the group. */
2941 /* The name for the local symbol at the start of this stub. The
2942 stub name in the hash table has to be unique; this does not, so
2943 it can be friendlier. */
2945 };
2947 /* Used to build a map of a section. This is required for mixed-endian
2948 code/data. */
2951 {
2952 bfd_vma vma;
2954 }
2955 elf32_arm_section_map;
2957 /* Information about a VFP11 erratum veneer, or a branch to such a veneer. */
2960 {
2961 VFP11_ERRATUM_BRANCH_TO_ARM_VENEER,
2962 VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER,
2963 VFP11_ERRATUM_ARM_VENEER,
2964 VFP11_ERRATUM_THUMB_VENEER
2965 }
2966 elf32_vfp11_erratum_type;
2969 {
2971 bfd_vma vma;
2972 union
2973 {
2974 struct
2975 {
2979 struct
2980 {
2985 elf32_vfp11_erratum_type type;
2986 }
2987 elf32_vfp11_erratum_list;
2989 /* Information about a STM32L4XX erratum veneer, or a branch to such a
2990 veneer. */
2992 {
2993 STM32L4XX_ERRATUM_BRANCH_TO_VENEER,
2994 STM32L4XX_ERRATUM_VENEER
2995 }
2996 elf32_stm32l4xx_erratum_type;
2999 {
3001 bfd_vma vma;
3002 union
3003 {
3004 struct
3005 {
3009 struct
3010 {
3015 elf32_stm32l4xx_erratum_type type;
3016 }
3017 elf32_stm32l4xx_erratum_list;
3020 {
3021 DELETE_EXIDX_ENTRY,
3022 INSERT_EXIDX_CANTUNWIND_AT_END
3023 }
3024 arm_unwind_edit_type;
3026 /* A (sorted) list of edits to apply to an unwind table. */
3028 {
3029 arm_unwind_edit_type type;
3030 /* Note: we sometimes want to insert an unwind entry corresponding to a
3031 section different from the one we're currently writing out, so record the
3032 (text) section this edit relates to here. */
3036 }
3037 arm_unwind_table_edit;
3040 {
3041 /* Information about mapping symbols. */
3046 /* Information about CPU errata. */
3052 /* Information about unwind tables. */
3053 union
3054 {
3055 /* Unwind info attached to a text section. */
3056 struct
3057 {
3061 /* Unwind info attached to an .ARM.exidx section. */
3062 struct
3063 {
3068 }
3069 _arm_elf_section_data;
3071 #define elf32_arm_section_data(sec) \
3072 ((_arm_elf_section_data *) elf_section_data (sec))
3074 /* A fix which might be required for Cortex-A8 Thumb-2 branch/TLB erratum.
3075 These fixes are subject to a relaxation procedure (in elf32_arm_size_stubs),
3076 so may be created multiple times: we use an array of these entries whilst
3077 relaxing which we can refresh easily, then create stubs for each potentially
3078 erratum-triggering instruction once we've settled on a solution. */
3080 struct a8_erratum_fix
3081 {
3084 bfd_vma offset;
3085 bfd_vma target_offset;
3090 };
3092 /* A table of relocs applied to branches which might trigger Cortex-A8
3093 erratum. */
3095 struct a8_erratum_reloc
3096 {
3097 bfd_vma from;
3098 bfd_vma destination;
3104 };
3106 /* The size of the thread control block. */
3107 #define TCB_SIZE 8
3109 /* ARM-specific information about a PLT entry, over and above the usual
3110 gotplt_union. */
3111 struct arm_plt_info
3112 {
3113 /* We reference count Thumb references to a PLT entry separately,
3114 so that we can emit the Thumb trampoline only if needed. */
3115 bfd_signed_vma thumb_refcount;
3117 /* Some references from Thumb code may be eliminated by BL->BLX
3118 conversion, so record them separately. */
3119 bfd_signed_vma maybe_thumb_refcount;
3121 /* How many of the recorded PLT accesses were from non-call relocations.
3122 This information is useful when deciding whether anything takes the
3123 address of an STT_GNU_IFUNC PLT. A value of 0 means that all
3124 non-call references to the function should resolve directly to the
3125 real runtime target. */
3128 /* Since PLT entries have variable size if the Thumb prologue is
3129 used, we need to record the index into .got.plt instead of
3130 recomputing it from the PLT offset. */
3131 bfd_signed_vma got_offset;
3132 };
3134 /* Information about an .iplt entry for a local STT_GNU_IFUNC symbol. */
3135 struct arm_local_iplt_info
3136 {
3137 /* The information that is usually found in the generic ELF part of
3138 the hash table entry. */
3141 /* The information that is usually found in the ARM-specific part of
3142 the hash table entry. */
3145 /* A list of all potential dynamic relocations against this symbol. */
3147 };
3149 /* Structure to handle FDPIC support for local functions. */
3150 struct fdpic_local
3151 {
3155 };
3157 struct elf_arm_obj_tdata
3158 {
3161 /* Zero to warn when linking objects with incompatible enum sizes. */
3164 /* Zero to warn when linking objects with incompatible wchar_t sizes. */
3167 /* The number of entries in each of the arrays in this strcuture.
3168 Used to avoid buffer overruns. */
3169 bfd_size_type num_entries;
3171 /* tls_type for each local got entry. */
3174 /* GOTPLT entries for TLS descriptors. */
3177 /* Information for local symbols that need entries in .iplt. */
3180 /* Maintains FDPIC counters and funcdesc info. */
3182 };
3184 #define elf_arm_tdata(bfd) \
3185 ((struct elf_arm_obj_tdata *) (bfd)->tdata.any)
3187 #define elf32_arm_num_entries(bfd) \
3188 (elf_arm_tdata (bfd)->num_entries)
3190 #define elf32_arm_local_got_tls_type(bfd) \
3191 (elf_arm_tdata (bfd)->local_got_tls_type)
3193 #define elf32_arm_local_tlsdesc_gotent(bfd) \
3194 (elf_arm_tdata (bfd)->local_tlsdesc_gotent)
3196 #define elf32_arm_local_iplt(bfd) \
3197 (elf_arm_tdata (bfd)->local_iplt)
3199 #define elf32_arm_local_fdpic_cnts(bfd) \
3200 (elf_arm_tdata (bfd)->local_fdpic_cnts)
3202 #define is_arm_elf(bfd) \
3203 (bfd_get_flavour (bfd) == bfd_target_elf_flavour \
3204 && elf_tdata (bfd) != NULL \
3205 && elf_object_id (bfd) == ARM_ELF_DATA)
3207 static bool
3209 {
3211 ARM_ELF_DATA);
3212 }
3214 #define elf32_arm_hash_entry(ent) ((struct elf32_arm_link_hash_entry *)(ent))
3216 /* Structure to handle FDPIC support for extern functions. */
3223 };
3225 /* Arm ELF linker hash entry. */
3226 struct elf32_arm_link_hash_entry
3227 {
3230 /* ARM-specific PLT information. */
3233 #define GOT_UNKNOWN 0
3234 #define GOT_NORMAL 1
3235 #define GOT_TLS_GD 2
3236 #define GOT_TLS_IE 4
3237 #define GOT_TLS_GDESC 8
3238 #define GOT_TLS_GD_ANY_P(type) ((type & GOT_TLS_GD) || (type & GOT_TLS_GDESC))
3241 /* True if the symbol's PLT entry is in .iplt rather than .plt. */
3246 /* Offset of the GOTPLT entry reserved for the TLS descriptor,
3247 starting at the end of the jump table. */
3248 bfd_vma tlsdesc_got;
3250 /* The symbol marking the real symbol location for exported thumb
3251 symbols with Arm stubs. */
3254 /* A pointer to the most recently used stub hash entry against this
3255 symbol. */
3258 /* Counter for FDPIC relocations against this symbol. */
3260 };
3262 /* Traverse an arm ELF linker hash table. */
3263 #define elf32_arm_link_hash_traverse(table, func, info) \
3264 (elf_link_hash_traverse \
3265 (&(table)->root, \
3266 (bool (*) (struct elf_link_hash_entry *, void *)) (func), \
3267 (info)))
3269 /* Get the ARM elf linker hash table from a link_info structure. */
3270 #define elf32_arm_hash_table(p) \
3271 ((is_elf_hash_table ((p)->hash) \
3272 && elf_hash_table_id (elf_hash_table (p)) == ARM_ELF_DATA) \
3273 ? (struct elf32_arm_link_hash_table *) (p)->hash : NULL)
3275 #define arm_stub_hash_lookup(table, string, create, copy) \
3276 ((struct elf32_arm_stub_hash_entry *) \
3277 bfd_hash_lookup ((table), (string), (create), (copy)))
3279 /* Array to keep track of which stub sections have been created, and
3280 information on stub grouping. */
3281 struct map_stub
3282 {
3283 /* This is the section to which stubs in the group will be
3284 attached. */
3286 /* The stub section. */
3288 };
3290 #define elf32_arm_compute_jump_table_size(htab) \
3291 ((htab)->next_tls_desc_index * 4)
3293 /* ARM ELF linker hash table. */
3294 struct elf32_arm_link_hash_table
3295 {
3296 /* The main hash table. */
3299 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
3300 bfd_size_type thumb_glue_size;
3302 /* The size in bytes of the section containing the ARM-to-Thumb glue. */
3303 bfd_size_type arm_glue_size;
3305 /* The size in bytes of section containing the ARMv4 BX veneers. */
3306 bfd_size_type bx_glue_size;
3308 /* Offsets of ARMv4 BX veneers. Bit1 set if present, and Bit0 set when
3309 veneer has been populated. */
3312 /* The size in bytes of the section containing glue for VFP11 erratum
3313 veneers. */
3314 bfd_size_type vfp11_erratum_glue_size;
3316 /* The size in bytes of the section containing glue for STM32L4XX erratum
3317 veneers. */
3318 bfd_size_type stm32l4xx_erratum_glue_size;
3320 /* A table of fix locations for Cortex-A8 Thumb-2 branch/TLB erratum. This
3321 holds Cortex-A8 erratum fix locations between elf32_arm_size_stubs() and
3322 elf32_arm_write_section(). */
3326 /* An arbitrary input BFD chosen to hold the glue sections. */
3329 /* Nonzero to output a BE8 image. */
3332 /* Zero if R_ARM_TARGET1 means R_ARM_ABS32.
3333 Nonzero if R_ARM_TARGET1 means R_ARM_REL32. */
3336 /* The relocation to use for R_ARM_TARGET2 relocations. */
3339 /* 0 = Ignore R_ARM_V4BX.
3340 1 = Convert BX to MOV PC.
3341 2 = Generate v4 interworing stubs. */
3344 /* Whether we should fix the Cortex-A8 Thumb-2 branch/TLB erratum. */
3347 /* Whether we should fix the ARM1176 BLX immediate issue. */
3350 /* Nonzero if the ARM/Thumb BLX instructions are available for use. */
3353 /* What sort of code sequences we should look for which may trigger the
3354 VFP11 denorm erratum. */
3355 bfd_arm_vfp11_fix vfp11_fix;
3357 /* Global counter for the number of fixes we have emitted. */
3360 /* What sort of code sequences we should look for which may trigger the
3361 STM32L4XX erratum. */
3362 bfd_arm_stm32l4xx_fix stm32l4xx_fix;
3364 /* Global counter for the number of fixes we have emitted. */
3367 /* Nonzero to force PIC branch veneers. */
3370 /* The number of bytes in the initial entry in the PLT. */
3371 bfd_size_type plt_header_size;
3373 /* The number of bytes in the subsequent PLT etries. */
3374 bfd_size_type plt_entry_size;
3376 /* True if the target uses REL relocations. */
3379 /* Nonzero if import library must be a secure gateway import library
3380 as per ARMv8-M Security Extensions. */
3383 /* The import library whose symbols' address must remain stable in
3384 the import library generated. */
3387 /* The index of the next unused R_ARM_TLS_DESC slot in .rel.plt. */
3388 bfd_vma next_tls_desc_index;
3390 /* How many R_ARM_TLS_DESC relocations were generated so far. */
3391 bfd_vma num_tls_desc;
3393 /* The (unloaded but important) VxWorks .rela.plt.unloaded section. */
3396 /* Offset in .plt section of tls_arm_trampoline. */
3397 bfd_vma tls_trampoline;
3399 /* Data for R_ARM_TLS_LDM32/R_ARM_TLS_LDM32_FDPIC relocations. */
3400 union
3401 {
3402 bfd_signed_vma refcount;
3403 bfd_vma offset;
3406 /* For convenience in allocate_dynrelocs. */
3409 /* The amount of space used by the reserved portion of the sgotplt
3410 section, plus whatever space is used by the jump slots. */
3411 bfd_vma sgotplt_jump_table_size;
3413 /* The stub hash table. */
3416 /* Linker stub bfd. */
3419 /* Linker call-backs. */
3424 /* Array to keep track of which stub sections have been created, and
3425 information on stub grouping. */
3428 /* Input stub section holding secure gateway veneers. */
3431 /* Offset in cmse_stub_sec where new SG veneers (not in input import library)
3432 start to be allocated. */
3433 bfd_vma new_cmse_stub_offset;
3435 /* Number of elements in stub_group. */
3438 /* Assorted information used by elf32_arm_size_stubs. */
3443 /* True if the target system uses FDPIC. */
3446 /* Fixup section. Used for FDPIC. */
3448 };
3450 /* Add an FDPIC read-only fixup. */
3451 static void
3453 {
3454 bfd_vma fixup_offset;
3459 }
3463 {
3464 #if GCC_VERSION >= 3004
3466 #else
3470 {
3474 }
3476 #endif
3477 }
3481 {
3482 #if GCC_VERSION >= 3004
3484 #else
3489 {
3491 sum++;
3493 }
3495 #endif
3496 }
3501 static void
3507 bfd_vma addr,
3508 bfd_vma dynreloc_value,
3509 bfd_vma seg)
3510 {
3512 {
3517 {
3519 Elf_Internal_Rela outrel;
3528 }
3529 else
3530 {
3544 }
3546 }
3547 }
3549 /* Create an entry in an ARM ELF linker hash table. */
3555 {
3559 /* Allocate the structure if it has not already been allocated by a
3560 subclass. */
3567 /* Call the allocation method of the superclass. */
3572 {
3589 }
3592 }
3594 /* Ensure that we have allocated bookkeeping structures for ABFD's local
3595 symbols. */
3597 static bool
3599 {
3601 {
3602 bfd_size_type num_syms;
3606 /* Whilst it might be tempting to allocate a single block of memory and
3607 then divide it up amoungst the arrays in the elf_arm_obj_tdata
3608 structure, this interferes with the work of memory checkers looking
3609 for buffer overruns. So allocate each array individually. */
3645 #if GCC_VERSION >= 3000
3654 #endif
3655 }
3657 }
3659 /* Return the .iplt information for local symbol R_SYMNDX, which belongs
3660 to input bfd ABFD. Create the information if it doesn't already exist.
3661 Return null if an allocation fails. */
3665 {
3677 }
3679 /* Try to obtain PLT information for the symbol with index R_SYMNDX
3680 in ABFD's symbol table. If the symbol is global, H points to its
3681 hash table entry, otherwise H is null.
3683 Return true if the symbol does have PLT information. When returning
3684 true, point *ROOT_PLT at the target-independent reference count/offset
3685 union and *ARM_PLT at the ARM-specific information. */
3687 static bool
3692 {
3699 {
3703 }
3718 }
3722 /* Return true if the PLT described by ARM_PLT requires a Thumb stub
3723 before it. */
3725 static bool
3728 {
3735 }
3737 /* Return a pointer to the head of the dynamic reloc list that should
3738 be used for local symbol ISYM, which is symbol number R_SYMNDX in
3739 ABFD's symbol table. Return null if an error occurs. */
3744 {
3746 {
3753 }
3754 else
3755 {
3756 /* Track dynamic relocs needed for local syms too.
3757 We really need local syms available to do this
3758 easily. Oh well. */
3768 }
3769 }
3771 /* Initialize an entry in the stub hash table. */
3777 {
3778 /* Allocate the structure if it has not already been allocated by a
3779 subclass. */
3781 {
3786 }
3788 /* Call the allocation method of the superclass. */
3791 {
3794 /* Initialize the local fields. */
3809 }
3812 }
3814 /* Create .got, .gotplt, and .rel(a).got sections in DYNOBJ, and set up
3815 shortcuts to them in our hash table. */
3817 static bool
3819 {
3829 /* Also create .rofixup. */
3831 {
3838 }
3841 }
3843 /* Create the .iplt, .rel(a).iplt and .igot.plt sections. */
3845 static bool
3847 {
3852 flagword flags;
3860 {
3867 }
3870 {
3878 }
3881 {
3887 }
3889 }
3891 /* Determine if we're dealing with a Thumb only architecture. */
3893 static bool
3895 {
3898 Tag_CPU_arch_profile);
3905 /* Force return logic to be reviewed for each new architecture. */
3917 }
3919 /* Determine if we're dealing with a Thumb-2 object. */
3921 static bool
3923 {
3926 Tag_THUMB_ISA_use);
3928 /* No use of thumb permitted, or a legacy thumb-1/2 definition. */
3932 /* Variant of thumb is described by the architecture tag. */
3935 /* Force return logic to be reviewed for each new architecture. */
3945 }
3947 /* Determine whether Thumb-2 BL instruction is available. */
3949 static bool
3951 {
3955 /* Force return logic to be reviewed for each new architecture. */
3958 /* Architecture was introduced after ARMv6T2 (eg. ARMv6-M). */
3961 }
3963 /* Create .plt, .rel(a).plt, .got, .got.plt, .rel(a).got, .dynbss, and
3964 .rel(a).bss sections in DYNOBJ, and set up shortcuts to them in our
3965 hash table. */
3967 static bool
3969 {
3983 {
3988 {
3990 htab->plt_entry_size
3992 }
3993 else
3994 {
3995 htab->plt_header_size
3997 htab->plt_entry_size
3999 }
4003 }
4004 else
4005 {
4006 /* PR ld/16017
4007 Test for thumb only architectures. Note - we cannot just call
4008 using_thumb_only() as the attributes in the output bfd have not been
4009 initialised at this point, so instead we use the input bfd. */
4014 {
4017 }
4019 }
4025 else
4027 }
4036 }
4038 /* Copy the extra info we tack onto an elf_link_hash_entry. */
4040 static void
4044 {
4051 {
4052 /* Copy over PLT info. */
4060 /* Copy FDPIC counters. */
4065 /* We should only allocate a function to .iplt once the final
4066 symbol information is known. */
4070 {
4073 }
4074 }
4077 }
4079 /* Destroy an ARM elf linker hash table. */
4081 static void
4083 {
4089 }
4091 /* Create an ARM elf linker hash table. */
4095 {
4104 elf32_arm_link_hash_newfunc,
4106 ARM_ELF_DATA))
4107 {
4110 }
4114 #ifdef FOUR_WORD_PLT
4117 #else
4120 #endif
4127 {
4130 }
4134 }
4136 /* Determine what kind of NOPs are available. */
4138 static bool
4140 {
4142 Tag_CPU_arch);
4144 /* Force return logic to be reviewed for each new architecture. */
4153 }
4155 static bool
4157 {
4159 {
4176 }
4177 }
4179 /* Determine the type of stub needed, if any, for a call. */
4181 static enum elf32_arm_stub_type
4188 bfd_vma destination,
4192 {
4193 bfd_vma location;
4194 bfd_signed_vma branch_offset;
4219 /* True for architectures that implement the thumb2 movw instruction. */
4222 /* Determine where the call point is. */
4229 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
4230 are considering a function call relocation. */
4236 /* For TLS call relocs, it is the caller's responsibility to provide
4237 the address of the appropriate trampoline. */
4244 {
4249 else
4252 {
4255 /* Note when dealing with PLT entries: the main PLT stub is in
4256 ARM mode, so if the branch is in Thumb mode, another
4257 Thumb->ARM stub will be inserted later just before the ARM
4258 PLT stub. If a long branch stub is needed, we'll add a
4259 Thumb->Arm one and branch directly to the ARM PLT entry.
4260 Here, we have to check if a pre-PLT Thumb->ARM stub
4261 is needed and if it will be close enough. */
4268 /* Thumb branch/call to PLT: it can become a branch to ARM
4269 or to Thumb. We must perform the same checks and
4270 corrections as in elf32_arm_final_link_relocate. */
4273 {
4277 {
4278 /* If the Thumb BLX instruction is available, convert
4279 the BL to a BLX instruction to call the ARM-mode
4280 PLT entry. */
4282 }
4283 else
4284 {
4286 /* Target the Thumb stub before the ARM PLT entry. */
4289 }
4290 }
4291 else
4292 {
4294 }
4295 }
4296 }
4297 /* Calls to STT_GNU_IFUNC symbols should go through a PLT. */
4304 {
4305 /* Handle cases where:
4306 - this call goes too far (different Thumb/Thumb2 max
4307 distance)
4308 - it's a Thumb->Arm call and blx is not available, or it's a
4309 Thumb->Arm branch (not bl). A stub is needed in this case,
4310 but only if this call is not through a PLT entry. Indeed,
4311 PLT stubs handle mode switching already. */
4315 || (thumb2_bl
4318 || (thumb2
4328 {
4329 /* If we need to insert a Thumb-Thumb long branch stub to a
4330 PLT, use one that branches directly to the ARM PLT
4331 stub. If we pretended we'd use the pre-PLT Thumb->ARM
4332 stub, undo this now. */
4334 {
4337 }
4340 {
4341 /* Thumb to thumb. */
4343 {
4345 _bfd_error_handler
4347 " section with SHF_ARM_PURECODE section"
4348 " attribute is only supported for M-profile"
4353 /* PIC stubs. */
4356 /* V5T and above. Stub starts with ARM code, so
4357 we must be able to switch mode before
4358 reaching it, which is only possible for 'bl'
4359 (ie R_ARM_THM_CALL relocation). */
4360 ? arm_stub_long_branch_any_thumb_pic
4361 /* On V4T, use Thumb code only. */
4364 /* non-PIC stubs. */
4367 /* V5T and above. */
4368 ? arm_stub_long_branch_any_any
4369 /* V4T. */
4371 }
4372 else
4373 {
4376 else
4377 {
4379 _bfd_error_handler
4381 " section with SHF_ARM_PURECODE section"
4382 " attribute is only supported for M-profile"
4387 /* PIC stub. */
4388 ? arm_stub_long_branch_thumb_only_pic
4389 /* non-PIC stub. */
4392 }
4393 }
4394 }
4395 else
4396 {
4398 _bfd_error_handler
4400 " section with SHF_ARM_PURECODE section"
4405 /* Thumb to arm. */
4409 {
4410 _bfd_error_handler
4414 }
4416 stub_type =
4418 /* PIC stubs. */
4420 /* TLS PIC stubs. */
4424 /* V5T PIC and above. */
4425 ? arm_stub_long_branch_any_arm_pic
4426 /* V4T PIC stub. */
4429 /* non-PIC stubs. */
4431 /* V5T and above. */
4432 ? arm_stub_long_branch_any_any
4433 /* V4T. */
4436 /* Handle v4t short branches. */
4441 }
4442 }
4443 }
4448 {
4450 _bfd_error_handler
4452 " section with SHF_ARM_PURECODE section"
4453 " attribute is only supported for M-profile"
4457 {
4458 /* Arm to thumb. */
4463 {
4464 _bfd_error_handler
4468 }
4470 /* We have an extra 2-bytes reach because of
4471 the mode change (bit 24 (H) of BLX encoding). */
4477 {
4479 /* PIC stubs. */
4481 /* V5T and above. */
4482 ? arm_stub_long_branch_any_thumb_pic
4483 /* V4T stub. */
4486 /* non-PIC stubs. */
4488 /* V5T and above. */
4489 ? arm_stub_long_branch_any_any
4490 /* V4T. */
4492 }
4493 }
4494 else
4495 {
4496 /* Arm to arm. */
4499 {
4500 stub_type =
4502 /* PIC stubs. */
4504 /* TLS PIC Stub. */
4505 ? arm_stub_long_branch_any_tls_pic
4507 ? arm_stub_long_branch_arm_nacl_pic
4509 /* non-PIC stubs. */
4511 ? arm_stub_long_branch_arm_nacl
4513 }
4514 }
4515 }
4517 /* If a stub is needed, record the actual destination type. */
4522 }
4524 /* Build a name for an entry in the stub hash table. */
4532 {
4534 bfd_size_type len;
4537 {
4546 }
4547 else
4548 {
4560 }
4563 }
4565 /* Look up an entry in the stub hash. Stub entries are cached because
4566 creating the stub name takes a bit of time. */
4575 {
4583 /* If the input section is the CMSE stubs one and it needs a long
4584 branch stub to reach it's final destination, give up with an
4585 error message: this is not supported. See PR ld/24709. */
4587 {
4593 CMSE_STUB_NAME,
4599 /* Exit, rather than leave incompletely processed
4600 relocations. */
4602 }
4604 /* If this input section is part of a group of sections sharing one
4605 stub section, then use the id of the first section in the group.
4606 Stub names need to include a section id, as there may well be
4607 more than one stub used to reach say, printf, and we need to
4608 distinguish between them. */
4616 {
4618 }
4619 else
4620 {
4633 }
4636 }
4638 /* Whether veneers of type STUB_TYPE require to be in a dedicated output
4639 section. */
4641 static bool
4643 {
4648 {
4654 }
4657 }
4659 /* Required alignment (as a power of 2) for the dedicated section holding
4660 veneers of type STUB_TYPE, or 0 if veneers of this type are interspersed
4661 with input sections. */
4663 static int
4664 arm_dedicated_stub_output_section_required_alignment
4666 {
4671 {
4672 /* Vectors of Secure Gateway veneers must be aligned on 32byte
4673 boundary. */
4680 }
4683 }
4685 /* Name of the dedicated output section to put veneers of type STUB_TYPE, or
4686 NULL if veneers of this type are interspersed with input sections. */
4690 {
4695 {
4702 }
4705 }
4707 /* If veneers of type STUB_TYPE should go in a dedicated output section,
4708 returns the address of the hash table field in HTAB holding a pointer to the
4709 corresponding input section. Otherwise, returns NULL. */
4714 {
4719 {
4726 }
4729 }
4731 /* Find or create a stub section to contain a stub of type STUB_TYPE. SECTION
4732 is the section that branch into veneer and can be NULL if stub should go in
4733 a dedicated output section. Returns a pointer to the stub section, and the
4734 section to which the stub section will be attached (in *LINK_SEC_P).
4735 LINK_SEC_P may be NULL. */
4741 {
4749 {
4759 {
4763 }
4764 }
4765 else
4766 {
4776 }
4779 {
4781 bfd_size_type len;
4793 align);
4800 }
4809 }
4811 /* Add a new stub entry to the stub hash. Not all fields of the new
4812 stub entry are initialised. */
4818 {
4824 stub_type);
4828 /* Enter this entry into the linker stub hash table. */
4832 {
4838 }
4845 }
4847 /* Store an Arm insn into an output section not processed by
4848 elf32_arm_write_section. */
4850 static void
4853 {
4856 else
4858 }
4860 /* Store a 16-bit Thumb insn into an output section not processed by
4861 elf32_arm_write_section. */
4863 static void
4866 {
4869 else
4871 }
4873 /* Store a Thumb2 insn into an output section not processed by
4874 elf32_arm_write_section. */
4876 static void
4879 {
4880 /* T2 instructions are 16-bit streamed. */
4882 {
4885 }
4886 else
4887 {
4890 }
4891 }
4893 /* If it's possible to change R_TYPE to a more efficient access
4894 model, return the new reloc type. */
4896 static unsigned
4899 {
4906 /* We do not support relaxations for Old TLS models. */
4908 {
4915 }
4918 }
4920 static bfd_reloc_status_type elf32_arm_final_link_relocate
4926 static unsigned int
4928 {
4930 {
4962 }
4963 }
4965 /* Returns whether stubs of type STUB_TYPE take over the symbol they are
4966 veneering (TRUE) or have their own symbol (FALSE). */
4968 static bool
4970 {
4975 {
4981 }
4984 }
4986 /* Returns the padding needed for the dedicated section used stubs of type
4987 STUB_TYPE. */
4989 static int
4991 {
4996 {
5002 }
5005 }
5007 /* If veneers of type STUB_TYPE should go in a dedicated output section,
5008 returns the address of the hash table field in HTAB holding the offset at
5009 which new veneers should be layed out in the stub section. */
5014 {
5016 {
5023 }
5024 }
5026 static bool
5029 {
5030 #define MAXRELOCS 3
5038 bfd_vma sym_value;
5048 /* Massage our args to the form they really have. */
5052 /* Fail if the target section could not be assigned to an output
5053 section. The user should fix his linker script. */
5068 /* We have to do less-strictly-aligned fixes last. */
5071 /* Assign a slot at the end of section if none assigned yet. */
5073 {
5076 }
5081 /* This is the address of the stub destination. */
5091 {
5093 {
5095 {
5098 {
5099 /* We've borrowed the reloc_addend field to mean we should
5100 insert a condition code into this (Thumb-1 branch)
5101 instruction. See THUMB16_BCOND_INSN. */
5104 }
5107 }
5117 {
5120 }
5127 /* Handle cases where the target is encoded within the
5128 instruction. */
5130 {
5133 }
5147 }
5148 }
5153 /* Stub size has already been computed in arm_size_one_stub. Check
5154 consistency. */
5157 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
5161 /* Assume non empty slots have at least one and at most MAXRELOCS entries
5162 to relocate in each stub. */
5163 removed_sg_veneer =
5168 {
5169 Elf_Internal_Rela rel;
5172 bfd_vma points_to =
5181 /* The first relocation in the elf32_arm_stub_a8_veneer_b_cond[]
5182 template should refer back to the instruction after the original
5183 branch. We use target_section as Cortex-A8 erratum workaround stubs
5184 are only generated when both source and target are in the same
5185 section. */
5197 }
5200 #undef MAXRELOCS
5201 }
5203 /* Calculate the template, template size and instruction size for a stub.
5204 Return value is the instruction size. */
5206 static unsigned int
5210 {
5225 {
5227 {
5241 }
5242 }
5245 }
5247 /* As above, but don't actually build the stub. Just bump offset so
5248 we know stub section sizes. */
5250 static bool
5253 {
5258 /* Massage our args to the form they really have. */
5267 /* Initialized to -1. Null size indicates an empty slot full of zeros. */
5269 {
5273 }
5275 /* Already accounted for. */
5283 }
5285 /* External entry points for sizing and building linker stubs. */
5287 /* Set up various things so that we can make a list of input sections
5288 for each output section included in the link. Returns -1 on error,
5289 0 when no stubs will be needed, and 1 on success. */
5291 int
5294 {
5306 /* Count the number of input BFDs and find the top input section id. */
5310 {
5315 {
5318 }
5319 }
5328 /* We can't use output_bfd->section_count here to find the top output
5329 section index as some sections may have been removed, and
5330 _bfd_strip_section_from_output doesn't renumber the indices. */
5334 {
5337 }
5346 /* For sections we aren't interested in, mark their entries with a
5347 value we can check later. */
5349 do
5356 {
5359 }
5362 }
5364 /* The linker repeatedly calls this function for each input section,
5365 in the order that input sections are linked into output sections.
5366 Build lists of input sections to determine groupings between which
5367 we may insert linker stubs. */
5369 void
5372 {
5379 {
5383 {
5384 /* Steal the link_sec pointer for our list. */
5385 #define PREV_SEC(sec) (htab->stub_group[(sec)->id].link_sec)
5386 /* This happens to make the list in reverse order,
5387 which we reverse later. */
5390 }
5391 }
5392 }
5394 /* See whether we can group stub sections together. Grouping stub
5395 sections may result in fewer stubs. More importantly, we need to
5396 put all .init* and .fini* stubs at the end of the .init or
5397 .fini output sections respectively, because glibc splits the
5398 _init and _fini functions into multiple parts. Putting a stub in
5399 the middle of a function is not a good idea. */
5401 static void
5403 bfd_size_type stub_group_size,
5405 {
5408 do
5409 {
5416 /* Reverse the list: we must avoid placing stubs at the
5417 beginning of the section because the beginning of the text
5418 section may be required for an interrupt vector in bare metal
5419 code. */
5420 #define NEXT_SEC PREV_SEC
5423 {
5424 /* Pop from tail. */
5428 /* Push on head. */
5431 }
5434 {
5438 bfd_vma end_of_next;
5442 {
5446 /* End of NEXT is too far from start, so stop. */
5448 /* Add NEXT to the group. */
5450 }
5452 /* OK, the size from the start to the start of CURR is less
5453 than stub_group_size and thus can be handled by one stub
5454 section. (Or the head section is itself larger than
5455 stub_group_size, in which case we may be toast.)
5456 We should really be keeping track of the total size of
5457 stubs added here, as stubs contribute to the final output
5458 section size. */
5459 do
5460 {
5462 /* Set up this stub group. */
5464 }
5467 /* But wait, there's more! Input sections up to stub_group_size
5468 bytes after the stub section can be handled by it too. */
5470 {
5474 {
5477 /* End of NEXT is too far from stubs, so stop. */
5479 /* Add NEXT to the stub group. */
5483 }
5484 }
5486 }
5487 }
5491 #undef PREV_SEC
5492 #undef NEXT_SEC
5493 }
5495 /* Comparison function for sorting/searching relocations relating to Cortex-A8
5496 erratum fix. */
5498 static int
5500 {
5508 else
5510 }
5515 /* Helper function to scan code for sequences which might trigger the Cortex-A8
5516 branch/TLB erratum. Fill in the table described by A8_FIXES_P,
5517 NUM_A8_FIXES_P, A8_FIX_TABLE_SIZE_P. Returns true if an error occurs, false
5518 otherwise. */
5520 static bool
5530 {
5543 {
5547 bfd_vma base_vma;
5566 {
5577 /* Span is entirely within a single 4KB region: skip scanning. */
5582 /* Scan for 32-bit Thumb-2 branches which span two 4K regions, where:
5584 * The opcode is BLX.W, BL.W, B.W, Bcc.W
5585 * The branch target is in the same 4KB region as the
5586 first half of the branch.
5587 * The instruction before the branch is a 32-bit
5588 length non-branch instruction. */
5590 {
5599 {
5600 /* Load the rest of the insn (in manual-friendly order). */
5603 /* Encoding T4: B<c>.W. */
5605 /* Encoding T1: BL<c>.W. */
5607 /* Encoding T2: BLX<c>.W. */
5609 /* Encoding T3: B<c>.W (not permitted in IT block). */
5612 }
5617 && insn_32bit
5618 && is_32bit_branch
5619 && last_was_32bit
5621 {
5625 bfd_vma target;
5637 {
5641 /* We don't care about the error returned from this
5642 function, only if there is glue or not. */
5649 /* Keep a simpler condition, for the sake of clarity. */
5655 {
5659 else
5661 }
5662 }
5664 /* Check if we have an offending branch instruction. */
5667 /* We've already made a stub for this instruction, e.g.
5668 it's a long branch or a Thumb->ARM stub. Assume that
5669 stub will suffice to work around the A8 erratum (see
5670 setting of always_after_branch above). */
5671 ;
5673 {
5682 }
5684 {
5704 }
5707 {
5710 /* The original instruction is a BL, but the target is
5711 an ARM instruction. If we were not making a stub,
5712 the BL would have been converted to a BLX. Use the
5713 BLX stub instead in that case. */
5716 {
5720 }
5721 /* Conversely, if the original instruction was
5722 BLX but the target is Thumb mode, use the BL
5723 stub. */
5726 {
5730 }
5735 /* If we found a relocation, use the proper destination,
5736 not the offset in the (unrelocated) instruction.
5737 Note this is always done if we switched the stub type
5738 above. */
5740 offset =
5743 /* If the stub will use a Thumb-mode branch to a
5744 PLT target, redirect it to the preceding Thumb
5745 entry point. */
5751 /* The BLX stub is ARM-mode code. Adjust the offset to
5752 take the different PC value (+8 instead of +4) into
5753 account. */
5758 {
5762 {
5768 }
5771 {
5772 /* If we're doing a subsequent scan,
5773 check if we've found the same fix as
5774 before, and try and reuse the stub
5775 name. */
5779 {
5783 }
5784 }
5787 {
5791 }
5804 num_a8_fixes++;
5805 }
5806 }
5807 }
5812 }
5813 }
5817 }
5824 }
5826 /* Create or update a stub entry depending on whether the stub can already be
5827 found in HTAB. The stub is identified by:
5828 - its type STUB_TYPE
5829 - its source branch (note that several can share the same stub) whose
5830 section and relocation (if any) are given by SECTION and IRELA
5831 respectively
5832 - its target symbol whose input section, hash, name, value and branch type
5833 are given in SYM_SEC, HASH, SYM_NAME, SYM_VALUE and BRANCH_TYPE
5834 respectively
5836 If found, the value of the stub's target symbol is updated from SYM_VALUE
5837 and *NEW_STUB is set to FALSE. Otherwise, *NEW_STUB is set to
5838 TRUE and the stub entry is initialized.
5840 Returns the stub that was created or updated, or NULL if an error
5841 occurred. */
5850 {
5862 else
5863 {
5868 /* Support for grouping stub sections. */
5871 /* Get the name of this stub. */
5873 stub_type);
5876 }
5880 /* The proper stub has already been created, just update its value. */
5882 {
5887 }
5891 {
5895 }
5905 else
5906 {
5913 {
5916 }
5918 /* For historical reasons, use the existing names for ARM-to-Thumb and
5919 Thumb-to-ARM stubs. */
5930 else
5932 }
5936 }
5938 /* Scan symbols in INPUT_BFD to identify secure entry functions needing a
5939 gateway veneer to transition from non secure to secure state and create them
5940 accordingly.
5942 "ARMv8-M Security Extensions: Requirements on Development Tools" document
5943 defines the conditions that govern Secure Gateway veneer creation for a
5944 given symbol <SYM> as follows:
5945 - it has function type
5946 - it has non local binding
5947 - a symbol named __acle_se_<SYM> (called special symbol) exists with the
5948 same type, binding and value as <SYM> (called normal symbol).
5949 An entry function can handle secure state transition itself in which case
5950 its special symbol would have a different value from the normal symbol.
5952 OUT_ATTR gives the output attributes, SYM_HASHES the symbol index to hash
5953 entry mapping while HTAB gives the name to hash entry mapping.
5954 *CMSE_STUB_CREATED is increased by the number of secure gateway veneer
5955 created.
5957 The return value gives whether a stub failed to be allocated. */
5959 static bool
5963 {
5971 bfd_vma sym_value;
5987 NULL);
5991 /* Scan symbols. */
5993 {
5997 {
6005 /* Special symbol with local binding. */
6007 }
6008 else
6009 {
6015 /* Special symbol has incorrect binding or type. */
6020 }
6023 {
6029 }
6032 {
6039 }
6045 /* No associated normal symbol or it is neither global nor weak. */
6050 {
6051 /* Initialize here to avoid warning about use of possibly
6052 uninitialized variable. */
6056 {
6057 /* Searching for a normal symbol with local binding. */
6059 {
6060 lsym_name =
6066 }
6067 }
6070 {
6071 _bfd_error_handler
6075 }
6076 else
6077 _bfd_error_handler
6082 }
6088 {
6089 _bfd_error_handler
6093 }
6097 /* If this section is a link-once section that will be discarded, then
6098 don't create any stubs. */
6100 {
6101 _bfd_error_handler
6104 }
6107 {
6108 _bfd_error_handler
6111 }
6116 stub_entry
6123 else
6124 {
6127 }
6128 }
6133 }
6135 /* Return TRUE iff a symbol identified by its linker HASH entry is a secure
6136 code entry function, ie can be called from non secure code without using a
6137 veneer. */
6139 static bool
6141 {
6145 file_ptr offset;
6148 /* Defined symbol of function type. */
6155 /* Read first instruction. */
6165 /* Starts by SG instruction. */
6167 }
6169 /* Output the name (in symbol table) of the veneer GEN_ENTRY if it is a new
6170 secure gateway veneers (ie. the veneers was not in the input import library)
6171 and there is no output import library (GEN_INFO->out_implib_bfd is NULL. */
6173 static bool
6175 {
6179 /* Massage our args to the form they really have. */
6193 }
6195 /* Set offset of each secure gateway veneers so that its address remain
6196 identical to the one in the input import library referred by
6197 HTAB->in_implib_bfd. A warning is issued for veneers that disappeared
6198 (present in input import library but absent from the executable being
6199 linked) or if new veneers appeared and there is no output import library
6200 (INFO->out_implib_bfd is NULL and *CMSE_STUB_CREATED is bigger than the
6201 number of secure gateway veneers found in the input import library.
6203 The function returns whether an error occurred. If no error occurred,
6204 *CMSE_STUB_CREATED gives the number of SG veneers created by both cmse_scan
6205 and this function and HTAB->new_cmse_stub_offset is set to the biggest
6206 veneer observed set for new veneers to be layed out after. */
6208 static bool
6212 {
6215 flagword flags;
6222 bfd_size_type cmse_stub_size;
6231 /* No input secure gateway import library. */
6237 {
6241 }
6243 /* Get symbol table size. */
6248 /* Read in the input secure gateway import library's symbol table. */
6255 {
6258 }
6261 cmse_stub_size =
6265 out_sec_name =
6267 stub_out_sec =
6272 /* Set addresses of veneers mentionned in input secure gateway import
6273 library's symbol table. */
6275 {
6286 {
6288 "symbol should be absolute, global and "
6293 }
6302 /* Stub entry should have been created by cmse_scan or the symbol be of
6303 a secure function callable from non secure code. */
6305 {
6308 _bfd_error_handler
6312 stub_entry
6319 else
6320 {
6322 new_cmse_stubs_created++;
6324 }
6327 }
6328 /* Symbol found is not callable from non secure code. */
6330 {
6332 {
6334 sym_name);
6336 }
6338 }
6339 else
6340 {
6341 /* Only stubs for SG veneers should have been created. */
6344 /* Check visibility hasn't changed. */
6347 _bfd_error_handler
6349 sym_name);
6352 }
6354 /* Size should match that of a SG veneer. */
6356 {
6360 }
6362 /* Previous veneer address is before current SG veneer section. */
6364 {
6365 /* Avoid offset underflow. */
6370 }
6372 /* Complain if stub offset not a multiple of stub size. */
6374 {
6375 _bfd_error_handler
6379 }
6384 new_cmse_stubs_created--;
6390 }
6393 {
6395 _bfd_error_handler
6399 }
6402 {
6403 _bfd_error_handler
6405 out_sec_name);
6407 }
6409 free_sym_buf:
6412 }
6414 /* Determine and set the size of the stub section for a final link.
6416 The basic idea here is to examine all the relocations looking for
6417 PC-relative calls to a target that is unreachable with a "bl"
6418 instruction. */
6420 bool
6424 bfd_signed_vma group_size,
6426 asection *,
6429 {
6433 bfd_size_type stub_group_size;
6445 {
6450 }
6452 /* Propagate mach to stub bfd, because it may not have been
6453 finalized when we created stub_bfd. */
6457 /* Stash our params away. */
6466 /* The Cortex-A8 erratum fix depends on stubs not being in the same 4K page
6467 as the first half of a 32-bit branch straddling two 4K pages. This is a
6468 crude way of enforcing that. */
6474 else
6478 {
6479 /* Default values. */
6480 /* Thumb branch range is +-4MB has to be used as the default
6481 maximum size (a given section can contain both ARM and Thumb
6482 code, so the worst case has to be taken into account).
6484 This value is 24K less than that, which allows for 2025
6485 12-byte stubs. If we exceed that, then we will fail to link.
6486 The user will have to relink with an explicit group size
6487 option. */
6489 }
6493 /* If we're applying the cortex A8 fix, we need to determine the
6494 program header size now, because we cannot change it later --
6495 that could alter section placements. Notice the A8 erratum fix
6496 ends up requiring the section addresses to remain unchanged
6497 modulo the page size. That's something we cannot represent
6498 inside BFD, and we don't want to force the section alignment to
6499 be the page size. */
6504 {
6516 {
6530 /* We'll need the symbol table in a second. */
6535 /* Limit scan of symbols to object file whose profile is
6536 Microcontroller to not hinder performance in the general case. */
6538 {
6548 }
6550 /* Walk over each section attached to the input bfd. */
6554 {
6557 /* If there aren't any relocs, then there's nothing more
6558 to do. */
6564 /* If this section is a link-once section that will be
6565 discarded, then don't create any stubs. */
6570 /* Get the relocs. */
6571 internal_relocs
6577 /* Now examine each relocation. */
6581 {
6584 bfd_vma sym_value;
6585 bfd_vma destination;
6596 {
6598 error_ret_free_internal:
6601 /* Fall through. */
6602 error_ret_free_local:
6606 }
6610 hash = elf32_arm_hash_entry
6614 /* Only look for stubs on branch instructions, or
6615 non-relaxed TLSCALL */
6629 : (elf32_arm_local_got_tls_type
6634 /* Now determine the call target, its name, value,
6635 section. */
6643 {
6644 /* A non-relaxed TLS call. The target is the
6645 plt-resident trampoline and nothing to do
6646 with the symbol. */
6653 }
6655 {
6656 /* It's a local symbol. */
6660 {
6661 local_syms
6664 local_syms
6670 }
6679 else
6680 sym_sec =
6684 /* This is an undefined symbol. It can never
6685 be resolved. */
6694 branch_type =
6696 sym_name
6700 }
6701 else
6702 {
6703 /* It's an external symbol. */
6711 {
6718 /* For a destination in a shared library,
6719 use the PLT stub as target address to
6720 decide whether a branch stub is
6721 needed. */
6726 {
6730 destination = (sym_value
6733 }
6738 }
6741 {
6742 /* For a shared library, use the PLT stub as
6743 target address to decide whether a long
6744 branch stub is needed.
6745 For absolute code, they cannot be handled. */
6753 {
6757 destination = (sym_value
6760 }
6761 else
6763 }
6764 else
6765 {
6768 }
6770 branch_type =
6773 }
6775 do
6776 {
6780 /* Determine what (if any) linker stub is needed. */
6788 /* We've either created a stub for this reloc already,
6789 or we are about to. */
6790 stub_entry =
6801 else
6803 }
6806 /* Look for relocations which might trigger Cortex-A8
6807 erratum. */
6813 {
6819 {
6820 /* Found a candidate. Note we haven't checked the
6821 destination is within 4K here: if we do so (and
6822 don't create an entry in a8_relocs) we can't tell
6823 that a branch should have been relocated when
6824 scanning later. */
6826 {
6832 }
6842 num_a8_relocs++;
6843 }
6844 }
6845 }
6847 /* We're done with the internal relocs, free them. */
6850 }
6853 {
6854 /* Sort relocs which might apply to Cortex-A8 erratum. */
6859 /* Scan for branches which might trigger Cortex-A8 erratum. */
6866 }
6870 {
6873 else
6875 }
6876 }
6889 /* OK, we've added some stubs. Find out the new size of the
6890 stub sections. */
6894 {
6895 /* Ignore non-stub sections. */
6900 }
6902 /* Add new SG veneers after those already in the input import
6903 library. */
6905 stub_type++)
6906 {
6918 }
6920 /* Compute stub section size, considering padding. */
6923 stub_type++)
6924 {
6930 /* Skip if no stub input section or no stub section padding
6931 required. */
6934 /* Stub section padding required but no dedicated section. */
6940 }
6942 /* Add Cortex-A8 erratum veneers to stub section sizes too. */
6945 {
6952 stub_sec->size
6954 NULL);
6955 }
6958 /* Ask the linker to do its stuff. */
6961 }
6963 /* Add stubs for Cortex-A8 erratum fixes now. */
6965 {
6967 {
6980 {
6984 }
7003 }
7005 /* Stash the Cortex-A8 erratum fix array for use later in
7006 elf32_arm_write_section(). */
7009 }
7010 else
7011 {
7014 }
7016 }
7018 /* Build all the stubs associated with the current output file. The
7019 stubs are kept in a hash table attached to the main linker hash
7020 table. We also set up the .plt entries for statically linked PIC
7021 functions here. This function is called via arm_elf_finish in the
7022 linker. */
7024 bool
7026 {
7039 {
7040 bfd_size_type size;
7042 /* Ignore non-stub sections. */
7046 /* Allocate memory to hold the linker stubs. Zeroing the stub sections
7047 must at least be done for stub section requiring padding and for SG
7048 veneers to ensure that a non secure code branching to a removed SG
7049 veneer causes an error. */
7056 }
7058 /* Add new SG veneers after those already in the input import library. */
7060 {
7072 }
7074 /* Build the stubs as directed by the stub hash table. */
7078 {
7079 /* Place the cortex a8 stubs last. */
7082 }
7085 }
7087 /* Locate the Thumb encoded calling stub for NAME. */
7093 {
7098 /* We need a pointer to the armelf specific hash table. */
7110 hash = elf_link_hash_lookup
7121 }
7123 /* Locate the ARM encoded calling stub for NAME. */
7129 {
7134 /* We need a pointer to the elfarm specific hash table. */
7145 myh = elf_link_hash_lookup
7156 }
7158 /* ARM->Thumb glue (static images):
7160 .arm
7161 __func_from_arm:
7162 ldr r12, __func_addr
7163 bx r12
7164 __func_addr:
7165 .word func @ behave as if you saw a ARM_32 reloc.
7167 (v5t static images)
7168 .arm
7169 __func_from_arm:
7170 ldr pc, __func_addr
7171 __func_addr:
7172 .word func @ behave as if you saw a ARM_32 reloc.
7174 (relocatable images)
7175 .arm
7176 __func_from_arm:
7177 ldr r12, __func_offset
7178 add r12, r12, pc
7179 bx r12
7180 __func_offset:
7181 .word func - . */
7183 #define ARM2THUMB_STATIC_GLUE_SIZE 12
7188 #define ARM2THUMB_V5_STATIC_GLUE_SIZE 8
7192 #define ARM2THUMB_PIC_GLUE_SIZE 16
7197 /* Thumb->ARM: Thumb->(non-interworking aware) ARM
7199 .thumb .thumb
7200 .align 2 .align 2
7201 __func_from_thumb: __func_from_thumb:
7202 bx pc push {r6, lr}
7203 nop ldr r6, __func_addr
7204 .arm mov lr, pc
7205 b func bx r6
7206 .arm
7207 ;; back_to_thumb
7208 ldmia r13! {r6, lr}
7209 bx lr
7210 __func_addr:
7211 .word func */
7213 #define THUMB2ARM_GLUE_SIZE 8
7218 #define VFP11_ERRATUM_VENEER_SIZE 8
7219 #define STM32L4XX_ERRATUM_LDM_VENEER_SIZE 16
7220 #define STM32L4XX_ERRATUM_VLDM_VENEER_SIZE 24
7222 #define ARM_BX_VENEER_SIZE 12
7227 #ifndef ELFARM_NABI_C_INCLUDED
7228 static void
7230 {
7235 {
7236 /* Do not include empty glue sections in the output. */
7238 {
7242 }
7244 }
7255 }
7257 bool
7259 {
7267 ARM2THUMB_GLUE_SECTION_NAME);
7271 THUMB2ARM_GLUE_SECTION_NAME);
7275 VFP11_ERRATUM_VENEER_SECTION_NAME);
7279 STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
7283 ARM_BX_GLUE_SECTION_NAME);
7286 }
7288 /* Allocate space and symbols for calling a Thumb function from Arm mode.
7289 returns the symbol identifying the stub. */
7294 {
7301 bfd_vma val;
7302 bfd_size_type size;
7308 s = bfd_get_linker_section
7319 myh = elf_link_hash_lookup
7323 {
7324 /* We've already seen this guy. */
7327 }
7329 /* The only trick here is using hash_table->arm_glue_size as the value.
7330 Even though the section isn't allocated yet, this is where we will be
7331 putting it. The +1 on the value marks that the stub has not been
7332 output yet - not that it is a Thumb function. */
7351 else
7358 }
7360 /* Allocate space for ARMv4 BX veneers. */
7362 static void
7364 {
7370 bfd_vma val;
7372 /* BX PC does not need a veneer. */
7380 /* Check if this veneer has already been allocated. */
7384 s = bfd_get_linker_section
7389 /* Add symbol for veneer. */
7396 myh = elf_link_hash_lookup
7414 }
7417 /* Add an entry to the code/data map for section SEC. */
7419 static void
7421 {
7426 {
7431 }
7436 {
7441 }
7444 {
7447 }
7448 }
7451 /* Record information about a VFP11 denorm-erratum veneer. Only ARM-mode
7452 veneers are handled for now. */
7454 static bfd_vma
7460 {
7466 bfd_vma val;
7474 s = bfd_get_linker_section
7488 myh = elf_link_hash_lookup
7503 /* Link veneer back to calling location. */
7517 /* A symbol for the return from the veneer. */
7521 myh = elf_link_hash_lookup
7538 /* Generate a mapping symbol for the veneer section, and explicitly add an
7539 entry for that symbol to the code/data map for the section. */
7541 {
7543 /* FIXME: Creates an ARM symbol. Thumb mode will need attention if it
7544 ever requires this erratum fix. */
7554 /* The elf32_arm_init_maps function only cares about symbols from input
7555 BFDs. We must make a note of this generated mapping symbol
7556 ourselves so that code byteswapping works properly in
7557 elf32_arm_write_section. */
7559 }
7565 /* The offset of the veneer. */
7567 }
7569 /* Record information about a STM32L4XX STM erratum veneer. Only THUMB-mode
7570 veneers need to be handled because used only in Cortex-M. */
7572 static bfd_vma
7578 bfd_size_type veneer_size)
7579 {
7585 bfd_vma val;
7593 s = bfd_get_linker_section
7607 myh = elf_link_hash_lookup
7622 /* Link veneer back to calling location. */
7636 /* A symbol for the return from the veneer. */
7640 myh = elf_link_hash_lookup
7657 /* Generate a mapping symbol for the veneer section, and explicitly add an
7658 entry for that symbol to the code/data map for the section. */
7660 {
7662 /* Creates a THUMB symbol since there is no other choice. */
7672 /* The elf32_arm_init_maps function only cares about symbols from input
7673 BFDs. We must make a note of this generated mapping symbol
7674 ourselves so that code byteswapping works properly in
7675 elf32_arm_write_section. */
7677 }
7683 /* The offset of the veneer. */
7685 }
7687 #define ARM_GLUE_SECTION_FLAGS \
7688 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_CODE \
7689 | SEC_READONLY | SEC_LINKER_CREATED)
7691 /* Create a fake section for use by the ARM backend of the linker. */
7693 static bool
7695 {
7700 /* Already made. */
7709 /* Set the gc mark to prevent the section from being removed by garbage
7710 collection, despite the fact that no relocs refer to this section. */
7714 }
7716 /* Set size of .plt entries. This function is called from the
7717 linker scripts in ld/emultempl/{armelf}.em. */
7719 void
7721 {
7723 }
7725 /* Add the glue sections to ABFD. This function is called from the
7726 linker scripts in ld/emultempl/{armelf}.em. */
7728 bool
7731 {
7737 /* If we are only performing a partial
7738 link do not bother adding the glue. */
7750 return addglue
7752 }
7754 /* Mark output sections of veneers needing a dedicated one with SEC_KEEP. This
7755 ensures they are not marked for deletion by
7756 strip_excluded_output_sections () when veneers are going to be created
7757 later. Not doing so would trigger assert on empty section size in
7758 lang_size_sections_1 (). */
7760 void
7762 {
7765 /* If we are only performing a partial
7766 link do not bother adding the glue. */
7771 {
7782 }
7783 }
7785 /* Select a BFD to be used to hold the sections used by the glue code.
7786 This function is called from the linker scripts in ld/emultempl/
7787 {armelf/pe}.em. */
7789 bool
7791 {
7794 /* If we are only performing a partial link
7795 do not bother getting a bfd to hold the glue. */
7799 /* Make sure we don't attach the glue sections to a dynamic object. */
7808 /* Save the bfd for later use. */
7812 }
7814 static void
7816 {
7820 Tag_CPU_arch);
7823 {
7826 }
7827 else
7828 {
7831 }
7832 }
7834 bool
7837 {
7846 /* If we are only performing a partial link do not bother
7847 to construct any glue. */
7851 /* Here we have a bfd that is to be included on the link. We have a
7852 hook to do reloc rummaging, before section sizes are nailed down. */
7859 {
7861 abfd);
7863 }
7865 /* PR 5398: If we have not decided to include any loadable sections in
7866 the output then we will not have a glue owner bfd. This is OK, it
7867 just means that there is nothing else for us to do here. */
7871 /* Rummage around all the relocs and map the glue vectors. */
7878 {
7887 /* Load the relocs. */
7888 internal_relocs
7896 {
7905 /* These are the only relocation types we care about. */
7910 /* Get the section contents if we haven't done so already. */
7912 {
7913 /* Get cached copy if it exists. */
7916 else
7917 {
7918 /* Go get them off disk. */
7921 }
7922 }
7925 {
7931 }
7933 /* If the relocation is not against a symbol it cannot concern us. */
7936 /* We don't care about local symbols. */
7940 /* This is an external symbol. */
7945 /* If the relocation is against a static symbol it must be within
7946 the current section and so cannot be a cross ARM/Thumb relocation. */
7950 /* If the call will go through a PLT entry then we do not need
7951 glue. */
7956 {
7958 /* This one is a call from arm code. We need to look up
7959 the target of the call. If it is a thumb target, we
7960 insert glue. */
7968 }
7969 }
7978 }
7982 error_return:
7989 }
7990 #endif
7993 /* Initialise maps of ARM/Thumb/data for input BFDs. */
7995 void
7997 {
8002 /* PR 7093: Make sure that we are dealing with an arm elf binary. */
8012 /* Obtain a buffer full of symbols for this BFD. The hdr->sh_info field
8013 should contain the number of local symbols, which should come before any
8014 global symbols. Mapping symbols are always local. */
8016 NULL);
8018 /* No internal symbols read? Skip this BFD. */
8023 {
8030 {
8035 BFD_ARM_SPECIAL_SYM_TYPE_MAP))
8037 }
8038 }
8039 }
8042 /* Auto-select enabling of Cortex-A8 erratum fix if the user didn't explicitly
8043 say what they wanted. */
8045 void
8047 {
8055 {
8056 /* Turn on Cortex-A8 erratum workaround for ARMv7-A. */
8061 else
8063 }
8064 }
8067 void
8069 {
8075 /* We assume that ARMv7+ does not need the VFP11 denorm erratum fix. */
8077 {
8079 {
8086 /* Give a warning, but do as the user requests anyway. */
8089 }
8090 }
8092 /* For earlier architectures, we might need the workaround, but do not
8093 enable it by default. If users is running with broken hardware, they
8094 must enable the erratum fix explicitly. */
8096 }
8098 void
8100 {
8107 /* We assume only Cortex-M4 may require the fix. */
8110 {
8112 /* Give a warning, but do as the user requests anyway. */
8113 _bfd_error_handler
8116 }
8117 }
8119 enum bfd_arm_vfp11_pipe
8120 {
8121 VFP11_FMAC,
8122 VFP11_LS,
8123 VFP11_DS,
8124 VFP11_BAD
8125 };
8127 /* Return a VFP register number. This is encoded as RX:X for single-precision
8128 registers, or X:RX for double-precision registers, where RX is the group of
8129 four bits in the instruction encoding and X is the single extension bit.
8130 RX and X fields are specified using their lowest (starting) bit. The return
8131 value is:
8133 0...31: single-precision registers s0...s31
8134 32...63: double-precision registers d0...d31.
8136 Although X should be zero for VFP11 (encoding d0...d15 only), we might
8137 encounter VFP3 instructions, so we allow the full range for DP registers. */
8139 static unsigned int
8142 {
8145 else
8147 }
8149 /* Set bits in *WMASK according to a register number REG as encoded by
8150 bfd_arm_vfp11_regno(). Ignore d16-d31. */
8152 static void
8154 {
8159 }
8161 /* Return TRUE if WMASK overwrites anything in REGS. */
8163 static bool
8165 {
8169 {
8182 }
8185 }
8187 /* In this function, we're interested in two things: finding input registers
8188 for VFP data-processing instructions, and finding the set of registers which
8189 arbitrary VFP instructions may write to. We use a 32-bit unsigned int to
8190 hold the written set, so FLDM etc. are easy to deal with (we're only
8191 interested in 32 SP registers or 16 dp registers, due to the VFP version
8192 implemented by the chip in question). DP registers are marked by setting
8193 both SP registers in the write mask). */
8195 static enum bfd_arm_vfp11_pipe
8198 {
8203 {
8213 {
8235 vfp_binop:
8243 {
8248 {
8262 /* These instructions will not bounce due to underflow. */
8268 /* fsqrt cannot underflow, but it can (perhaps) overwrite
8269 registers to cause the erratum in previous instructions. */
8275 {
8280 /* Only FCVTSD can underflow. */
8287 }
8292 }
8293 }
8298 }
8299 }
8300 /* Two-register transfer. */
8302 {
8306 {
8309 else
8310 {
8313 }
8314 }
8317 }
8319 {
8324 {
8331 {
8339 }
8349 }
8352 }
8353 /* Single-register transfer. Note L==0. */
8355 {
8360 {
8363 /* Mark fmdhr and fmdlr as writing to the whole of the DP
8364 destination register. I don't know if this is exactly right,
8365 but it is the conservative choice. */
8371 }
8374 }
8377 }
8383 /* Look for potentially-troublesome code sequences which might trigger the
8384 VFP11 denormal/antidependency erratum. See, e.g., the ARM1136 errata sheet
8385 (available from ARM) for details of the erratum. A short version is
8386 described in ld.texinfo. */
8388 bool
8390 {
8401 /* We use a simple FSM to match troublesome VFP11 instruction sequences.
8402 The states transition as follows:
8404 0 -> 1 (vector) or 0 -> 2 (scalar)
8405 A VFP FMAC-pipeline instruction has been seen. Fill
8406 regs[0]..regs[numregs-1] with its input operands. Remember this
8407 instruction in 'first_fmac'.
8409 1 -> 2
8410 Any instruction, except for a VFP instruction which overwrites
8411 regs[*].
8413 1 -> 3 [ -> 0 ] or
8414 2 -> 3 [ -> 0 ]
8415 A VFP instruction has been seen which overwrites any of regs[*].
8416 We must make a veneer! Reset state to 0 before examining next
8417 instruction.
8419 2 -> 0
8420 If we fail to match anything in state 2, reset to state 0 and reset
8421 the instruction pointer to the instruction after 'first_fmac'.
8423 If the VFP11 vector mode is in use, there must be at least two unrelated
8424 instructions between anti-dependent VFP11 instructions to properly avoid
8425 triggering the erratum, hence the use of the extra state 1. */
8427 /* If we are only performing a partial link do not bother
8428 to construct any glue. */
8432 /* Skip if this bfd does not correspond to an ELF image. */
8436 /* We should have chosen a fix type by the time we get here. */
8442 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8447 {
8451 /* If we don't have executable progbits, we're not interested in this
8452 section. Also skip if section is to be excluded. */
8472 elf32_arm_compare_mapping);
8475 {
8481 /* FIXME: Only ARM mode is supported at present. We may need to
8482 support Thumb-2 mode also at some point. */
8487 {
8502 {
8506 /* I'm assuming the VFP11 erratum can trigger with denorm
8507 operands on either the FMAC or the DS pipeline. This might
8508 lead to slightly overenthusiastic veneer insertion. */
8510 {
8514 }
8518 {
8521 other_regs,
8525 numregs))
8527 else
8529 }
8533 {
8536 other_regs,
8540 numregs))
8542 else
8543 {
8546 }
8547 }
8552 }
8555 {
8564 {
8571 }
8574 first_fmac);
8582 }
8585 }
8586 }
8591 }
8595 error_return:
8600 }
8602 /* Find virtual-memory addresses for VFP11 erratum veneers and return locations
8603 after sections have been laid out, using specially-named symbols. */
8605 void
8608 {
8616 /* Skip if this bfd does not correspond to an ELF image. */
8629 {
8634 {
8636 bfd_vma vma;
8639 {
8642 /* Find veneer symbol. */
8646 myh = elf_link_hash_lookup
8662 /* Find return location. */
8666 myh = elf_link_hash_lookup
8682 }
8683 }
8684 }
8687 }
8689 /* Find virtual-memory addresses for STM32L4XX erratum veneers and
8690 return locations after sections have been laid out, using
8691 specially-named symbols. */
8693 void
8696 {
8704 /* Skip if this bfd does not correspond to an ELF image. */
8717 {
8722 {
8724 bfd_vma vma;
8727 {
8729 /* Find veneer symbol. */
8733 myh = elf_link_hash_lookup
8748 /* Find return location. */
8752 myh = elf_link_hash_lookup
8768 }
8769 }
8770 }
8773 }
8777 {
8778 /* Encoding T2: LDM<c>.W <Rn>{!},<registers>
8779 1110 - 1000 - 10W1 - rrrr - PM (0) l - llll - llll - llll. */
8781 }
8785 {
8786 /* Encoding T1: LDMDB<c> <Rn>{!},<registers>
8787 1110 - 1001 - 00W1 - rrrr - PM (0) l - llll - llll - llll. */
8789 }
8793 {
8794 /* A6.5 Extension register load or store instruction
8795 A7.7.229
8796 We look for SP 32-bit and DP 64-bit registers.
8797 Encoding T1 VLDM{mode}<c> <Rn>{!}, <list>
8798 <list> is consecutive 64-bit registers
8799 1110 - 110P - UDW1 - rrrr - vvvv - 1011 - iiii - iiii
8800 Encoding T2 VLDM{mode}<c> <Rn>{!}, <list>
8801 <list> is consecutive 32-bit registers
8802 1110 - 110P - UDW1 - rrrr - vvvv - 1010 - iiii - iiii
8803 if P==0 && U==1 && W==1 && Rn=1101 VPOP
8804 if PUW=010 || PUW=011 || PUW=101 VLDM. */
8805 return
8810 /* (IA with !), includes VPOP (when reg number is SP). */
8812 /* (DB with !). */
8814 }
8816 /* STM STM32L4XX erratum : This function assumes that it receives an LDM or
8817 VLDM opcode and:
8818 - computes the number and the mode of memory accesses
8819 - decides if the replacement should be done:
8820 . replaces only if > 8-word accesses
8821 . or (testing purposes only) replaces all accesses. */
8823 static bool
8825 bfd_arm_stm32l4xx_fix stm32l4xx_fix)
8826 {
8829 /* The field encoding the register list is the same for both LDMIA
8830 and LDMDB encodings. */
8836 /* DEFAULT mode accounts for the real bug condition situation,
8837 ALL mode inserts stubs for each LDM/VLDM instruction (testing). */
8841 }
8843 /* Look for potentially-troublesome code sequences which might trigger
8844 the STM STM32L4XX erratum. */
8846 bool
8849 {
8857 /* If we are only performing a partial link do not bother
8858 to construct any glue. */
8862 /* Skip if this bfd does not correspond to an ELF image. */
8869 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8874 {
8878 /* If we don't have executable progbits, we're not interested in this
8879 section. Also skip if section is to be excluded. */
8899 elf32_arm_compare_mapping);
8902 {
8909 /* Only Thumb2 mode need be supported with this CM4 specific
8910 code, we should not encounter any arm mode eg span_type
8911 != 'a'. */
8916 {
8923 /* The first 16-bits of all 32-bit thumb2 instructions start
8924 with opcode[15..13]=0b111 and the encoded op1 can be anything
8925 except opcode[12..11]!=0b00.
8926 See 32-bit Thumb instruction encoding. */
8930 /* Compute the predicate that tells if the instruction
8931 is concerned by the IT block
8932 - Creates an error if there is a ldm that is not
8933 last in the IT block thus cannot be replaced
8934 - Otherwise we can create a branch at the end of the
8935 IT block, it will be controlled naturally by IT
8936 with the proper pseudo-predicate
8937 - So the only interesting predicate is the one that
8938 tells that we are not on the last item of an IT
8939 block. */
8944 {
8945 /* Load the rest of the insn (in manual-friendly order). */
8950 /* Veneers are created for (v)ldm depending on
8951 option flags and memory accesses conditions; but
8952 if the instruction is not the last instruction of
8953 an IT block, we cannot create a jump there, so we
8954 bail out. */
8956 && stm32l4xx_need_create_replacing_stub
8958 {
8960 {
8961 _bfd_error_handler
8962 /* xgettext:c-format */
8964 " in non-last IT block instruction:"
8965 " STM32L4XX veneer cannot be generated; "
8966 "use gcc option -mrestrict-it to generate"
8969 }
8970 else
8971 {
8974 bfd_zmalloc
8980 /* We create only thumb branches. */
8982 STM32L4XX_ERRATUM_BRANCH_TO_VENEER;
8983 record_stm32l4xx_erratum_veneer
8985 i,
8986 is_ldm ?
8987 STM32L4XX_ERRATUM_LDM_VENEER_SIZE:
8988 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
8992 }
8993 }
8994 }
8995 else
8996 {
8997 /* A7.7.37 IT p208
8998 IT blocks are only encoded in T1
8999 Encoding T1: IT{x{y{z}}} <firstcond>
9000 1 0 1 1 - 1 1 1 1 - firstcond - mask
9001 if mask = '0000' then see 'related encodings'
9002 We don't deal with UNPREDICTABLE, just ignore these.
9003 There can be no nested IT blocks so an IT block
9004 is naturally a new one for which it is worth
9005 computing its size. */
9008 /* If we have a new IT block we compute its size. */
9010 {
9011 /* Compute the number of instructions controlled
9012 by the IT block, it will be used to decide
9013 whether we are inside an IT block or not. */
9016 }
9017 }
9020 }
9021 }
9026 }
9030 error_return:
9035 }
9037 /* Set target relocation values needed during linking. */
9039 void
9043 {
9059 else
9060 {
9063 }
9070 else
9082 }
9084 /* Replace the target offset of a Thumb bl or b.w instruction. */
9086 static void
9088 {
9089 bfd_vma upper;
9090 bfd_vma lower;
9107 }
9109 /* Thumb code calling an ARM function. */
9111 static int
9119 bfd_vma offset,
9120 bfd_signed_vma addend,
9121 bfd_vma val,
9123 {
9125 bfd_vma my_offset;
9141 THUMB2ARM_GLUE_SECTION_NAME);
9148 {
9152 {
9153 _bfd_error_handler
9159 }
9170 ret_offset =
9171 /* Address of destination of the stub. */
9174 /* Offset from the start of the current section
9175 to the start of the stubs. */
9177 /* Offset of the start of this stub from the start of the stubs. */
9178 + my_offset
9179 /* Address of the start of the current section. */
9181 /* The branch instruction is 4 bytes into the stub. */
9183 /* ARM branches work from the pc of the instruction + 8. */
9189 }
9193 /* Now go back and fix up the original BL insn to point to here. */
9194 ret_offset =
9195 /* Address of where the stub is located. */
9197 /* Address of where the BL is located. */
9200 /* Addend in the relocation. */
9201 - addend
9202 /* Biassing for PC-relative addressing. */
9208 }
9210 /* Populate an Arm to Thumb stub. Returns the stub symbol. */
9218 bfd_vma val,
9221 {
9222 bfd_vma my_offset;
9238 {
9242 {
9243 _bfd_error_handler
9247 }
9255 {
9256 /* For relocatable objects we can't use absolute addresses,
9257 so construct the address from a relative offset. */
9258 /* TODO: If the offset is small it's probably worth
9259 constructing the address with adds. */
9266 /* Adjust the offset by 4 for the position of the add,
9267 and 8 for the pipeline offset. */
9274 }
9276 {
9280 /* It's a thumb address. Add the low order bit. */
9283 }
9284 else
9285 {
9292 /* It's a thumb address. Add the low order bit. */
9297 }
9298 }
9303 }
9305 /* Arm code calling a Thumb function. */
9307 static int
9315 bfd_vma offset,
9316 bfd_signed_vma addend,
9317 bfd_vma val,
9319 {
9321 bfd_vma my_offset;
9332 ARM2THUMB_GLUE_SECTION_NAME);
9346 /* Somehow these are both 4 too far, so subtract 8. */
9348 + my_offset
9360 }
9362 /* Populate Arm stub for an exported Thumb function. */
9364 static bool
9366 {
9373 bfd_vma val;
9377 /* Allocate stubs for exported Thumb functions on v4t. */
9386 ARM2THUMB_GLUE_SECTION_NAME);
9404 }
9406 /* Populate ARMv4 BX veneers. Returns the absolute adress of the veneer. */
9408 static bfd_vma
9410 {
9412 bfd_vma glue_addr;
9421 ARM_BX_GLUE_SECTION_NAME);
9431 {
9437 }
9440 }
9442 /* Generate Arm stubs for exported Thumb symbols. */
9443 static void
9446 {
9450 /* Ignore this if we are not called by the ELF backend linker. */
9457 /* If blx is available then exported Thumb symbols are OK and there is
9458 nothing to do. */
9463 link_info);
9464 }
9466 /* Reserve space for COUNT dynamic relocations in relocation selection
9467 SRELOC. */
9469 static void
9471 bfd_size_type count)
9472 {
9480 }
9482 /* Reserve space for COUNT R_ARM_IRELATIVE relocations. If the link is
9483 dynamic, the relocations should go in SRELOC, otherwise they should
9484 go in the special .rel.iplt section. */
9486 static void
9488 bfd_size_type count)
9489 {
9495 else
9496 {
9499 }
9500 }
9502 /* Add relocation REL to the end of relocation section SRELOC. */
9504 static void
9507 {
9522 }
9524 /* Allocate room for a PLT entry described by ROOT_PLT and ARM_PLT.
9525 IS_IPLT_ENTRY says whether the entry belongs to .iplt rather than
9526 to .plt. */
9528 static void
9533 {
9541 {
9545 /* NaCl uses a special first entry in .iplt too. */
9549 /* Allocate room for an R_ARM_IRELATIVE relocation in .rel.iplt. */
9551 }
9552 else
9553 {
9558 {
9559 /* Allocate room for R_ARM_FUNCDESC_VALUE. */
9560 /* For lazy binding, relocations will be put into .rel.plt, in
9561 .rel.got otherwise. */
9562 /* FIXME: today we don't support lazy binding so put it in .rel.got */
9565 else
9567 }
9568 else
9569 {
9570 /* Allocate room for an R_JUMP_SLOT relocation in .rel.plt. */
9572 }
9574 /* If this is the first .plt entry, make room for the special
9575 first entry. */
9580 }
9582 /* Allocate the PLT entry itself, including any leading Thumb stub. */
9588 /* We also need to make an entry in the .got.plt section, which
9589 will be placed in the .got section by the linker script. */
9592 else
9595 /* Function descriptor takes 64 bits in GOT. */
9597 else
9599 }
9601 static bfd_vma
9603 {
9605 }
9607 static bfd_vma
9609 {
9611 }
9613 /* Fill in a PLT entry and its associated GOT slot. If DYNINDX == -1,
9614 the entry lives in .iplt and resolves to (*SYM_VALUE)().
9615 Otherwise, DYNINDX is the index of the symbol in the dynamic
9616 symbol table and SYM_VALUE is undefined.
9618 ROOT_PLT points to the offset of the PLT entry from the start of its
9619 section (.iplt or .plt). ARM_PLT points to the symbol's ARM-specific
9620 bookkeeping information.
9622 Returns FALSE if there was a problem. */
9624 static bool
9629 {
9635 bfd_vma plt_index;
9636 Elf_Internal_Rela rel;
9637 bfd_vma got_header_size;
9641 /* Pick the appropriate sections and sizes. */
9643 {
9648 /* There are no reserved entries in .igot.plt, and no special
9649 first entry in .iplt. */
9651 }
9652 else
9653 {
9659 }
9668 /* Get the offset into the .(i)got.plt table of the entry that
9669 corresponds to this function. */
9672 /* Get the index in the procedure linkage table which
9673 corresponds to this symbol. This is the index of this symbol
9674 in all the symbols for which we are making plt entries.
9675 After the reserved .got.plt entries, all symbols appear in
9676 the same order as in .plt. */
9678 /* Function descriptor takes 8 bytes. */
9680 else
9683 /* Calculate the address of the GOT entry. */
9688 /* ...and the address of the PLT entry. */
9695 {
9697 bfd_vma val;
9700 {
9708 else
9710 }
9711 }
9713 {
9715 bfd_vma val;
9718 {
9728 else
9730 }
9735 /* Create the .rela.plt.unloaded R_ARM_ABS32 relocation
9736 referencing the GOT for this PLT entry. */
9743 /* Create the R_ARM_ABS32 relocation referencing the
9744 beginning of the PLT for this GOT entry. */
9749 }
9751 {
9752 /* Calculate the displacement between the PLT slot and the
9753 common tail that's part of the special initial PLT slot. */
9754 int32_t tail_displacement
9764 /* Calculate the displacement between the PLT slot and the entry
9765 in the GOT. The offset accounts for the value produced by
9766 adding to pc in the penultimate instruction of the PLT stub. */
9767 got_displacement = (got_address
9770 /* NaCl does not support interworking at all. */
9788 }
9790 {
9792 ? elf32_arm_fdpic_thumb_plt_entry
9795 /* Fill-up Thumb stub if needed. */
9797 {
9802 }
9803 /* As we are using 32 bit instructions even for the Thumb
9804 version, we have to use 'put_arm_insn' instead of
9805 'put_thumb_insn'. */
9813 {
9814 /* funcdesc_value_reloc_offset. */
9822 }
9823 }
9825 {
9826 /* PR ld/16017: Generate thumb only PLT entries. */
9828 {
9829 /* FIXME: We ought to be able to generate thumb-1 PLT
9830 instructions... */
9832 output_bfd);
9834 }
9836 /* Calculate the displacement between the PLT slot and the entry in
9837 the GOT. The 12-byte offset accounts for the value produced by
9838 adding to pc in the 3rd instruction of the PLT stub. */
9841 /* As we are using 32 bit instructions we have to use 'put_arm_insn'
9842 instead of 'put_thumb_insn'. */
9863 }
9864 else
9865 {
9866 /* Calculate the displacement between the PLT slot and the
9867 entry in the GOT. The eight-byte offset accounts for the
9868 value produced by adding to pc in the first instruction
9869 of the PLT stub. */
9873 {
9878 }
9881 {
9896 #ifdef FOUR_WORD_PLT
9898 #endif
9899 }
9900 else
9901 {
9918 }
9919 }
9921 /* Fill in the entry in the .rel(a).(i)plt section. */
9925 {
9926 /* .igot.plt entries use IRELATIVE relocations against SYM_VALUE.
9927 The dynamic linker or static executable then calls SYM_VALUE
9928 to determine the correct run-time value of the .igot.plt entry. */
9931 }
9932 else
9933 {
9934 /* For FDPIC we will have to resolve a R_ARM_FUNCDESC_VALUE
9935 used by PLT entry. */
9937 {
9940 }
9941 else
9942 {
9947 /* PR ld/16017
9948 When thumb only we need to set the LSB for any address that
9949 will be used with an interworking branch instruction. */
9952 }
9953 }
9955 /* Fill in the entry in the global offset table. */
9960 {
9961 /* Setup initial funcdesc value. */
9962 /* FIXME: we don't support lazy binding because there is a
9963 race condition between both words getting written and
9964 some other thread attempting to read them. The ARM
9965 architecture does not have an atomic 64 bit load/store
9966 instruction that could be used to prevent it; it is
9967 recommended that threaded FDPIC applications run with the
9968 LD_BIND_NOW environment variable set. */
9973 }
9977 else
9978 {
9980 {
9981 /* For FDPIC we put PLT relocationss into .rel.got when not
9982 lazy binding otherwise we put them in .rel.plt. For now,
9983 we don't support lazy binding so put it in .rel.got. */
9986 else
9988 }
9989 else
9990 {
9993 }
9994 }
9997 }
9999 /* Some relocations map to different relocations depending on the
10000 target. Return the real relocation. */
10002 static int
10005 {
10007 {
10011 else
10019 }
10020 }
10022 /* Return the base VMA address which should be subtracted from real addresses
10023 when resolving @dtpoff relocation.
10024 This is PT_TLS segment p_vaddr. */
10026 static bfd_vma
10028 {
10029 /* If tls_sec is NULL, we should have signalled an error already. */
10033 }
10035 /* Return the relocation value for @tpoff relocation
10036 if STT_TLS virtual address is ADDRESS. */
10038 static bfd_vma
10040 {
10042 bfd_vma base;
10044 /* If tls_sec is NULL, we should have signalled an error already. */
10049 }
10051 /* Perform an R_ARM_ABS12 relocation on the field pointed to by DATA.
10052 VALUE is the relocation value. */
10054 static bfd_reloc_status_type
10056 {
10063 }
10065 /* Handle TLS relaxations. Relaxing is possible for symbols that use
10066 R_ARM_GOTDESC, R_ARM_{,THM_}TLS_CALL or
10067 R_ARM_{,THM_}TLS_DESCSEQ relocations, during a static link.
10069 Return bfd_reloc_ok if we're done, bfd_reloc_continue if the caller
10070 is to then call final_link_relocate. Return other values in the
10071 case of error.
10073 FIXME:When --emit-relocs is in effect, we'll emit relocs describing
10074 the pre-relaxed code. It would be nice if the relocs were updated
10075 to match the optimization. */
10077 static bfd_reloc_status_type
10081 {
10085 {
10092 else
10093 {
10097 else
10099 }
10104 /* Thumb insn. */
10107 {
10109 /* nop */
10111 }
10113 {
10115 /* nop */
10117 else
10118 /* ldr rx,[ry] */
10120 }
10122 {
10124 /* nop */
10126 else
10127 /* mov r0, rx */
10130 }
10131 else
10132 {
10134 /* It's a 32 bit instruction, fetch the rest of it for
10135 error generation. */
10138 _bfd_error_handler
10139 /* xgettext:c-format */
10145 }
10149 /* arm insn. */
10152 {
10154 /* mov rx, ry */
10157 }
10159 {
10161 /* nop */
10163 else
10164 /* ldr rx,[ry] */
10167 }
10169 {
10171 /* nop */
10173 else
10174 /* mov r0, rx */
10177 }
10178 else
10179 {
10180 _bfd_error_handler
10181 /* xgettext:c-format */
10187 }
10191 /* GD->IE relaxation, turn the instruction into 'nop' or
10192 'ldr r0, [pc,r0]' */
10198 /* GD->IE relaxation. */
10200 /* add r0,pc; ldr r0, [r0] */
10203 /* nop.w */
10205 else
10206 /* nop; nop */
10212 }
10214 }
10216 /* For a given value of n, calculate the value of G_n as required to
10217 deal with group relocations. We return it in the form of an
10218 encoded constant-and-rotation, together with the final residual. If n is
10219 specified as less than zero, then final_residual is filled with the
10220 input value and no further action is performed. */
10222 static bfd_vma
10224 {
10226 bfd_vma g_n;
10231 {
10234 /* Calculate which part of the value to mask. */
10237 else
10238 {
10241 /* Determine the most significant bit in the residual and
10242 align the resulting value to a 2-bit boundary. */
10247 /* The desired shift is now (msb - 6), or zero, whichever
10248 is the greater. */
10252 }
10254 /* Calculate g_n in 32-bit as well as encoded constant+rotation form. */
10259 /* Calculate the residual for the next time around. */
10261 }
10266 }
10268 /* Given an ARM instruction, determine whether it is an ADD or a SUB.
10269 Returns 1 if it is an ADD, -1 if it is a SUB, and 0 otherwise. */
10271 static int
10273 {
10283 }
10285 /* Perform a relocation as part of a final link. */
10287 static bfd_reloc_status_type
10294 bfd_vma value,
10303 {
10313 bfd_vma addend;
10314 bfd_signed_vma signed_addend;
10316 bfd_vma dynreloc_value;
10321 bfd_vma plt_offset;
10322 bfd_vma gotplt_offset;
10333 /* Some relocation types map to different relocations depending on the
10334 target. We pick the right one here. */
10337 /* It is possible to have linker relaxations on some TLS access
10338 models. Update our information here. */
10351 else
10357 {
10358 bfd_vma sign;
10361 {
10366 }
10367 /* Note: the addend and signed_addend calculated here are
10368 incorrect for any split field. */
10374 }
10375 else
10378 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
10379 are resolving a function call relocation. */
10386 /* Record the symbol information that should be used in dynamic
10387 relocations. */
10393 /* Find out whether the symbol has a PLT. Set ST_VALUE, BRANCH_TYPE and
10394 VALUE appropriately for relocations that we resolve at link time. */
10399 {
10404 {
10408 /* Populate .iplt entries here, because not all of them will
10409 be seen by finish_dynamic_symbol. The lower bit is set if
10410 we have already populated the entry. */
10412 plt_offset--;
10413 else
10414 {
10418 else
10420 }
10422 /* Static relocations always resolve to the .iplt entry. */
10429 /* If there are non-call relocations that resolve to the .iplt
10430 entry, then all dynamic ones must too. */
10432 {
10435 }
10436 }
10437 else
10438 /* We populate the .plt entry in finish_dynamic_symbol. */
10440 }
10441 else
10442 {
10446 }
10452 {
10454 /* We don't need to find a value for this symbol. It's just a
10455 marker. */
10462 /* Fall through. */
10474 /* Handle relocations which should use the PLT entry. ABS32/REL32
10475 will use the symbol's value, which may point to a PLT entry, but we
10476 don't need to handle that here. If we created a PLT entry, all
10477 branches in this object should go to it, except if the PLT is too
10478 far away, in which case a long branch stub should be inserted. */
10485 {
10486 /* If we've created a .plt section, and assigned a PLT entry
10487 to this function, it must either be a STT_GNU_IFUNC reference
10488 or not be known to bind locally. In other cases, we should
10489 have cleared the PLT entry by now. */
10499 }
10501 /* When generating a shared object or relocatable executable, these
10502 relocations are copied into the output file to be resolved at
10503 run time. */
10524 {
10525 Elf_Internal_Rela outrel;
10531 {
10537 _bfd_error_handler
10542 }
10547 {
10553 }
10578 else
10579 {
10582 /* This symbol is local, or marked to become local. */
10585 /* On SVR4-ish systems, the dynamic loader cannot
10586 relocate the text and data segments independently,
10587 so the symbol does not matter. */
10590 /* We have an STT_GNU_IFUNC symbol that doesn't resolve
10591 to the .iplt entry. Instead, every non-call reference
10592 must use an R_ARM_IRELATIVE relocation to obtain the
10593 correct run-time address. */
10597 else
10601 else
10603 }
10607 else
10610 /* If this reloc is against an external symbol, we do not want to
10611 fiddle with the addend. Otherwise, we need to include the symbol
10612 value so that it becomes an addend for the dynamic reloc. */
10619 }
10621 {
10630 {
10634 {
10635 /* Check for Arm calling Arm function. */
10636 /* FIXME: Should we translate the instruction into a BL
10637 instruction instead ? */
10639 _bfd_error_handler
10644 }
10646 {
10647 /* Check for Arm calling Thumb function. */
10649 {
10654 error_message))
10656 else
10658 }
10659 }
10661 /* Check if a stub has to be inserted because the
10662 destination is too far or we are changing mode. */
10666 {
10677 {
10678 /* The target is out of reach, so redirect the
10679 branch to the local stub for this function. */
10683 stub_type);
10684 {
10692 }
10693 }
10694 else
10695 {
10696 /* If the call goes through a PLT entry, make sure to
10697 check distance to the right destination address. */
10699 {
10704 /* The PLT entry is in ARM mode, regardless of the
10705 target function. */
10707 }
10708 }
10709 }
10711 /* The ARM ELF ABI says that this reloc is computed as: S - P + A
10712 where:
10713 S is the address of the symbol in the relocation.
10714 P is address of the instruction being relocated.
10715 A is the addend (extracted from the instruction) in bytes.
10717 S is held in 'value'.
10718 P is the base address of the section containing the
10719 instruction plus the offset of the reloc into that
10720 section, ie:
10721 (input_section->output_section->vma +
10722 input_section->output_offset +
10723 rel->r_offset).
10724 A is the addend, converted into bytes, ie:
10725 (signed_addend * 4)
10727 Note: None of these operations have knowledge of the pipeline
10728 size of the processor, thus it is up to the assembler to
10729 encode this information into the addend. */
10738 /* A branch to an undefined weak symbol is turned into a jump to
10739 the next instruction unless a PLT entry will be created.
10740 Do the same for local undefined symbols (but not for STN_UNDEF).
10741 The jump to the next instruction is optimized as a NOP depending
10742 on the architecture. */
10746 {
10751 else
10753 }
10754 else
10755 {
10756 /* Perform a signed range check. */
10767 {
10768 /* Set the H bit in the BLX instruction. */
10770 {
10773 else
10775 }
10777 /* Select the correct instruction (BL or BLX). */
10778 /* Only if we are not handling a BL to a stub. In this
10779 case, mode switching is performed by the stub. */
10783 {
10786 }
10787 }
10788 }
10789 }
10821 {
10822 /* Check for overflow. */
10825 }
10831 }
10839 /* There is no way to tell whether the user intended to use a signed or
10840 unsigned addend. When checking for overflow we accept either,
10841 as specified by the AAELF. */
10851 /* See comment for R_ARM_ABS8. */
10859 /* Support ldr and str instructions for the thumb. */
10861 {
10862 /* Need to refetch addend. */
10864 /* ??? Need to determine shift amount from operand size. */
10866 }
10869 /* ??? Isn't value unsigned? */
10873 /* ??? Value needs to be properly shifted into place first. */
10879 /* Corresponds to: addw.w reg, pc, #offset (and similarly for subw). */
10880 {
10881 bfd_vma insn;
10882 bfd_signed_vma relocation;
10888 {
10893 }
10900 /* PR 21523: Use an absolute value. The user of this reloc will
10901 have already selected an ADD or SUB insn appropriately. */
10907 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
10921 }
10924 /* PR 10073: This reloc is not generated by the GNU toolchain,
10925 but it is supported for compatibility with third party libraries
10926 generated by other compilers, specifically the ARM/IAR. */
10927 {
10928 bfd_vma insn;
10929 bfd_signed_vma relocation;
10943 /* We do not check for overflow of this reloc. Although strictly
10944 speaking this is incorrect, it appears to be necessary in order
10945 to work with IAR generated relocs. Since GCC and GAS do not
10946 generate R_ARM_THM_PC8 relocs, the lack of a check should not be
10947 a problem for them. */
10955 }
10958 /* Corresponds to: ldr.w reg, [pc, #offset]. */
10959 {
10960 bfd_vma insn;
10961 bfd_signed_vma relocation;
10967 {
10971 }
10991 }
10996 /* Thumb BL (branch long instruction). */
10997 {
10998 bfd_vma relocation;
10999 bfd_vma reloc_sign;
11003 bfd_signed_vma reloc_signed_max;
11004 bfd_signed_vma reloc_signed_min;
11005 bfd_vma check;
11006 bfd_signed_vma signed_check;
11011 /* A branch to an undefined weak symbol is turned into a jump to
11012 the next instruction unless a PLT entry will be created.
11013 The jump to the next instruction is optimized as a NOP.W for
11014 Thumb-2 enabled architectures. */
11017 {
11019 {
11022 }
11023 else
11024 {
11027 }
11029 }
11031 /* Fetch the addend. We use the Thumb-2 encoding (backwards compatible
11032 with Thumb-1) involving the J1 and J2 bits. */
11034 {
11044 /* Sign extend. */
11048 }
11051 {
11052 /* Check for Thumb to Thumb call. */
11053 /* FIXME: Should we translate the instruction into a BL
11054 instruction instead ? */
11056 _bfd_error_handler
11061 }
11062 else
11063 {
11064 /* If it is not a call to Thumb, assume call to Arm.
11065 If it is a call relative to a section name, then it is not a
11066 function call at all, but rather a long jump. Calls through
11067 the PLT do not require stubs. */
11069 {
11071 {
11072 /* Convert BL to BLX. */
11074 }
11077 {
11081 error_message))
11083 else
11085 }
11086 }
11090 {
11091 /* Make sure this is a BL. */
11093 }
11094 }
11098 {
11099 /* Check if a stub has to be inserted because the destination
11100 is too far. */
11112 {
11113 /* The target is out of reach or we are changing modes, so
11114 redirect the branch to the local stub for this
11115 function. */
11119 stub_type);
11121 {
11128 }
11130 /* If this call becomes a call to Arm, force BLX. */
11132 {
11137 }
11138 }
11139 }
11141 /* Handle calls via the PLT. */
11143 {
11151 {
11152 /* If the Thumb BLX instruction is available, convert
11153 the BL to a BLX instruction to call the ARM-mode
11154 PLT entry. */
11157 }
11158 else
11159 {
11161 /* Target the Thumb stub before the ARM PLT entry. */
11164 }
11166 }
11176 /* If this is a signed value, the rightshift just dropped
11177 leading 1 bits (assuming twos complement). */
11180 else
11183 /* Calculate the permissable maximum and minimum values for
11184 this relocation according to whether we're relocating for
11185 Thumb-2 or not. */
11192 /* Assumes two's complement. */
11197 /* For a BLX instruction, make sure that the relocation is rounded up
11198 to a word boundary. This follows the semantics of the instruction
11199 which specifies that bit 1 of the target address will come from bit
11200 1 of the base address. */
11203 /* Put RELOCATION back into the insn. Assumes two's complement.
11204 We use the Thumb-2 encoding, which is safe even if dealing with
11205 a Thumb-1 instruction by virtue of our overflow check above. */
11215 /* Put the relocated value back in the object file: */
11220 }
11224 /* Thumb32 conditional branch instruction. */
11225 {
11226 bfd_vma relocation;
11232 bfd_signed_vma signed_check;
11237 /* Need to refetch the addend, reconstruct the top three bits,
11238 and squish the two 11 bit pieces together. */
11240 {
11254 }
11256 /* Handle calls via the PLT. */
11258 {
11262 /* Target the Thumb stub before the ARM PLT entry. */
11265 }
11274 {
11278 stub_type);
11280 {
11284 }
11285 }
11296 /* Put RELOCATION back into the insn. */
11297 {
11306 }
11308 /* Put the relocated value back in the object file: */
11313 }
11318 /* Thumb B (branch) instruction). */
11319 {
11320 bfd_signed_vma relocation;
11323 bfd_signed_vma signed_check;
11325 /* CZB cannot jump backward. */
11327 {
11331 }
11344 else
11350 /* Assumes two's complement. */
11355 }
11360 {
11361 bfd_vma insn;
11362 bfd_vma relocation;
11366 {
11367 /* Extract the addend. */
11370 }
11380 }
11388 /* Relocation is relative to the start of the
11389 global offset table. */
11395 /* If we are addressing a Thumb function, we need to adjust the
11396 address by one, so that attempts to call the function pointer will
11397 correctly interpret it as Thumb code. */
11401 /* Note that sgot->output_offset is not involved in this
11402 calculation. We always want the start of .got. If we
11403 define _GLOBAL_OFFSET_TABLE in a different way, as is
11404 permitted by the ABI, we might have to change this
11405 calculation. */
11412 /* Use global offset table as symbol value. */
11426 /* Relocation is to the entry for this symbol in the
11427 global offset table. */
11434 {
11435 /* We have a relocation against a locally-binding STT_GNU_IFUNC
11436 symbol, and the relocation resolves directly to the runtime
11437 target rather than to the .iplt entry. This means that any
11438 .got entry would be the same value as the .igot.plt entry,
11439 so there's no point creating both. */
11442 }
11444 {
11445 bfd_vma off;
11450 {
11451 /* We have already processsed one GOT relocation against
11452 this symbol. */
11457 }
11458 else
11459 {
11460 Elf_Internal_Rela outrel;
11465 {
11466 /* If the symbol doesn't resolve locally in a static
11467 object, we have an undefined reference. If the
11468 symbol doesn't resolve locally in a dynamic object,
11469 it should be resolved by the dynamic linker. */
11471 {
11474 }
11475 else
11478 }
11479 else
11480 {
11486 else
11487 {
11491 }
11493 }
11495 /* The GOT entry is initialized to zero by default.
11496 See if we should install a different value. */
11499 {
11503 }
11512 {
11517 }
11520 }
11522 }
11523 else
11524 {
11525 bfd_vma off;
11532 /* The offset must always be a multiple of 4. We use the
11533 least significant bit to record whether we have already
11534 generated the necessary reloc. */
11537 else
11538 {
11539 Elf_Internal_Rela outrel;
11546 else
11547 {
11551 }
11553 /* The GOT entry is initialized to zero by default.
11554 See if we should install a different value. */
11565 {
11571 }
11574 }
11577 }
11594 {
11595 bfd_vma off;
11604 else
11605 {
11606 /* If we don't know the module number, create a relocation
11607 for it. */
11609 {
11610 Elf_Internal_Rela outrel;
11625 }
11626 else
11630 }
11633 {
11639 }
11640 else
11641 {
11649 }
11650 }
11661 {
11669 {
11674 h)
11677 {
11680 }
11684 }
11685 else
11686 {
11690 {
11693 input_bfd,
11695 r_symndx);
11697 }
11701 }
11703 /* Linker relaxations happens from one of the
11704 R_ARM_{GOTDESC,CALL,DESCSEQ} relocations to IE or LE. */
11712 else
11713 {
11715 Elf_Internal_Rela outrel;
11718 /* The GOT entries have not been initialized yet. Do it
11719 now, and emit any relocations. If both an IE GOT and a
11720 GD GOT are necessary, we emit the GD first. */
11727 {
11730 }
11733 {
11736 /* We should have relaxed, unless this is an undefined
11737 weak symbol. */
11746 + offplt
11758 /* For globals, the first word in the relocation gets
11759 the relocation index and the top bit set, or zero,
11760 if we're binding now. For locals, it gets the
11761 symbol's offset in the tls section. */
11769 /* Second word in the relocation is always zero. */
11773 }
11775 {
11777 {
11793 else
11794 {
11797 R_ARM_TLS_DTPOFF32);
11806 }
11807 }
11808 else
11809 {
11810 /* If we are not emitting relocations for a
11811 general dynamic reference, then we must be in a
11812 static link or an executable link with the
11813 symbol binding locally. Mark it as belonging
11814 to module 1, the executable. */
11819 }
11822 }
11825 {
11827 {
11830 else
11842 }
11843 else
11847 }
11851 else
11853 }
11862 {
11863 bfd_signed_vma offset;
11864 /* TLS stubs are arm mode. The original symbol is a
11865 data object, so branch_type is bogus. */
11867 enum elf32_arm_stub_type stub_type
11875 {
11877 = elf32_arm_get_stub_entry
11883 }
11884 else
11890 {
11900 }
11901 else
11902 {
11903 /* Thumb blx encodes the offset in a complicated
11904 fashion. */
11914 {
11916 }
11917 else
11918 {
11920 /* Round up the offset to a word boundary. */
11922 }
11934 }
11935 }
11936 /* These relocations needs special care, as besides the fact
11937 they point somewhere in .gotplt, the addend must be
11938 adjusted accordingly depending on the type of instruction
11939 we refer to. */
11941 {
11950 {
11957 /* bl/blx */
11960 /* add */
11962 else
11963 {
11964 _bfd_error_handler
11965 /* xgettext:c-format */
11967 "unexpected %s instruction '%#lx' "
11972 }
11973 }
11974 else
11975 {
11979 {
11990 _bfd_error_handler
11991 /* xgettext:c-format */
11993 "unexpected %s instruction '%#lx' "
11998 }
11999 }
12007 }
12008 else
12016 {
12017 /* For FDPIC relocations, resolve to the offset of the GOT
12018 entry from the start of GOT. */
12024 }
12025 else
12026 {
12030 }
12031 }
12035 {
12036 _bfd_error_handler
12037 /* xgettext:c-format */
12042 }
12043 else
12052 {
12055 /* Ensure that we have a BX instruction. */
12059 {
12060 /* Branch to veneer. */
12061 bfd_vma glue_addr;
12068 }
12069 else
12070 {
12071 /* Preserve Rm (lowest four bits) and the condition code
12072 (highest four bits). Other bits encode MOV PC,Rm. */
12074 }
12077 }
12084 /* Until we properly support segment-base-relative addressing then
12085 we assume the segment base to be zero, as for the group relocations.
12086 Thus R_ARM_MOVW_BREL_NC has the same semantics as R_ARM_MOVW_ABS_NC
12087 and R_ARM_MOVT_BREL has the same semantics as R_ARM_MOVT_ABS. */
12091 {
12095 {
12098 }
12120 }
12127 /* Until we properly support segment-base-relative addressing then
12128 we assume the segment base to be zero, as for the above relocations.
12129 Thus R_ARM_THM_MOVW_BREL_NC has the same semantics as
12130 R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_BREL has the same semantics
12131 as R_ARM_THM_MOVT_ABS. */
12135 {
12136 bfd_vma insn;
12142 {
12148 }
12174 }
12187 {
12191 /* sb is the origin of the *segment* containing the symbol. */
12193 bfd_vma residual;
12194 bfd_vma g_n;
12195 bfd_signed_vma signed_value;
12198 /* Determine which group of bits to select. */
12200 {
12222 }
12224 /* If REL, extract the addend from the insn. If RELA, it will
12225 have already been fetched for us. */
12227 {
12234 else
12235 {
12236 /* Compensate for the fact that in the instruction, the
12237 rotation is stored in multiples of 2 bits. */
12240 /* Rotate "constant" right by "rotation" bits. */
12243 }
12245 /* Determine if the instruction is an ADD or a SUB.
12246 (For REL, this determines the sign of the addend.) */
12249 {
12250 _bfd_error_handler
12251 /* xgettext:c-format */
12256 }
12259 }
12261 /* Compute the value (X) to go in the place. */
12267 /* PC relative. */
12269 else
12270 /* Section base relative. */
12273 /* If the target symbol is a Thumb function, then set the
12274 Thumb bit in the address. */
12278 /* Calculate the value of the relevant G_n, in encoded
12279 constant-with-rotation format. */
12283 /* Check for overflow if required. */
12290 {
12291 _bfd_error_handler
12292 /* xgettext:c-format */
12299 }
12301 /* Mask out the value and the ADD/SUB part of the opcode; take care
12302 not to destroy the S bit. */
12305 /* Set the opcode according to whether the value to go in the
12306 place is negative. */
12309 else
12312 /* Encode the offset. */
12316 }
12325 {
12329 /* sb is the origin of the *segment* containing the symbol. */
12331 bfd_vma residual;
12332 bfd_signed_vma signed_value;
12335 /* Determine which groups of bits to calculate. */
12337 {
12355 }
12357 /* If REL, extract the addend from the insn. If RELA, it will
12358 have already been fetched for us. */
12360 {
12363 }
12365 /* Compute the value (X) to go in the place. */
12369 /* PC relative. */
12371 else
12372 /* Section base relative. */
12375 /* Calculate the value of the relevant G_{n-1} to obtain
12376 the residual at that stage. */
12380 /* Check for overflow. */
12382 {
12383 _bfd_error_handler
12384 /* xgettext:c-format */
12391 }
12393 /* Mask out the value and U bit. */
12396 /* Set the U bit if the value to go in the place is non-negative. */
12400 /* Encode the offset. */
12404 }
12413 {
12417 /* sb is the origin of the *segment* containing the symbol. */
12419 bfd_vma residual;
12420 bfd_signed_vma signed_value;
12423 /* Determine which groups of bits to calculate. */
12425 {
12443 }
12445 /* If REL, extract the addend from the insn. If RELA, it will
12446 have already been fetched for us. */
12448 {
12451 }
12453 /* Compute the value (X) to go in the place. */
12457 /* PC relative. */
12459 else
12460 /* Section base relative. */
12463 /* Calculate the value of the relevant G_{n-1} to obtain
12464 the residual at that stage. */
12468 /* Check for overflow. */
12470 {
12471 _bfd_error_handler
12472 /* xgettext:c-format */
12479 }
12481 /* Mask out the value and U bit. */
12484 /* Set the U bit if the value to go in the place is non-negative. */
12488 /* Encode the offset. */
12492 }
12501 {
12505 /* sb is the origin of the *segment* containing the symbol. */
12507 bfd_vma residual;
12508 bfd_signed_vma signed_value;
12511 /* Determine which groups of bits to calculate. */
12513 {
12531 }
12533 /* If REL, extract the addend from the insn. If RELA, it will
12534 have already been fetched for us. */
12536 {
12539 }
12541 /* Compute the value (X) to go in the place. */
12545 /* PC relative. */
12547 else
12548 /* Section base relative. */
12551 /* Calculate the value of the relevant G_{n-1} to obtain
12552 the residual at that stage. */
12556 /* Check for overflow. (The absolute value to go in the place must be
12557 divisible by four and, after having been divided by four, must
12558 fit in eight bits.) */
12560 {
12561 _bfd_error_handler
12562 /* xgettext:c-format */
12569 }
12571 /* Mask out the value and U bit. */
12574 /* Set the U bit if the value to go in the place is non-negative. */
12578 /* Encode the offset. */
12582 }
12589 {
12595 /* Compute address. */
12601 /* Clean imm8 insn. */
12603 /* And update with correct part of address. */
12605 /* Update insn. */
12607 }
12613 {
12615 {
12620 {
12623 }
12630 {
12633 }
12635 /* Resolve relocation. */
12638 /* Emit R_ARM_FUNCDESC_VALUE or two fixups on funcdesc if
12639 not done yet. */
12643 }
12644 else
12645 {
12648 bfd_vma addr;
12651 /* For static binaries, sym_sec can be null. */
12653 {
12656 }
12657 else
12658 {
12661 }
12664 {
12667 }
12669 /* This case cannot occur since funcdesc is allocated by
12670 the dynamic loader so we cannot resolve the relocation. */
12672 {
12675 }
12677 /* Resolve relocation. */
12680 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12684 }
12685 }
12690 {
12692 {
12693 Elf_Internal_Rela outrel;
12695 /* Resolve relocation. */
12699 /* Add funcdesc and associated R_ARM_FUNCDESC_VALUE. */
12701 {
12704 bfd_vma addr;
12707 /* For static binaries sym_sec can be null. */
12709 {
12712 }
12713 else
12714 {
12717 }
12719 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12723 }
12725 /* Add a dynamic relocation on GOT entry if not already done. */
12727 {
12729 {
12734 else
12738 sgot->contents
12740 }
12741 else
12742 {
12744 }
12752 else
12755 else
12758 }
12759 }
12760 else
12761 {
12762 /* Such relocation on static function should not have been
12763 emitted by the compiler. */
12765 }
12766 }
12771 {
12773 {
12775 Elf_Internal_Rela outrel;
12779 {
12782 }
12789 {
12792 }
12794 /* Replace static FUNCDESC relocation with a
12795 R_ARM_RELATIVE dynamic relocation or with a rofixup for
12796 executable. */
12803 else
12809 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12813 }
12814 else
12815 {
12817 {
12820 bfd_vma addr;
12822 Elf_Internal_Rela outrel;
12824 /* For static binaries sym_sec can be null. */
12826 {
12829 }
12830 else
12831 {
12834 }
12839 /* Replace static FUNCDESC relocation with a
12840 R_ARM_RELATIVE dynamic relocation. */
12847 else
12853 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12857 }
12858 else
12859 {
12860 Elf_Internal_Rela outrel;
12862 /* Add a dynamic relocation. */
12868 }
12869 }
12870 }
12875 {
12876 bfd_vma relocation;
12881 {
12889 /* Sign extend. */
12891 }
12898 /* Put RELOCATION back into the insn. */
12899 {
12906 }
12908 /* Put the relocated value back in the object file: */
12913 }
12916 {
12917 bfd_vma relocation;
12922 {
12930 /* Sign extend. */
12933 }
12940 /* Put RELOCATION back into the insn. */
12941 {
12948 }
12950 /* Put the relocated value back in the object file: */
12955 }
12958 {
12959 bfd_vma relocation;
12964 {
12972 /* Sign extend. */
12975 }
12982 /* Put RELOCATION back into the insn. */
12983 {
12990 }
12992 /* Put the relocated value back in the object file: */
12997 }
13001 }
13002 }
13004 /* Add INCREMENT to the reloc (of type HOWTO) at ADDRESS. */
13005 static void
13009 bfd_signed_vma increment)
13010 {
13011 bfd_signed_vma addend;
13015 {
13033 }
13034 else
13035 {
13036 bfd_vma contents;
13040 /* Get the (signed) value from the instruction. */
13043 {
13044 bfd_signed_vma mask;
13049 }
13051 /* Add in the increment, (which is a byte value). */
13053 {
13065 /* Should we check for overflow here ? */
13067 /* Drop any undesired bits. */
13070 }
13075 }
13076 }
13078 #define IS_ARM_TLS_RELOC(R_TYPE) \
13079 ((R_TYPE) == R_ARM_TLS_GD32 \
13080 || (R_TYPE) == R_ARM_TLS_GD32_FDPIC \
13081 || (R_TYPE) == R_ARM_TLS_LDO32 \
13082 || (R_TYPE) == R_ARM_TLS_LDM32 \
13083 || (R_TYPE) == R_ARM_TLS_LDM32_FDPIC \
13084 || (R_TYPE) == R_ARM_TLS_DTPOFF32 \
13085 || (R_TYPE) == R_ARM_TLS_DTPMOD32 \
13086 || (R_TYPE) == R_ARM_TLS_TPOFF32 \
13087 || (R_TYPE) == R_ARM_TLS_LE32 \
13088 || (R_TYPE) == R_ARM_TLS_IE32 \
13089 || (R_TYPE) == R_ARM_TLS_IE32_FDPIC \
13090 || IS_ARM_TLS_GNU_RELOC (R_TYPE))
13092 /* Specific set of relocations for the gnu tls dialect. */
13093 #define IS_ARM_TLS_GNU_RELOC(R_TYPE) \
13094 ((R_TYPE) == R_ARM_TLS_GOTDESC \
13095 || (R_TYPE) == R_ARM_TLS_CALL \
13096 || (R_TYPE) == R_ARM_THM_TLS_CALL \
13097 || (R_TYPE) == R_ARM_TLS_DESCSEQ \
13098 || (R_TYPE) == R_ARM_THM_TLS_DESCSEQ)
13100 /* Relocate an ARM ELF section. */
13102 static int
13111 {
13129 {
13136 bfd_vma relocation;
13137 bfd_reloc_status_type r;
13138 arelent bfd_reloc;
13161 {
13166 /* An object file might have a reference to a local
13167 undefined symbol. This is a daft object file, but we
13168 should at least do something about it. V4BX & NONE
13169 relocations do not use the symbol and are explicitly
13170 allowed to use the undefined symbol, so allow those.
13171 Likewise for relocations against STN_UNDEF. */
13184 {
13191 {
13196 {
13218 {
13219 _bfd_error_handler
13220 /* xgettext:c-format */
13226 }
13230 /* Get the (signed) value from the instruction. */
13233 {
13234 bfd_signed_vma mask;
13239 }
13241 }
13244 addend =
13249 /* Cases here must match those in the preceding
13250 switch statement. */
13252 {
13275 }
13276 }
13277 }
13278 else
13280 }
13281 else
13282 {
13291 }
13298 {
13299 /* This is a relocatable link. We don't have to change
13300 anything, unless the reloc is against a section symbol,
13301 in which case we have to adjust according to where the
13302 section symbol winds up in the output section. */
13304 {
13308 else
13310 }
13312 }
13316 else
13317 {
13318 name = (bfd_elf_string_from_elf_section
13322 }
13330 {
13331 _bfd_error_handler
13333 /* xgettext:c-format */
13335 /* xgettext:c-format */
13337 input_bfd,
13338 input_section,
13341 name);
13342 }
13344 /* We call elf32_arm_final_link_relocate unless we're completely
13345 done, i.e., the relaxation produced the final output we want,
13346 and we won't let anybody mess with it. Also, we have to do
13347 addend adjustments in case of a R_ARM_TLS_GOTDESC relocation
13348 both in relaxed and non-relaxed cases. */
13354 {
13357 /* This may have been marked unresolved because it came from
13358 a shared library. But we've just dealt with that. */
13360 }
13361 else
13365 {
13376 }
13378 /* Dynamic relocs are not propagated for SEC_DEBUGGING sections
13379 because such sections are not SEC_ALLOC and thus ld.so will
13380 not process them. */
13386 {
13387 _bfd_error_handler
13388 /* xgettext:c-format */
13391 input_bfd,
13392 input_section,
13397 }
13400 {
13402 {
13404 /* If the overflowing reloc was to an undefined symbol,
13405 we have already printed one error message and there
13406 is no point complaining again. */
13427 /* error_message should already be set. */
13432 /* Fall through. */
13434 common_error:
13439 }
13440 }
13441 }
13444 }
13446 /* Add a new unwind edit to the list described by HEAD, TAIL. If TINDEX is zero,
13447 adds the edit to the start of the list. (The list must be built in order of
13448 ascending TINDEX: the function's callers are primarily responsible for
13449 maintaining that condition). */
13451 static void
13454 arm_unwind_edit_type type,
13457 {
13466 {
13476 }
13477 else
13478 {
13485 }
13486 }
13490 /* Increase the size of EXIDX_SEC by ADJUST bytes. ADJUST mau be negative. */
13492 static void
13494 {
13502 /* Adjust size of output section. */
13504 }
13506 /* Insert an EXIDX_CANTUNWIND marker at the end of a section. */
13508 static void
13510 {
13514 add_unwind_table_edit
13522 }
13524 /* Scan .ARM.exidx tables, and create a list describing edits which should be
13525 made to those tables, such that:
13527 1. Regions without unwind data are marked with EXIDX_CANTUNWIND entries.
13528 2. Duplicate entries are merged together (EXIDX_CANTUNWIND, or unwind
13529 codes which have been inlined into the index).
13531 If MERGE_EXIDX_ENTRIES is false, duplicate entries are not merged.
13533 The edits are applied when the tables are written
13534 (in elf32_arm_write_section). */
13536 bool
13541 {
13548 /* Walk over all EXIDX sections, and create backlinks from the corrsponding
13549 text sections. */
13551 {
13555 {
13563 {
13564 Elf_Internal_Shdr *linked_hdr
13572 /* Link this .ARM.exidx section back from the text section it
13573 describes. */
13575 }
13576 }
13577 }
13579 /* Walk all text sections in order of increasing VMA. Eilminate duplicate
13580 index table entries (EXIDX_CANTUNWIND and inlined unwind opcodes),
13581 and add EXIDX_CANTUNWIND entries for sections with no unwind table data. */
13584 {
13591 bfd_vma j;
13602 {
13603 /* Section has no unwind data. */
13607 /* Ignore zero sized sections. */
13614 }
13616 /* Skip /DISCARD/ sections. */
13633 /* An error? */
13637 {
13639 /* Add cantunwind if first unwind item does not match section
13640 start. */
13642 {
13645 }
13646 }
13649 {
13654 /* An EXIDX_CANTUNWIND entry. */
13656 {
13660 }
13661 /* Inlined unwinding data. Merge if equal to previous. */
13663 {
13669 }
13670 /* Normal table entry. In theory we could merge these too,
13671 but duplicate entries are likely to be much less common. */
13672 else
13676 {
13681 }
13684 }
13686 /* Free contents if we allocated it ourselves. */
13690 /* Record edits to be applied later (in elf32_arm_write_section). */
13699 }
13701 /* Add terminating CANTUNWIND entry. */
13707 }
13709 static bool
13712 {
13728 }
13730 static bool
13732 {
13739 /* Invoke the regular ELF backend linker to do all the work. */
13743 /* Process stub sections (eg BE8 encoding, ...). */
13747 {
13749 /* Only process it once, in its link_sec slot. */
13751 {
13757 }
13758 }
13760 /* Write out any glue sections now that we have created all the
13761 stubs. */
13763 {
13766 ARM2THUMB_GLUE_SECTION_NAME))
13771 THUMB2ARM_GLUE_SECTION_NAME))
13776 VFP11_ERRATUM_VENEER_SECTION_NAME))
13781 STM32L4XX_ERRATUM_VENEER_SECTION_NAME))
13786 ARM_BX_GLUE_SECTION_NAME))
13788 }
13791 }
13793 /* Return a best guess for the machine number based on the attributes. */
13795 static unsigned int
13797 {
13801 {
13808 {
13815 {
13823 {
13829 {
13833 }
13834 }
13835 }
13838 }
13872 /* Force entry to be added for any new known Tag_CPU_arch value. */
13875 /* Unknown Tag_CPU_arch value. */
13877 }
13878 }
13880 /* Set the right machine number. */
13882 static bool
13884 {
13890 {
13893 else
13895 }
13899 }
13901 /* Function to keep ARM specific flags in the ELF header. */
13903 static bool
13905 {
13908 {
13910 {
13912 _bfd_error_handler
13913 (_("warning: not setting interworking flag of %pB since it has already been specified as non-interworking"),
13914 abfd);
13915 else
13916 _bfd_error_handler
13918 abfd);
13919 }
13920 }
13921 else
13922 {
13925 }
13928 }
13930 /* Copy backend specific data from one object module to another. */
13932 static bool
13934 {
13935 flagword in_flags;
13936 flagword out_flags;
13947 {
13948 /* Cannot mix APCS26 and APCS32 code. */
13952 /* Cannot mix float APCS and non-float APCS code. */
13956 /* If the src and dest have different interworking flags
13957 then turn off the interworking bit. */
13959 {
13961 _bfd_error_handler
13962 (_("warning: clearing the interworking flag of %pB because non-interworking code in %pB has been linked with it"),
13966 }
13968 /* Likewise for PIC, though don't warn for this case. */
13971 }
13977 }
13979 /* Values for Tag_ABI_PCS_R9_use. */
13980 enum
13981 {
13982 AEABI_R9_V6,
13983 AEABI_R9_SB,
13984 AEABI_R9_TLS,
13985 AEABI_R9_unused
13986 };
13988 /* Values for Tag_ABI_PCS_RW_data. */
13989 enum
13990 {
13991 AEABI_PCS_RW_data_absolute,
13992 AEABI_PCS_RW_data_PCrel,
13993 AEABI_PCS_RW_data_SBrel,
13994 AEABI_PCS_RW_data_unused
13995 };
13997 /* Values for Tag_ABI_enum_size. */
13998 enum
13999 {
14000 AEABI_enum_unused,
14001 AEABI_enum_short,
14002 AEABI_enum_wide,
14003 AEABI_enum_forced_wide
14004 };
14006 /* Determine whether an object attribute tag takes an integer, a
14007 string or both. */
14009 static int
14011 {
14020 else
14022 }
14024 /* The ABI defines that Tag_conformance should be emitted first, and that
14025 Tag_nodefaults should be second (if either is defined). This sets those
14026 two positions, and bumps up the position of all the remaining tags to
14027 compensate. */
14028 static int
14030 {
14040 }
14042 /* Attribute numbers >=64 (mod 128) can be safely ignored. */
14043 static bool
14045 {
14047 {
14048 _bfd_error_handler
14053 }
14054 else
14055 {
14056 _bfd_error_handler
14060 }
14061 }
14063 /* Read the architecture from the Tag_also_compatible_with attribute, if any.
14064 Returns -1 if no architecture could be read. */
14066 static int
14068 {
14072 /* Note: the tag and its argument below are uleb128 values, though
14073 currently-defined values fit in one byte for each. */
14080 /* This tag is "safely ignorable", so don't complain if it looks funny. */
14082 }
14084 /* Set, or unset, the architecture of the Tag_also_compatible_with attribute.
14085 The tag is removed if ARCH is -1. */
14087 static void
14089 {
14094 {
14097 }
14099 /* Note: the tag and its argument below are uleb128 values, though
14100 currently-defined values fit in one byte for each. */
14106 }
14108 /* Combine two values for Tag_CPU_arch, taking secondary compatibility tags
14109 into account. */
14111 static int
14114 {
14115 #define T(X) TAG_CPU_ARCH_##X
14118 {
14128 };
14130 {
14141 };
14143 {
14155 };
14157 {
14170 };
14172 {
14186 };
14188 {
14203 };
14205 {
14228 };
14230 {
14247 };
14249 {
14267 };
14269 {
14288 };
14290 {
14313 };
14315 {
14339 };
14341 {
14366 };
14368 {
14369 v6t2,
14370 v6k,
14371 v7,
14372 v6_m,
14373 v6s_m,
14374 v7e_m,
14375 v8,
14376 v8r,
14377 v8m_baseline,
14378 v8m_mainline,
14379 NULL,
14380 NULL,
14381 NULL,
14382 v8_1m_mainline,
14383 v9,
14384 /* Pseudo-architecture. */
14385 v4t_plus_v6_m
14386 };
14388 /* Check we've not got a higher architecture than we know about. */
14391 {
14394 }
14396 /* Override old tag if we have a Tag_also_compatible_with on the output. */
14402 /* And override the new tag if we have a Tag_also_compatible_with on the
14403 input. */
14412 /* Architectures before V6KZ add features monotonically. */
14418 /* Use Tag_CPU_arch == V4T and Tag_also_compatible_with (Tag_CPU_arch V6_M)
14419 as the canonical version. */
14421 {
14424 }
14425 else
14429 {
14433 }
14436 #undef T
14437 }
14439 /* Query attributes object to see if integer divide instructions may be
14440 present in an object. */
14441 static bool
14443 {
14448 {
14450 /* Integer divide allowed if instruction contained in archetecture. */
14455 else
14459 /* Integer divide explicitly prohibited. */
14463 /* Unrecognised case - treat as allowing divide everywhere. */
14465 /* Integer divide allowed in ARM state. */
14467 }
14468 }
14470 /* Query attributes object to see if integer divide instructions are
14471 forbidden to be in the object. This is not the inverse of
14472 elf32_arm_attributes_accept_div. */
14473 static bool
14475 {
14477 }
14479 /* Merge EABI object attributes from IBFD into OBFD. Raise an error if there
14480 are conflicting attributes. */
14482 static bool
14484 {
14488 /* Some tags have 0 = don't care, 1 = strong requirement,
14489 2 = weak requirement. */
14495 /* Skip the linker stubs file. This preserves previous behavior
14496 of accepting unknown attributes in the first input file - but
14497 is that a bug? */
14501 /* Skip any input that hasn't attribute section.
14502 This enables to link object files without attribute section with
14503 any others. */
14508 {
14509 /* This is the first object. Copy the attributes. */
14514 /* Use the Tag_null value to indicate the attributes have been
14515 initialized. */
14518 /* We do not output objects with Tag_MPextension_use_legacy - we move
14519 the attribute's value to Tag_MPextension_use. */
14521 {
14525 {
14526 _bfd_error_handler
14530 }
14536 }
14538 /* PR 28859 and 28848: Handle the case where the first input file,
14539 eg crti.o, has a Tag_ABI_HardFP_use of 3 but no Tag_FP_arch set.
14540 Using Tag_ABI_HardFP_use in this way is deprecated, so reset the
14541 attribute to zero.
14542 FIXME: Should we handle other non-zero values of Tag_ABI_HardFO_use ? */
14547 }
14551 /* This needs to happen before Tag_ABI_FP_number_model is merged. */
14553 {
14554 /* Ignore mismatches if the object doesn't use floating point or is
14555 floating point ABI independent. */
14562 {
14563 _bfd_error_handler
14568 }
14569 }
14572 {
14573 /* Merge this attribute with existing attributes. */
14575 {
14578 /* These are merged after Tag_CPU_arch. */
14583 /* Use the first value seen. */
14587 {
14592 {
14593 /* These aren't real CPU names, but we can't guess
14594 that from the architecture version alone. */
14618 };
14620 /* Merge Tag_CPU_arch and Tag_also_compatible_with. */
14626 secondary_compat);
14628 /* Return with error if failed to merge. */
14636 /* Merge Tag_CPU_name and Tag_CPU_raw_name. */
14640 {
14641 /* The output architecture has been changed to match the
14642 input architecture. Use the input names. */
14649 }
14650 else
14651 {
14654 }
14656 /* If we still don't have a value for Tag_CPU_name,
14657 make one up now. Tag_CPU_raw_name remains blank. */
14662 }
14669 /* ??? Do Advanced_SIMD (NEON) and WMMX conflict? */
14683 /* Use the largest value specified. */
14690 /* Use the smallest value specified. */
14699 {
14700 /* This error message should be enabled once all non-conformant
14701 binaries in the toolchain have had the attributes set
14702 properly.
14703 _bfd_error_handler
14704 (_("error: %pB: 8-byte data alignment conflicts with %pB"),
14705 obfd, ibfd);
14706 result = false; */
14707 }
14708 /* Fall through. */
14711 /* Use the "greatest" from the sequence 0, 2, 1, or the largest
14712 value if greater than 2 (for future-proofing). */
14720 /* The virtualization tag effectively stores two bits of
14721 information: the intended use of TrustZone (in bit 0), and the
14722 intended use of Virtualization (in bit 1). */
14727 {
14730 else
14731 {
14732 _bfd_error_handler
14737 }
14738 }
14743 {
14744 /* 0 will merge with anything.
14745 'A' and 'S' merge to 'A'.
14746 'R' and 'S' merge to 'R'.
14747 'M' and 'A|R|S' is an error. */
14756 else
14757 {
14758 _bfd_error_handler
14760 ibfd,
14764 }
14765 }
14769 /* No need to change output value if any of:
14770 - pre (<=) ARMv5T input architecture (do not have DSP)
14771 - M input profile not ARMv7E-M and do not have DSP. */
14777 /* Output value should be 0 if DSP part of architecture, ie.
14778 - post (>=) ARMv5te architecture output
14779 - A, R or S profile output or ARMv7E-M output architecture. */
14786 /* Otherwise, DSP instructions are added and not part of output
14787 architecture. */
14788 else
14793 {
14794 /* Tag_ABI_HardFP_use is handled along with Tag_FP_arch since
14795 the meaning of Tag_ABI_HardFP_use depends on Tag_FP_arch
14796 when it's 0. It might mean absence of FP hardware if
14797 Tag_FP_arch is zero. */
14799 #define VFP_VERSION_COUNT 9
14800 static const struct
14801 {
14805 {
14815 };
14820 /* If the output has no requirement about FP hardware,
14821 follow the requirement of the input. */
14823 {
14824 /* This assert is still reasonable, we shouldn't
14825 produce the suspicious build attribute
14826 combination (See below for in_attr). */
14832 }
14833 /* If the input has no requirement about FP hardware, do
14834 nothing. */
14836 {
14837 /* We used to assert that Tag_ABI_HardFP_use was
14838 zero here, but we should never assert when
14839 consuming an object file that has suspicious
14840 build attributes. The single precision variant
14841 of 'no FP architecture' is still 'no FP
14842 architecture', so we just ignore the tag in this
14843 case. */
14845 }
14847 /* Both the input and the output have nonzero Tag_FP_arch.
14848 So Tag_ABI_HardFP_use is implied by Tag_FP_arch when it's zero. */
14850 /* If both the input and the output have zero Tag_ABI_HardFP_use,
14851 do nothing. */
14854 ;
14855 /* If the input and the output have different Tag_ABI_HardFP_use,
14856 the combination of them is 0 (implied by Tag_FP_arch). */
14861 /* Now we can handle Tag_FP_arch. */
14863 /* Values of VFP_VERSION_COUNT or more aren't defined, so just
14864 pick the biggest. */
14867 {
14870 }
14871 /* The output uses the superset of input features
14872 (ISA version) and registers. */
14879 /* This assumes all possible supersets are also a valid
14880 options. */
14882 {
14886 }
14888 }
14894 {
14895 /* It's sometimes ok to mix different configs, so this is only
14896 a warning. */
14897 _bfd_error_handler
14899 }
14905 {
14906 _bfd_error_handler
14909 }
14917 {
14918 _bfd_error_handler
14920 ibfd);
14922 }
14923 /* Use the smallest value specified. */
14930 {
14931 _bfd_error_handler
14932 (_("warning: %pB uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail"),
14934 }
14940 {
14943 {
14944 /* The existing object is compatible with anything.
14945 Use whatever requirements the new object has. */
14947 }
14951 {
14962 _bfd_error_handler
14963 (_("warning: %pB uses %s enums yet the output is to use %s enums; use of enum values across objects may fail"),
14965 }
14966 }
14969 /* Aready done. */
14973 {
14974 _bfd_error_handler
14978 }
14981 /* Merged in target-independent code. */
14984 /* This is handled along with Tag_FP_arch. */
14988 {
14990 {
14991 _bfd_error_handler
14995 }
14996 }
15002 /* A value of zero on input means that the divide instruction may
15003 be used if available in the base architecture as specified via
15004 Tag_CPU_arch and Tag_CPU_arch_profile. A value of 1 means that
15005 the user did not want divide instructions. A value of 2
15006 explicitly means that divide instructions were allowed in ARM
15007 and Thumb state. */
15021 /* We don't output objects with Tag_MPextension_use_legacy - we
15022 move the value to Tag_MPextension_use. */
15024 {
15026 {
15027 _bfd_error_handler
15030 ibfd);
15032 }
15033 }
15041 /* This tag is set if it exists, but the value is unused (and is
15042 typically zero). We don't actually need to do anything here -
15043 the merge happens automatically when the type flags are merged
15044 below. */
15047 /* Already done in Tag_CPU_arch. */
15050 /* Keep the attribute if it matches. Throw it away otherwise.
15051 No attribute means no claim to conform. */
15058 result
15060 }
15062 /* If out_attr was copied from in_attr then it won't have a type yet. */
15065 }
15067 /* Merge Tag_compatibility attributes and any common GNU ones. */
15071 /* Check for any attributes not known on ARM. */
15075 }
15078 /* Return TRUE if the two EABI versions are incompatible. */
15080 static bool
15082 {
15083 /* v4 and v5 are the same spec before and after it was released,
15084 so allow mixing them. */
15090 }
15092 /* Merge backend specific data from an object file to the output
15093 object file when linking. */
15095 static bool
15098 /* Display the flags field. */
15100 static bool
15102 {
15108 /* Print normal ELF private data. */
15112 /* Ignore init flag - it may not be set, despite the flags field
15113 containing valid data. */
15118 {
15120 /* The following flag bits are GNU extensions and not part of the
15121 official ARM ELF extended ABI. Hence they are only decoded if
15122 the EABI version is not set. */
15128 else
15135 else
15164 else
15175 else
15207 eabi:
15220 }
15241 }
15243 static int
15245 {
15247 {
15252 /* If the symbol is not an object, return the STT_ARM_16BIT flag.
15253 This allows us to distinguish between data used by Thumb instructions
15254 and non-data (which is probably code) inside Thumb regions of an
15255 executable. */
15262 }
15265 }
15273 {
15276 {
15280 }
15283 }
15285 /* Look through the relocs for a section during the first phase. */
15287 static bool
15290 {
15314 /* Create dynamic sections for relocatable executables so that we can
15315 copy relocations. */
15318 {
15321 }
15336 {
15348 /* PR 9934: It is possible to have relocations that do not
15349 refer to symbols, thus it is also possible to have an
15350 object file containing relocations but no symbol table. */
15352 {
15354 r_symndx);
15356 }
15361 {
15363 {
15364 /* A local symbol. */
15369 }
15370 else
15371 {
15376 }
15377 }
15385 /* Could be done earlier, if h were already available. */
15388 {
15390 {
15392 {
15399 }
15400 else
15401 {
15403 }
15404 }
15408 {
15410 {
15411 /* Such a relocation is not supposed to be generated
15412 by gcc on a static function. */
15413 /* Anyway if needed it could be handled. */
15415 }
15416 else
15417 {
15419 }
15420 }
15424 {
15426 {
15433 }
15434 else
15435 {
15437 }
15438 }
15452 /* This symbol requires a global offset table entry. */
15453 {
15457 {
15470 }
15476 {
15479 }
15480 else
15481 {
15482 /* This is a global offset table entry for a local symbol. */
15486 {
15488 r_symndx);
15490 }
15494 }
15496 /* If a variable is accessed with both tls methods, two
15497 slots may be created. */
15502 /* We will already have issued an error message if there
15503 is a TLS/non-TLS mismatch, based on the symbol
15504 type. So just combine any TLS types needed. */
15509 /* If the symbol is accessed in both IE and GDESC
15510 method, we're able to relax. Turn off the GDESC flag,
15511 without messing up with any other kind of tls types
15512 that may be involved. */
15517 {
15520 else
15522 }
15523 }
15524 /* Fall through. */
15530 /* Fall through. */
15552 /* VxWorks uses dynamic R_ARM_ABS12 relocations for
15553 ldr __GOTT_INDEX__ offsets. */
15555 {
15558 }
15561 /* Fall through. */
15568 {
15569 _bfd_error_handler
15570 (_("%pB: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"),
15575 }
15577 /* Fall through. */
15580 jump_over:
15582 {
15584 }
15585 /* Fall through. */
15593 /* Should the interworking branches be listed here? */
15597 {
15600 {
15601 /* In shared libraries and relocatable executables,
15602 we treat local relative references as calls;
15603 see the related SYMBOL_CALLS_LOCAL code in
15604 allocate_dynrelocs. */
15607 }
15608 else
15609 /* We are creating a shared library or relocatable
15610 executable, and this is a reloc against a global symbol,
15611 or a non-PC-relative reloc against a local symbol.
15612 We may need to copy the reloc into the output. */
15614 }
15615 else
15619 /* This relocation describes the C++ object vtable hierarchy.
15620 Reconstruct it for later use during GC. */
15626 /* This relocation describes which C++ vtable entries are actually
15627 used. Record for later use during GC. */
15632 }
15635 {
15637 /* We may need a .plt entry if the function this reloc
15638 refers to is in a different object, regardless of the
15639 symbol's type. We can't tell for sure yet, because
15640 something later might force the symbol local. */
15643 /* If this reloc is in a read-only section, we might
15644 need a copy reloc. We can't check reliably at this
15645 stage whether the section is read-only, as input
15646 sections have not yet been mapped to output sections.
15647 Tentatively set the flag for now, and correct in
15648 adjust_dynamic_symbol. */
15650 }
15654 {
15660 {
15663 }
15664 else
15665 {
15671 }
15673 /* If the symbol is a function that doesn't bind locally,
15674 this relocation will need a PLT entry. */
15681 /* It's too early to use htab->use_blx here, so we have to
15682 record possible blx references separately from
15683 relocs that definitely need a thumb stub. */
15691 }
15694 {
15697 /* Create a reloc section in dynobj. */
15699 {
15700 sreloc = _bfd_elf_make_dynamic_reloc_section
15705 }
15707 /* If this is a global symbol, count the number of
15708 relocations we need for this symbol. */
15711 else
15712 {
15716 }
15720 {
15731 }
15738 {
15739 /* Here we only support R_ARM_ABS32 and R_ARM_ABS32_NOI
15740 that will become rofixup. */
15741 /* This is due to the fact that we suppose all will become rofixup. */
15742 _bfd_error_handler
15747 }
15748 }
15749 }
15752 }
15754 static void
15757 {
15779 {
15782 }
15784 {
15787 }
15788 else
15800 {
15803 {
15806 irela++;
15807 count++;
15808 }
15810 {
15814 bfd_size_type j;
15815 bfd_vma offset;
15831 else
15835 {
15837 {
15839 bfd_vma bias;
15840 bfd_vma reloc_index;
15850 {
15851 bias++;
15853 }
15857 {
15859 irela++;
15860 count++;
15861 }
15864 }
15867 {
15868 /* New relocation entity. */
15877 irela++;
15878 count++;
15879 }
15880 }
15881 else
15882 {
15884 {
15887 irela++;
15888 }
15891 }
15892 }
15893 }
15901 {
15904 irela++;
15905 count--;
15906 }
15910 /* Hashes are no longer valid. */
15913 }
15915 /* Unwinding tables are not referenced directly. This pass marks them as
15916 required if the corresponding code section is marked. Similarly, ARMv8-M
15917 secure entry functions can only be referenced by SG veneers which are
15918 created after the GC process. They need to be marked in case they reside in
15919 their own section (as would be the case if code was compiled with
15920 -ffunction-sections). */
15922 static bool
15924 elf_gc_mark_hook_fn gc_mark_hook)
15925 {
15945 /* Marking EH data may cause additional code sections to be marked,
15946 requiring multiple passes. */
15949 {
15952 {
15960 {
15969 {
15973 }
15974 }
15976 /* Mark section holding ARMv8-M secure entry functions. We mark all
15977 of them so no need for a second browsing. */
15979 {
15986 /* Scan symbols. */
15988 {
15991 /* Assume it is a special symbol. If not, cmse_scan will
15992 warn about it and user can do something about it. */
15994 CMSE_PREFIX))
15995 {
16000 /* The debug sections related to these secure entry
16001 functions are marked on enabling below flag. */
16003 }
16004 }
16007 {
16008 /* Looping over all the sections of the object file containing
16009 Armv8-M secure entry functions and marking all the debug
16010 sections. */
16012 {
16013 /* If not a debug sections, skip it. */
16016 }
16018 }
16019 }
16020 }
16022 }
16025 }
16027 /* Treat mapping symbols as special target symbols. */
16029 static bool
16031 {
16033 BFD_ARM_SPECIAL_SYM_TYPE_ANY);
16034 }
16036 /* If the ELF symbol SYM might be a function in SEC, return the
16037 function size and set *CODE_OFF to the function's entry point,
16038 otherwise return zero. */
16040 static bfd_size_type
16043 {
16044 bfd_size_type size;
16056 {
16058 /* Ignore symbols created by the annobin plugin for gcc and clang.
16059 These symbols are hidden, local, notype and have a size of 0. */
16064 /* Fall through. */
16067 /* FIXME: Allow STT_GNU_IFUNC as well ? */
16071 }
16075 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
16080 /* Do not return 0 for the function's size. */
16083 }
16085 static bool
16090 {
16096 }
16098 /* Adjust a symbol defined by a dynamic object and referenced by a
16099 regular object. The current definition is in some section of the
16100 dynamic object, but we're not including those sections. We have to
16101 change the definition to something the rest of the link can
16102 understand. */
16104 static bool
16107 {
16119 /* Make sure we know what is going on here. */
16130 /* If this is a function, put it in the procedure linkage table. We
16131 will fill in the contents of the procedure linkage table later,
16132 when we know the address of the .got section. */
16134 {
16135 /* Calls to STT_GNU_IFUNC symbols always use a PLT, even if the
16136 symbol binds locally. */
16142 {
16143 /* This case can occur if we saw a PLT32 reloc in an input
16144 file, but the symbol was never referred to by a dynamic
16145 object, or if all references were garbage collected. In
16146 such a case, we don't actually need to build a procedure
16147 linkage table, and we can just do a PC24 reloc instead. */
16153 }
16156 }
16157 else
16158 {
16159 /* It's possible that we incorrectly decided a .plt reloc was
16160 needed for an R_ARM_PC24 or similar reloc to a non-function sym
16161 in check_relocs. We can't decide accurately between function
16162 and non-function syms in check-relocs; Objects loaded later in
16163 the link may change h->type. So fix it now. */
16168 }
16170 /* If this is a weak symbol, and there is a real definition, the
16171 processor independent code will have arranged for us to see the
16172 real definition first, and we can just use the same value. */
16174 {
16180 }
16182 /* If there are no non-GOT references, we do not need a copy
16183 relocation. */
16187 /* This is a reference to a symbol defined by a dynamic object which
16188 is not a function. */
16190 /* If we are creating a shared library, we must presume that the
16191 only references to the symbol are via the global offset table.
16192 For such cases we need not do anything here; the relocations will
16193 be handled correctly by relocate_section. Relocatable executables
16194 can reference data in shared objects directly, so we don't need to
16195 do anything here. */
16199 /* We must allocate the symbol in our .dynbss section, which will
16200 become part of the .bss section of the executable. There will be
16201 an entry for this symbol in the .dynsym section. The dynamic
16202 object will contain position independent code, so all references
16203 from the dynamic object to this symbol will go through the global
16204 offset table. The dynamic linker will use the .dynsym entry to
16205 determine the address it must put in the global offset table, so
16206 both the dynamic object and the regular object will refer to the
16207 same memory location for the variable. */
16208 /* If allowed, we must generate a R_ARM_COPY reloc to tell the dynamic
16209 linker to copy the initial value out of the dynamic object and into
16210 the runtime process image. We need to remember the offset into the
16211 .rel(a).bss section we are going to use. */
16213 {
16216 }
16217 else
16218 {
16221 }
16225 {
16228 }
16231 }
16233 /* Allocate space in .plt, .got and associated reloc sections for
16234 dynamic relocs. */
16236 static bool
16238 {
16256 {
16257 /* Make sure this symbol is output as a dynamic symbol.
16258 Undefined weak syms won't yet be marked as dynamic. */
16261 {
16264 }
16266 /* If the call in the PLT entry binds locally, the associated
16267 GOT entry should use an R_ARM_IRELATIVE relocation instead of
16268 the usual R_ARM_JUMP_SLOT. Put it in the .iplt section rather
16269 than the .plt section. */
16271 {
16275 /* All non-call references can be resolved directly.
16276 This means that they can (and in some cases, must)
16277 resolve directly to the run-time target, rather than
16278 to the PLT. That in turns means that any .got entry
16279 would be equal to the .igot.plt entry, so there's
16280 no point having both. */
16282 }
16287 {
16290 /* If this symbol is not defined in a regular file, and we are
16291 not generating a shared library, then set the symbol to this
16292 location in the .plt. This is required to make function
16293 pointers compare as equal between the normal executable and
16294 the shared library. */
16297 {
16301 /* Make sure the function is not marked as Thumb, in case
16302 it is the target of an ABS32 relocation, which will
16303 point to the PLT entry. */
16305 }
16307 /* VxWorks executables have a second set of relocations for
16308 each PLT entry. They go in a separate relocation section,
16309 which is processed by the kernel loader. */
16311 {
16312 /* There is a relocation for the initial PLT entry:
16313 an R_ARM_32 relocation for _GLOBAL_OFFSET_TABLE_. */
16317 /* There are two extra relocations for each subsequent
16318 PLT entry: an R_ARM_32 relocation for the GOT entry,
16319 and an R_ARM_32 relocation for the PLT entry. */
16321 }
16322 }
16323 else
16324 {
16327 }
16328 }
16329 else
16330 {
16333 }
16339 {
16345 /* Make sure this symbol is output as a dynamic symbol.
16346 Undefined weak syms won't yet be marked as dynamic. */
16351 {
16354 }
16363 /* Non-TLS symbols need one GOT slot. */
16365 else
16366 {
16368 {
16369 /* R_ARM_TLS_DESC needs 2 GOT slots. */
16370 eh->tlsdesc_got
16375 /* plt.got_offset needs to know there's a TLS_DESC
16376 reloc in the middle of .got.plt. */
16378 }
16381 {
16382 /* R_ARM_TLS_GD32 and R_ARM_TLS_GD32_FDPIC need two
16383 consecutive GOT slots. If the symbol is both GD
16384 and GDESC, got.offset may have been
16385 overwritten. */
16388 }
16391 /* R_ARM_TLS_IE32/R_ARM_TLS_IE32_FDPIC need one GOT
16392 slot. */
16394 }
16408 {
16416 {
16418 /* GDESC needs a trampoline to jump to. */
16420 }
16422 /* Only GD needs it. GDESC just emits one relocation per
16423 2 entries. */
16426 }
16429 {
16431 /* Reserve room for the GOT entry's R_ARM_GLOB_DAT relocation. */
16433 }
16436 /* No non-call references resolve the STT_GNU_IFUNC's PLT entry;
16437 they all resolve dynamically instead. Reserve room for the
16438 GOT entry's R_ARM_IRELATIVE relocation. */
16442 /* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
16445 /* Reserve room for rofixup for FDPIC executable. */
16446 /* TLS relocs do not need space since they are completely
16447 resolved. */
16449 }
16450 else
16453 /* FDPIC support. */
16455 {
16456 /* Symbol musn't be exported. */
16460 /* We only allocate one function descriptor with its associated
16461 relocation. */
16463 {
16468 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16471 else
16473 }
16474 }
16477 {
16486 {
16487 /* We only allocate one function descriptor with its
16488 associated relocation. */
16490 {
16494 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two
16495 rofixups. */
16498 else
16500 }
16501 }
16503 /* Add one entry into the GOT and a R_ARM_FUNCDESC or
16504 R_ARM_RELATIVE/rofixup relocation on it. */
16509 else
16511 }
16514 {
16521 {
16522 /* We only allocate one function descriptor with its
16523 associated relocation. */
16525 {
16530 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two
16531 rofixups. */
16534 else
16536 }
16537 }
16539 {
16540 /* For FDPIC executable we replace R_ARM_RELATIVE with a rofixup. */
16542 }
16543 else
16544 {
16545 /* Will need one dynamic reloc per reference. will be either
16546 R_ARM_FUNCDESC or R_ARM_RELATIVE for hidden symbols. */
16549 }
16550 }
16552 /* Allocate stubs for exported Thumb functions on v4t. */
16557 {
16564 /* Create a new symbol to regist the real location of the function. */
16578 /* Point the symbol at the stub. */
16583 }
16588 /* In the shared -Bsymbolic case, discard space allocated for
16589 dynamic pc-relative relocs against symbols which turn out to be
16590 defined in regular objects. For the normal shared case, discard
16591 space for pc-relative relocs that have become local due to symbol
16592 visibility changes. */
16597 {
16598 /* Relocs that use pc_count are PC-relative forms, which will appear
16599 on something like ".long foo - ." or "movw REG, foo - .". We want
16600 calls to protected symbols to resolve directly to the function
16601 rather than going via the plt. If people want function pointer
16602 comparisons to work as expected then they should avoid writing
16603 assembly like ".long foo - .". */
16605 {
16609 {
16614 else
16616 }
16617 }
16620 {
16624 {
16627 else
16629 }
16630 }
16632 /* Also discard relocs on undefined weak syms with non-default
16633 visibility. */
16636 {
16641 /* Make sure undefined weak symbols are output as a dynamic
16642 symbol in PIEs. */
16645 {
16648 }
16649 }
16653 {
16654 /* Output absolute symbols so that we can create relocations
16655 against them. For normal symbols we output a relocation
16656 against the section that contains them. */
16659 }
16661 }
16662 else
16663 {
16664 /* For the non-shared case, discard space for relocs against
16665 symbols which turn out to need copy relocs or are not
16666 dynamic. */
16674 {
16675 /* Make sure this symbol is output as a dynamic symbol.
16676 Undefined weak syms won't yet be marked as dynamic. */
16679 {
16682 }
16684 /* If that succeeded, we know we'll be keeping all the
16685 relocs. */
16688 }
16692 keep: ;
16693 }
16695 /* Finally, allocate space. */
16697 {
16709 else
16711 }
16714 }
16716 void
16719 {
16727 }
16729 /* Set the sizes of the dynamic sections. */
16731 static bool
16734 {
16750 {
16751 /* Set the contents of the .interp section to the interpreter. */
16753 {
16758 }
16759 }
16761 /* Set up .got offsets for local syms, and space for local dynamic
16762 relocs. */
16764 {
16770 bfd_size_type locsymcount;
16780 {
16785 {
16788 {
16789 /* Input section has been discarded, either because
16790 it is a copy of a linkonce section or due to
16791 linker script /DISCARD/, so we'll be discarding
16792 the relocs too. */
16793 }
16797 {
16798 /* Relocations in vxworks .tls_vars sections are
16799 handled specially by the loader. */
16800 }
16802 {
16806 else
16810 }
16811 }
16812 }
16831 {
16838 /* FDPIC support. */
16840 {
16842 {
16846 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16849 else
16851 }
16852 }
16855 {
16857 {
16861 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16864 else
16866 }
16868 /* We will add n R_ARM_RELATIVE relocations or n rofixups. */
16871 else
16873 }
16876 {
16880 {
16885 /* All references to the PLT are calls, so all
16886 non-call references can resolve directly to the
16887 run-time target. This means that the .got entry
16888 would be the same as the .igot.plt entry, so there's
16889 no point creating both. */
16891 }
16892 else
16893 {
16896 }
16899 {
16905 else
16907 }
16908 }
16910 {
16915 /* TLS_GD relocs need an 8-byte structure in the GOT. */
16918 {
16923 /* plt.got_offset needs to know there's a TLS_DESC
16924 reloc in the middle of .got.plt. */
16926 }
16931 {
16932 /* If the symbol is both GD and GDESC, *local_got
16933 may have been overwritten. */
16936 }
16939 symndx);
16943 /* If all references to an STT_GNU_IFUNC PLT are calls,
16944 then all non-call references, including this GOT entry,
16945 resolve directly to the run-time target. */
16951 {
16959 {
16963 }
16964 }
16965 }
16966 else
16968 }
16969 }
16972 {
16973 /* Allocate two GOT entries and one dynamic relocation (if necessary)
16974 for R_ARM_TLS_LDM32/R_ARM_TLS_LDM32_FDPIC relocations. */
16979 }
16980 else
16983 /* At the very end of the .rofixup section is a pointer to the GOT,
16984 reserve space for it. */
16988 /* Allocate global sym .plt and .got entries, and space for global
16989 sym dynamic relocs. */
16992 /* Here we rummage through the found bfds to collect glue information. */
16994 {
16998 /* Initialise mapping tables for code/data. */
17005 }
17007 /* Allocate space for the glue sections now that we've sized them. */
17010 /* For every jump slot reserved in the sgotplt, reloc_count is
17011 incremented. However, when we reserve space for TLS descriptors,
17012 it's not incremented, so in order to compute the space reserved
17013 for them, it suffices to multiply the reloc count by the jump
17014 slot size. */
17019 {
17026 /* If we're not using lazy TLS relocations, don't generate the
17027 PLT and GOT entries they require. */
17030 else
17031 {
17037 }
17038 }
17040 /* The check_relocs and adjust_dynamic_symbol entry points have
17041 determined the sizes of the various dynamic sections. Allocate
17042 memory for them. */
17045 {
17051 /* It's OK to base decisions on the section name, because none
17052 of the dynobj section names depend upon the input files. */
17056 {
17057 /* Remember whether there is a PLT. */
17058 ;
17059 }
17061 {
17063 {
17064 /* Remember whether there are any reloc sections other
17065 than .rel(a).plt and .rela.plt.unloaded. */
17069 /* We use the reloc_count field as a counter if we need
17070 to copy relocs into the output file. */
17072 }
17073 }
17081 {
17082 /* It's not one of our sections, so don't allocate space. */
17084 }
17087 {
17088 /* If we don't need this section, strip it from the
17089 output file. This is mostly to handle .rel(a).bss and
17090 .rel(a).plt. We must create both sections in
17091 create_dynamic_sections, because they must be created
17092 before the linker maps input sections to output
17093 sections. The linker does that before
17094 adjust_dynamic_symbol is called, and it is that
17095 function which decides whether anything needs to go
17096 into these sections. */
17099 }
17104 /* Allocate memory for the section contents. */
17108 }
17111 relocs);
17112 }
17114 /* Size sections even though they're not dynamic. We use it to setup
17115 _TLS_MODULE_BASE_, if needed. */
17117 static bool
17120 {
17132 {
17135 tlsbase = elf_link_hash_lookup
17139 {
17155 }
17156 }
17164 }
17166 /* Finish up dynamic symbol handling. We set the contents of various
17167 dynamic sections here. */
17169 static bool
17174 {
17185 {
17187 {
17192 }
17195 {
17196 /* Mark the symbol as undefined, rather than as defined in
17197 the .plt section. */
17199 /* If the symbol is weak we need to clear the value.
17200 Otherwise, the PLT entry would provide a definition for
17201 the symbol even if the symbol wasn't defined anywhere,
17202 and so the symbol would never be NULL. Leave the value if
17203 there were any relocations where pointer equality matters
17204 (this is a clue for the dynamic linker, to make function
17205 pointer comparisons work between an application and shared
17206 library). */
17209 }
17211 {
17212 /* At least one non-call relocation references this .iplt entry,
17213 so the .iplt entry is the function's canonical address. */
17221 }
17222 }
17225 {
17227 Elf_Internal_Rela rel;
17229 /* This symbol needs a copy reloc. Set it up. */
17241 else
17244 }
17246 /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. On VxWorks,
17247 and for FDPIC, the _GLOBAL_OFFSET_TABLE_ symbol is not absolute:
17248 it is relative to the ".got" section. */
17256 }
17258 static void
17262 {
17266 {
17269 /* Emit mov pc,rx if bx is not permitted. */
17273 }
17274 }
17276 /* Install the special first PLT entry for elf32-arm-nacl. Unlike
17277 other variants, NaCl needs this entry in a static executable's
17278 .iplt too. When we're handling that case, GOT_DISPLACEMENT is
17279 zero. For .iplt really only the last bundle is useful, and .iplt
17280 could have a shorter first entry, with each individual PLT entry's
17281 relative branch calculated differently so it targets the last
17282 bundle instead of the instruction before it (labelled .Lplt_tail
17283 above). But it's simpler to keep the size and layout of PLT0
17284 consistent with the dynamic case, at the cost of some dead code at
17285 the start of .iplt and the one dead store to the stack at the start
17286 of .Lplt_tail. */
17287 static void
17290 {
17306 }
17308 /* Finish up the dynamic sections. */
17310 static bool
17312 {
17325 /* A broken linker script might have discarded the dynamic sections.
17326 Catch this here so that we do not seg-fault later on. */
17332 {
17344 {
17345 Elf_Internal_Dyn dyn;
17352 {
17372 get_vma:
17375 {
17376 _bfd_error_handler
17380 }
17412 /* Set the bottom bit of DT_INIT/FINI if the
17413 corresponding function is Thumb. */
17419 get_sym:
17420 /* If it wasn't set by elf_bfd_final_link
17421 then there is nothing to adjust. */
17423 {
17431 {
17434 }
17435 }
17437 }
17438 }
17440 /* Fill in the first entry in the procedure linkage table. */
17442 {
17446 /* Calculate the addresses of the GOT and PLT. */
17451 {
17452 /* The VxWorks GOT is relocated by the dynamic linker.
17453 Therefore, we must emit relocations rather than simply
17454 computing the values now. */
17455 Elf_Internal_Rela rel;
17466 /* Generate a relocation for _GLOBAL_OFFSET_TABLE_. */
17472 }
17477 {
17489 }
17490 else
17491 {
17504 #ifdef FOUR_WORD_PLT
17505 /* The displacement value goes in the otherwise-unused
17506 last word of the second entry. */
17508 #else
17510 #endif
17511 }
17512 }
17514 /* UnixWare sets the entsize of .plt to 4, although that doesn't
17515 really seem like the right value. */
17520 {
17521 bfd_vma got_address
17525 bfd_vma plt_address
17541 }
17544 {
17548 #ifdef FOUR_WORD_PLT
17551 #endif
17552 }
17557 {
17558 /* Correct the .rel(a).plt.unloaded relocations. They will have
17559 incorrect symbol indexes. */
17568 {
17569 Elf_Internal_Rela rel;
17580 }
17581 }
17582 }
17587 /* NaCl uses a special first entry in .iplt too. */
17590 /* Fill in the first three entries in the global offset table. */
17592 {
17594 {
17597 else
17603 }
17606 }
17608 /* At the very end of the .rofixup section is a pointer to the GOT. */
17610 {
17619 /* Make sure we allocated and generated the same number of fixups. */
17621 }
17624 }
17626 static bool
17628 {
17643 {
17650 }
17654 {
17658 else
17660 }
17662 /* Scan segment to set p_flags attribute if it contains only sections with
17663 SHF_ARM_PURECODE flag. */
17665 {
17671 {
17674 }
17676 {
17679 }
17680 }
17682 }
17684 static enum elf_reloc_type_class
17688 {
17690 {
17701 }
17702 }
17704 static void
17706 {
17708 }
17710 static bool
17712 {
17715 }
17717 /* Return TRUE if this is an unwinding table entry. */
17719 static bool
17721 {
17724 }
17727 /* Set the type and flags for an ARM section. We do this by
17728 the section name, which is a hack, but ought to work. */
17730 static bool
17732 {
17738 {
17741 }
17747 }
17749 /* Handle an ARM specific section when reading an object file. This is
17750 called when bfd_section_from_shdr finds a section with an unknown
17751 type. */
17753 static bool
17758 {
17759 /* There ought to be a place to keep ELF backend specific flags, but
17760 at the moment there isn't one. We just keep track of the
17761 sections by their name, instead. Fortunately, the ABI gives
17762 names for all the ARM specific sections, so we will probably get
17763 away with this. */
17765 {
17773 }
17779 }
17783 {
17786 else
17788 }
17791 {
17800 enum map_symbol_type
17801 {
17802 ARM_MAP_ARM,
17803 ARM_MAP_THUMB,
17804 ARM_MAP_DATA
17805 };
17808 /* Output a single mapping symbol. */
17810 static bool
17813 bfd_vma offset)
17814 {
17816 Elf_Internal_Sym sym;
17828 }
17830 /* Output mapping symbols for the PLT entry described by ROOT_PLT and ARM_PLT.
17831 IS_IPLT_ENTRY_P says whether the PLT is in .iplt rather than .plt. */
17833 static bool
17838 {
17850 {
17853 }
17854 else
17855 {
17858 }
17864 {
17873 }
17875 {
17878 }
17880 {
17882 ? ARM_MAP_THUMB
17895 }
17897 {
17900 }
17901 else
17902 {
17907 {
17910 }
17911 #ifdef FOUR_WORD_PLT
17916 #else
17917 /* A three-word PLT with no Thumb thunk contains only Arm code,
17918 so only need to output a mapping symbol for the first PLT entry and
17919 entries with thumb thunks. */
17921 {
17924 }
17925 #endif
17926 }
17929 }
17931 /* Output mapping symbols for PLT entries associated with H. */
17933 static bool
17935 {
17943 /* When warning symbols are created, they **replace** the "real"
17944 entry in the hash table, thus we never get to see the real
17945 symbol in a hash traversal. So look at it now. */
17951 }
17953 /* Bind a veneered symbol to its veneer identified by its hash entry
17954 STUB_ENTRY. The veneered location thus loose its symbol. */
17956 static void
17958 {
17965 }
17967 /* Output a single local symbol for a generated stub. */
17969 static bool
17972 {
17973 Elf_Internal_Sym sym;
17984 }
17986 static bool
17989 {
17992 bfd_vma addr;
18001 /* Massage our args to the form they really have. */
18007 /* Ensure this stub is attached to the current section being
18008 processed. */
18017 else
18018 {
18021 {
18036 }
18037 }
18042 {
18044 {
18061 }
18064 {
18068 }
18071 {
18088 }
18089 }
18092 }
18094 /* Output mapping symbols for linker generated sections,
18095 and for those data-only sections that do not have a
18096 $d. */
18098 static bool
18103 Elf_Internal_Sym *,
18104 asection *,
18106 {
18107 output_arch_syminfo osi;
18109 bfd_vma offset;
18110 bfd_size_type size;
18123 /* Add a $d mapping symbol to data-only sections that
18124 don't have any mapping symbol. This may result in (harmless) redundant
18125 mapping symbols. */
18129 {
18134 {
18139 == SEC_HAS_CONTENTS
18144 {
18149 }
18150 }
18151 }
18153 /* ARM->Thumb glue. */
18155 {
18157 ARM2THUMB_GLUE_SECTION_NAME);
18166 else
18170 {
18173 }
18174 }
18176 /* Thumb->ARM glue. */
18178 {
18180 THUMB2ARM_GLUE_SECTION_NAME);
18187 {
18190 }
18191 }
18193 /* ARMv4 BX veneers. */
18195 {
18197 ARM_BX_GLUE_SECTION_NAME);
18203 }
18205 /* Long calls stubs. */
18207 {
18213 {
18214 /* Ignore non-stub sections. */
18224 }
18225 }
18227 /* Finally, output mapping symbols for the PLT. */
18229 {
18234 /* Output mapping symbols for the plt header. */
18236 {
18237 /* VxWorks shared libraries have no PLT header. */
18239 {
18244 }
18245 }
18247 {
18250 }
18252 {
18259 }
18261 {
18264 #ifndef FOUR_WORD_PLT
18267 #endif
18268 }
18269 }
18273 {
18274 /* NaCl uses a special first entry in .iplt too. */
18280 }
18283 {
18288 {
18294 {
18297 {
18300 input_bfd,
18302 num_syms);
18304 }
18311 }
18312 }
18313 }
18315 {
18316 /* Mapping symbols for the lazy tls trampoline. */
18324 }
18326 {
18327 /* Mapping symbols for the tls trampoline. */
18330 #ifdef FOUR_WORD_PLT
18334 #endif
18335 }
18338 }
18340 /* Filter normal symbols of CMSE entry functions of ABFD to include in
18341 the import library. All SYMCOUNT symbols of ABFD can be examined
18342 from their pointers in SYMS. Pointers of symbols to keep should be
18343 stored continuously at the beginning of that array.
18345 Returns the number of symbols to keep. */
18347 static unsigned int
18351 {
18366 {
18369 flagword flags;
18384 {
18388 }
18400 }
18406 }
18408 /* Filter symbols of ABFD to include in the import library. All
18409 SYMCOUNT symbols of ABFD can be examined from their pointers in
18410 SYMS. Pointers of symbols to keep should be stored continuously at
18411 the beginning of that array.
18413 Returns the number of symbols to keep. */
18415 static unsigned int
18419 {
18422 /* Requirement 8 of "ARM v8-M Security Extensions: Requirements on
18423 Development Tools" (ARM-ECM-0359818) mandates Secure Gateway import
18424 library to be a relocatable object file. */
18428 else
18430 }
18432 /* Allocate target specific section data. */
18434 static bool
18436 {
18438 {
18446 }
18449 }
18452 /* Used to order a list of mapping symbols by address. */
18454 static int
18456 {
18465 /* Ensure results do not depend on the host qsort for objects with
18466 multiple mapping symbols at the same address by sorting on type
18467 after vma. */
18471 else
18473 }
18475 /* Add OFFSET to lower 31 bits of ADDR, leaving other bits unmodified. */
18477 static unsigned long
18479 {
18481 }
18483 /* Copy an .ARM.exidx table entry, adding OFFSET to (applied) PREL31
18484 relocations. */
18486 static void
18488 {
18492 /* High bit of first word is supposed to be zero. */
18496 /* If the high bit of the first word is clear, and the bit pattern is not 0x1
18497 (EXIDX_CANTUNWIND), this is an offset to an .ARM.extab entry. */
18503 }
18505 /* Data for make_branch_to_a8_stub(). */
18507 struct a8_branch_to_stub_data
18508 {
18511 };
18514 /* Helper to insert branches to Cortex-A8 erratum stubs in the right
18515 places for a particular section. */
18517 static bool
18520 {
18526 bfd_signed_vma branch_offset;
18539 /* We use target_section as Cortex-A8 erratum workaround stubs are only
18540 generated when both source and target are in the same section. */
18557 /* We attempt to avoid this condition by setting stubs_always_after_branch
18558 in elf32_arm_size_stubs if we've enabled the Cortex-A8 erratum workaround.
18559 This check is just to be on the safe side... */
18561 {
18565 }
18568 {
18579 {
18584 jump24:
18586 {
18587 /* There's not much we can do apart from complain if this
18588 happens. */
18592 }
18594 /* i1 = not(j1 eor s), so:
18595 not i1 = j1 eor s
18596 j1 = (not i1) eor s. */
18608 }
18614 }
18620 }
18622 /* Beginning of stm32l4xx work-around. */
18624 /* Functions encoding instructions necessary for the emission of the
18625 fix-stm32l4xx-629360.
18626 Encoding is extracted from the
18627 ARM (C) Architecture Reference Manual
18628 ARMv7-A and ARMv7-R edition
18629 ARM DDI 0406C.b (ID072512). */
18633 {
18634 /* A8.8.18 B (A8-334)
18635 B target_address (Encoding T4). */
18636 /* 1111 - 0Sii - iiii - iiii - 10J1 - Jiii - iiii - iiii. */
18637 /* jump offset is: S:I1:I2:imm10:imm11:0. */
18638 /* with : I1 = NOT (J1 EOR S) I2 = NOT (J2 EOR S). */
18655 }
18659 {
18660 /* A8.8.57 LDM/LDMIA/LDMFD (A8-396)
18661 LDMIA Rn!, {Ra, Rb, Rc, ...} (Encoding T2). */
18668 }
18672 {
18673 /* A8.8.60 LDMDB/LDMEA (A8-402)
18674 LDMDB Rn!, {Ra, Rb, Rc, ...} (Encoding T1). */
18681 }
18685 {
18686 /* A8.8.103 MOV (register) (A8-486)
18687 MOV Rd, Rm (Encoding T1). */
18694 }
18698 {
18699 /* A8.8.221 SUB (immediate) (A8-708)
18700 SUB Rd, Rn, #value (Encoding T3). */
18710 }
18715 {
18716 /* A8.8.332 VLDM (A8-922)
18717 VLMD{MODE} Rn{!}, {list} (Encoding T1 or T2). */
18726 }
18731 {
18732 /* A8.8.332 VLDM (A8-922)
18733 VLMD{MODE} Rn!, {} (Encoding T1 or T2). */
18741 }
18745 {
18746 /* A8.8.247 UDF (A8-758)
18747 Undefined (Encoding T2). */
18753 }
18757 {
18758 /* A8.8.247 UDF (A8-758)
18759 Undefined (Encoding T1). */
18764 }
18766 /* Functions writing an instruction in memory, returning the next
18767 memory position to write to. */
18772 {
18775 }
18780 {
18783 }
18785 /* Function filling up a region in memory with T1 and T2 UDFs taking
18786 care of alignment. */
18794 {
18797 /* Fill the remaining of the stub with deterministic contents : UDF
18798 instructions.
18799 Check if realignment is needed on modulo 4 frontier using T1, to
18800 further use T2. */
18804 current_stub_contents =
18809 current_stub_contents =
18814 }
18816 /* Functions writing the stream of instructions equivalent to the
18817 derived sequence for ldmia, ldmdb, vldm respectively. */
18819 static void
18825 {
18838 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
18839 smaller than 8 registers load sequences that do not cause the
18840 hardware issue. */
18842 {
18843 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
18844 current_stub_contents =
18846 initial_insn);
18848 /* B initial_insn_addr+4. */
18850 current_stub_contents =
18852 create_instruction_branch_absolute
18855 /* Fill the remaining of the stub with deterministic contents. */
18856 current_stub_contents =
18859 base_stub_contents +
18860 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18863 }
18865 /* - reg_list[13] == 0. */
18868 /* - reg_list[14] & reg_list[15] != 1. */
18871 /* - if (wback==1) reg_list[rn] == 0. */
18874 /* - nb_registers > 8. */
18877 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
18879 /* In the following algorithm, we split this wide LDM using 2 LDM insns:
18880 - One with the 7 lowest registers (register mask 0x007F)
18881 This LDM will finally contain between 2 and 7 registers
18882 - One with the 7 highest registers (register mask 0xDF80)
18883 This ldm will finally contain between 2 and 7 registers. */
18887 /* A spare register may be needed during this veneer to temporarily
18888 handle the base register. This register will be restored with the
18889 last LDM operation.
18890 The usable register may be any general purpose register (that
18891 excludes PC, SP, LR : register mask is 0x1FFF). */
18894 /* Generate the stub function. */
18896 {
18897 /* LDMIA Rn!, {R-low-register-list} : (Encoding T2). */
18898 current_stub_contents =
18900 create_instruction_ldmia
18903 /* LDMIA Rn!, {R-high-register-list} : (Encoding T2). */
18904 current_stub_contents =
18906 create_instruction_ldmia
18909 {
18910 /* B initial_insn_addr+4. */
18911 current_stub_contents =
18913 create_instruction_branch_absolute
18915 }
18916 }
18918 {
18921 /* If Rn is not part of the high-register-list, move it there. */
18923 {
18924 /* Choose a Ri in the high-register-list that will be restored. */
18927 /* MOV Ri, Rn. */
18928 current_stub_contents =
18931 }
18933 /* LDMIA Ri!, {R-low-register-list} : (Encoding T2). */
18934 current_stub_contents =
18936 create_instruction_ldmia
18939 /* LDMIA Ri, {R-high-register-list} : (Encoding T2). */
18940 current_stub_contents =
18942 create_instruction_ldmia
18946 {
18947 /* B initial_insn_addr+4. */
18948 current_stub_contents =
18950 create_instruction_branch_absolute
18952 }
18953 }
18955 /* Fill the remaining of the stub with deterministic contents. */
18956 current_stub_contents =
18959 base_stub_contents +
18960 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18961 }
18963 static void
18969 {
18982 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
18983 smaller than 8 registers load sequences that do not cause the
18984 hardware issue. */
18986 {
18987 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
18988 current_stub_contents =
18990 initial_insn);
18992 /* B initial_insn_addr+4. */
18993 current_stub_contents =
18995 create_instruction_branch_absolute
18998 /* Fill the remaining of the stub with deterministic contents. */
18999 current_stub_contents =
19002 base_stub_contents +
19003 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19006 }
19008 /* - reg_list[13] == 0. */
19011 /* - reg_list[14] & reg_list[15] != 1. */
19014 /* - if (wback==1) reg_list[rn] == 0. */
19017 /* - nb_registers > 8. */
19020 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
19022 /* In the following algorithm, we split this wide LDM using 2 LDM insn:
19023 - One with the 7 lowest registers (register mask 0x007F)
19024 This LDM will finally contain between 2 and 7 registers
19025 - One with the 7 highest registers (register mask 0xDF80)
19026 This ldm will finally contain between 2 and 7 registers. */
19030 /* A spare register may be needed during this veneer to temporarily
19031 handle the base register. This register will be restored with
19032 the last LDM operation.
19033 The usable register may be any general purpose register (that excludes
19034 PC, SP, LR : register mask is 0x1FFF). */
19037 /* Generate the stub function. */
19039 {
19040 /* Choose a Ri in the low-register-list that will be restored. */
19043 /* MOV Ri, Rn. */
19044 current_stub_contents =
19048 /* LDMDB Ri!, {R-high-register-list}. */
19049 current_stub_contents =
19051 create_instruction_ldmdb
19054 /* LDMDB Ri, {R-low-register-list}. */
19055 current_stub_contents =
19057 create_instruction_ldmdb
19060 /* B initial_insn_addr+4. */
19061 current_stub_contents =
19063 create_instruction_branch_absolute
19065 }
19067 {
19068 /* LDMDB Rn!, {R-high-register-list}. */
19069 current_stub_contents =
19071 create_instruction_ldmdb
19074 /* LDMDB Rn!, {R-low-register-list}. */
19075 current_stub_contents =
19077 create_instruction_ldmdb
19080 /* B initial_insn_addr+4. */
19081 current_stub_contents =
19083 create_instruction_branch_absolute
19085 }
19087 {
19088 /* Choose a Ri in the high-register-list that will be restored. */
19091 /* SUB Ri, Rn, #(4*nb_registers). */
19092 current_stub_contents =
19096 /* LDMIA Ri!, {R-low-register-list}. */
19097 current_stub_contents =
19099 create_instruction_ldmia
19102 /* LDMIA Ri, {R-high-register-list}. */
19103 current_stub_contents =
19105 create_instruction_ldmia
19107 }
19109 {
19110 /* Choose a Ri in the high-register-list that will be restored. */
19113 /* SUB Rn, Rn, #(4*nb_registers) */
19114 current_stub_contents =
19118 /* MOV Ri, Rn. */
19119 current_stub_contents =
19123 /* LDMIA Ri!, {R-low-register-list}. */
19124 current_stub_contents =
19126 create_instruction_ldmia
19129 /* LDMIA Ri, {R-high-register-list}. */
19130 current_stub_contents =
19132 create_instruction_ldmia
19134 }
19136 {
19139 {
19140 /* Choose a Ri in the low-register-list that will be restored. */
19143 /* MOV Ri, Rn. */
19144 current_stub_contents =
19147 }
19149 /* LDMDB Ri!, {R-high-register-list}. */
19150 current_stub_contents =
19152 create_instruction_ldmdb
19155 /* LDMDB Ri, {R-low-register-list}. */
19156 current_stub_contents =
19158 create_instruction_ldmdb
19161 /* B initial_insn_addr+4. */
19162 current_stub_contents =
19164 create_instruction_branch_absolute
19166 }
19168 {
19171 {
19172 /* Choose a Ri in the high-register-list that will be restored. */
19174 }
19176 /* SUB Ri, Rn, #(4*nb_registers). */
19177 current_stub_contents =
19181 /* LDMIA Ri!, {R-low-register-list}. */
19182 current_stub_contents =
19184 create_instruction_ldmia
19187 /* LDMIA Ri, {R-high-register-list}. */
19188 current_stub_contents =
19190 create_instruction_ldmia
19192 }
19194 {
19195 /* The assembler should not have accepted to encode this. */
19198 }
19200 /* Fill the remaining of the stub with deterministic contents. */
19201 current_stub_contents =
19204 base_stub_contents +
19205 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19207 }
19209 static void
19215 {
19221 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
19222 smaller than 8 words load sequences that do not cause the
19223 hardware issue. */
19225 {
19226 /* Untouched instruction. */
19227 current_stub_contents =
19229 initial_insn);
19231 /* B initial_insn_addr+4. */
19232 current_stub_contents =
19234 create_instruction_branch_absolute
19236 }
19237 else
19238 {
19248 /* d = UInt (Vd:D);. */
19252 /* Compute the number of 8-words chunks needed to split. */
19256 /* The test coverage has been done assuming the following
19257 hypothesis that exactly one of the previous is_ predicates is
19258 true. */
19262 /* We treat the cutting of the words in one pass for all
19263 cases, then we emit the adjustments:
19265 vldm rx, {...}
19266 -> vldm rx!, {8_words_or_less} for each needed 8_word
19267 -> sub rx, rx, #size (list)
19269 vldm rx!, {...}
19270 -> vldm rx!, {8_words_or_less} for each needed 8_word
19271 This also handles vpop instruction (when rx is sp)
19273 vldmd rx!, {...}
19274 -> vldmb rx!, {8_words_or_less} for each needed 8_word. */
19276 {
19280 {
19281 new_insn = create_instruction_vldmia
19283 is_dp,
19288 }
19290 {
19291 new_insn = create_instruction_vldmdb
19293 is_dp,
19297 }
19300 current_stub_contents =
19302 new_insn);
19303 }
19305 /* Only this case requires the base register compensation
19306 subtract. */
19308 {
19309 current_stub_contents =
19311 create_instruction_sub
19313 }
19315 /* B initial_insn_addr+4. */
19316 current_stub_contents =
19318 create_instruction_branch_absolute
19320 }
19322 /* Fill the remaining of the stub with deterministic contents. */
19323 current_stub_contents =
19326 base_stub_contents +
19327 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
19328 }
19330 static void
19336 {
19340 stub_contents);
19344 stub_contents);
19348 stub_contents);
19349 }
19351 /* End of stm32l4xx work-around. */
19354 /* Do code byteswapping. Return FALSE afterwards so that the section is
19355 written out as normal. */
19357 static bool
19362 {
19369 bfd_vma ptr;
19370 bfd_vma end;
19372 bfd_byte tmp;
19378 /* If this section has not been allocated an _arm_elf_section_data
19379 structure then we cannot record anything. */
19389 {
19394 {
19398 {
19400 {
19401 bfd_vma branch_to_veneer;
19402 /* Original condition code of instruction, plus bit mask for
19403 ARM B instruction. */
19407 /* The instruction is before the label. */
19410 /* Above offset included in -4 below. */
19424 }
19428 {
19429 bfd_vma branch_from_veneer;
19432 /* Take size of veneer into account. */
19441 /* Original instruction. */
19448 /* Branch back to insn after original insn. */
19454 }
19459 }
19460 }
19461 }
19464 {
19468 {
19472 {
19474 {
19476 bfd_vma branch_to_veneer =
19481 {
19482 bfd_vma out_of_range =
19488 _bfd_error_handler
19490 "cannot create STM32L4XX veneer; "
19493 output_bfd,
19497 }
19499 insn = create_instruction_branch_absolute
19502 /* The instruction is before the label. */
19507 }
19511 {
19517 veneer_r = veneer
19522 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE >
19523 STM32L4XX_ERRATUM_LDM_VENEER_SIZE ?
19524 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE :
19527 {
19531 }
19533 /* Original instruction. */
19536 stm32l4xx_create_replacing_stub
19538 }
19543 }
19544 }
19545 }
19548 {
19549 arm_unwind_table_edit *edit_node
19551 /* Now, sec->size is the size of the section we will write. The original
19552 size (before we merged duplicate entries and inserted EXIDX_CANTUNWIND
19553 markers) was sec->rawsize. (This isn't the case if we perform no
19554 edits, then rawsize will be zero and we should use size). */
19563 {
19565 {
19569 {
19572 out_index++;
19573 in_index++;
19574 }
19578 {
19580 {
19582 in_index++;
19587 {
19595 /* Note: this is meant to be equivalent to an
19596 R_ARM_PREL31 relocation. These synthetic
19597 EXIDX_CANTUNWIND markers are not relocated by the
19598 usual BFD method. */
19602 {
19603 /* Here relocation for new EXIDX_CANTUNWIND is
19604 created, so there is no need to
19605 adjust offset by hand. */
19608 }
19610 /* First address we can't unwind. */
19614 /* Code for EXIDX_CANTUNWIND. */
19618 out_index++;
19620 }
19622 }
19625 }
19626 }
19627 else
19628 {
19629 /* No more edits, copy remaining entries verbatim. */
19632 out_index++;
19633 in_index++;
19634 }
19635 }
19639 edited_contents,
19643 }
19645 /* Fix code to point to Cortex-A8 erratum stubs. */
19647 {
19655 }
19661 {
19666 {
19669 else
19673 {
19675 /* Byte swap code words. */
19677 {
19685 }
19689 /* Byte swap code halfwords. */
19691 {
19696 }
19700 /* Leave data alone. */
19702 }
19704 }
19705 }
19713 }
19715 /* Mangle thumb function symbols as we read them in. */
19717 static bool
19722 {
19727 /* New EABI objects mark thumb function symbols by setting the low bit of
19728 the address. */
19731 {
19733 {
19736 ST_BRANCH_TO_THUMB);
19737 }
19738 else
19740 }
19742 {
19745 }
19748 else
19752 }
19755 /* Mangle thumb function symbols as we write them out. */
19757 static void
19762 {
19763 Elf_Internal_Sym newsym;
19765 /* We convert STT_ARM_TFUNC symbols into STT_FUNC with the low bit
19766 of the address set, as per the new EABI. We do this unconditionally
19767 because objcopy does not set the elf header flags until after
19768 it writes out the symbol table. */
19770 {
19775 {
19776 /* Do this only for defined symbols. At link type, the static
19777 linker will simulate the work of dynamic linker of resolving
19778 symbols and will carry over the thumbness of found symbols to
19779 the output symbol table. It's not clear how it happens, but
19780 the thumbness of undefined symbols can well be different at
19781 runtime, and writing '1' for them will be confusing for users
19782 and possibly for dynamic linker itself.
19783 */
19785 }
19788 }
19790 }
19792 /* Add the PT_ARM_EXIDX program header. */
19794 static bool
19797 {
19803 {
19804 /* If there is already a PT_ARM_EXIDX header, then we do not
19805 want to add another one. This situation arises when running
19806 "strip"; the input binary already has the header. */
19811 {
19822 }
19823 }
19826 }
19828 /* We may add a PT_ARM_EXIDX program header. */
19830 static int
19833 {
19839 else
19841 }
19843 /* Hook called by the linker routine which adds symbols from an object
19844 file. */
19846 static bool
19850 {
19860 }
19862 /* We use this to override swap_symbol_in and swap_symbol_out. */
19864 {
19877 bfd_elf32_write_out_phdrs,
19878 bfd_elf32_write_shdrs_and_ehdr,
19879 bfd_elf32_checksum_contents,
19880 bfd_elf32_write_relocs,
19881 elf32_arm_swap_symbol_in,
19882 elf32_arm_swap_symbol_out,
19883 bfd_elf32_slurp_reloc_table,
19884 bfd_elf32_slurp_symbol_table,
19885 bfd_elf32_swap_dyn_in,
19886 bfd_elf32_swap_dyn_out,
19887 bfd_elf32_swap_reloc_in,
19888 bfd_elf32_swap_reloc_out,
19889 bfd_elf32_swap_reloca_in,
19890 bfd_elf32_swap_reloca_out
19891 };
19893 static bfd_vma
19895 {
19896 /* V7 BE8 code is always little endian. */
19901 }
19903 static bfd_vma
19905 {
19906 /* V7 BE8 code is always little endian. */
19911 }
19913 /* Return size of plt0 entry starting at ADDR
19914 or (bfd_vma) -1 if size can not be determined. */
19916 static bfd_vma
19918 {
19919 bfd_vma first_word;
19920 bfd_vma plt0_size;
19928 else
19929 /* We don't yet handle this PLT format. */
19933 }
19935 /* Return size of plt entry starting at offset OFFSET
19936 of plt section located at address START
19937 or (bfd_vma) -1 if size can not be determined. */
19939 static bfd_vma
19941 {
19942 bfd_vma first_insn;
19946 /* PLT entry size if fixed on Thumb-only platforms. */
19950 /* Respect Thumb stub if necessary. */
19952 {
19954 }
19956 /* Strip immediate from first add. */
19959 #ifdef FOUR_WORD_PLT
19962 #else
19967 #endif
19968 else
19969 /* We don't yet handle this PLT format. */
19973 }
19975 /* Implementation is shamelessly borrowed from _bfd_elf_get_synthetic_symtab. */
19977 static long
19984 {
19993 bfd_vma offset;
20022 {
20026 }
20032 {
20036 }
20050 {
20058 /* Undefined syms won't have BSF_LOCAL or BSF_GLOBAL set. Since
20059 we are defining a symbol, ensure one of them is set. */
20071 {
20078 ;
20082 }
20087 }
20090 }
20092 static bool
20094 {
20098 }
20100 static flagword
20102 {
20107 }
20109 static unsigned int
20111 {
20116 }
20118 /* Called to set the sh_flags, sh_link and sh_info fields of OSECTION which
20119 has a type >= SHT_LOOS. Returns TRUE if these fields were initialised
20120 FALSE otherwise. ISECTION is the best guess matching section from the
20121 input bfd IBFD, but it might be NULL. */
20123 static bool
20128 {
20130 {
20132 {
20140 /* The sh_link field must be set to the text section associated with
20141 this index section. Unfortunately the ARM EHABI does not specify
20142 exactly how to determine this association. Our caller does try
20143 to match up OSECTION with its corresponding input section however
20144 so that is a good first guess. */
20155 )
20156 {
20161 }
20164 {
20165 /* Failing that we have to find a matching section ourselves. If
20166 we had the output section name available we could compare that
20167 with input section names. Unfortunately we don't. So instead
20168 we use a simple heuristic and look for the nearest executable
20169 section before this one. */
20181 }
20184 {
20186 /* If the text section was part of a group
20187 then the index section should be too. */
20191 }
20192 }
20204 }
20207 }
20209 /* Returns TRUE if NAME is an ARM mapping symbol.
20210 Traditionally the symbols $a, $d and $t have been used.
20211 The ARM ELF standard also defines $x (for A64 code). It also allows a
20212 period initiated suffix to be added to the symbol: "$[adtx]\.[:sym_char]+".
20213 Other tools might also produce $b (Thumb BL), $f, $p, $m and $v, but we do
20214 not support them here. $t.x indicates the start of ThumbEE instructions. */
20216 static bool
20218 {
20221 the mapping symbols could have acquired a prefix.
20222 We do not support this here, since such symbols no
20223 longer conform to the ARM ELF ABI. */
20226 /* FIXME: Strictly speaking the symbol is only a valid mapping symbol if
20227 any characters that follow the period are legal characters for the body
20228 of a symbol's name. For now we just assume that this is the case. */
20229 }
20231 /* Make sure that mapping symbols in object files are not removed via the
20232 "strip --strip-unneeded" tool. These symbols are needed in order to
20233 correctly generate interworking veneers, and for byte swapping code
20234 regions. Once an object file has been linked, it is safe to remove the
20235 symbols as they will no longer be needed. */
20237 static void
20239 {
20244 }
20246 #undef elf_backend_copy_special_section_fields
20247 #define elf_backend_copy_special_section_fields elf32_arm_copy_special_section_fields
20249 #define ELF_ARCH bfd_arch_arm
20250 #define ELF_TARGET_ID ARM_ELF_DATA
20251 #define ELF_MACHINE_CODE EM_ARM
20252 #ifdef __QNXTARGET__
20253 #define ELF_MAXPAGESIZE 0x1000
20254 #else
20255 #define ELF_MAXPAGESIZE 0x10000
20256 #endif
20257 #define ELF_COMMONPAGESIZE 0x1000
20259 #define bfd_elf32_mkobject elf32_arm_mkobject
20261 #define bfd_elf32_bfd_copy_private_bfd_data elf32_arm_copy_private_bfd_data
20262 #define bfd_elf32_bfd_merge_private_bfd_data elf32_arm_merge_private_bfd_data
20263 #define bfd_elf32_bfd_set_private_flags elf32_arm_set_private_flags
20264 #define bfd_elf32_bfd_print_private_bfd_data elf32_arm_print_private_bfd_data
20265 #define bfd_elf32_bfd_link_hash_table_create elf32_arm_link_hash_table_create
20266 #define bfd_elf32_bfd_reloc_type_lookup elf32_arm_reloc_type_lookup
20267 #define bfd_elf32_bfd_reloc_name_lookup elf32_arm_reloc_name_lookup
20268 #define bfd_elf32_find_inliner_info elf32_arm_find_inliner_info
20269 #define bfd_elf32_new_section_hook elf32_arm_new_section_hook
20270 #define bfd_elf32_bfd_is_target_special_symbol elf32_arm_is_target_special_symbol
20271 #define bfd_elf32_bfd_final_link elf32_arm_final_link
20272 #define bfd_elf32_get_synthetic_symtab elf32_arm_get_synthetic_symtab
20274 #define elf_backend_get_symbol_type elf32_arm_get_symbol_type
20275 #define elf_backend_maybe_function_sym elf32_arm_maybe_function_sym
20276 #define elf_backend_gc_mark_hook elf32_arm_gc_mark_hook
20277 #define elf_backend_gc_mark_extra_sections elf32_arm_gc_mark_extra_sections
20278 #define elf_backend_check_relocs elf32_arm_check_relocs
20279 #define elf_backend_update_relocs elf32_arm_update_relocs
20280 #define elf_backend_relocate_section elf32_arm_relocate_section
20281 #define elf_backend_write_section elf32_arm_write_section
20282 #define elf_backend_adjust_dynamic_symbol elf32_arm_adjust_dynamic_symbol
20283 #define elf_backend_create_dynamic_sections elf32_arm_create_dynamic_sections
20284 #define elf_backend_finish_dynamic_symbol elf32_arm_finish_dynamic_symbol
20285 #define elf_backend_finish_dynamic_sections elf32_arm_finish_dynamic_sections
20286 #define elf_backend_size_dynamic_sections elf32_arm_size_dynamic_sections
20287 #define elf_backend_always_size_sections elf32_arm_always_size_sections
20288 #define elf_backend_init_index_section _bfd_elf_init_2_index_sections
20289 #define elf_backend_init_file_header elf32_arm_init_file_header
20290 #define elf_backend_reloc_type_class elf32_arm_reloc_type_class
20291 #define elf_backend_object_p elf32_arm_object_p
20292 #define elf_backend_fake_sections elf32_arm_fake_sections
20293 #define elf_backend_section_from_shdr elf32_arm_section_from_shdr
20294 #define elf_backend_final_write_processing elf32_arm_final_write_processing
20295 #define elf_backend_copy_indirect_symbol elf32_arm_copy_indirect_symbol
20296 #define elf_backend_size_info elf32_arm_size_info
20297 #define elf_backend_modify_segment_map elf32_arm_modify_segment_map
20298 #define elf_backend_additional_program_headers elf32_arm_additional_program_headers
20299 #define elf_backend_output_arch_local_syms elf32_arm_output_arch_local_syms
20300 #define elf_backend_filter_implib_symbols elf32_arm_filter_implib_symbols
20301 #define elf_backend_begin_write_processing elf32_arm_begin_write_processing
20302 #define elf_backend_add_symbol_hook elf32_arm_add_symbol_hook
20303 #define elf_backend_count_additional_relocs elf32_arm_count_additional_relocs
20304 #define elf_backend_symbol_processing elf32_arm_backend_symbol_processing
20306 #define elf_backend_can_refcount 1
20307 #define elf_backend_can_gc_sections 1
20308 #define elf_backend_plt_readonly 1
20309 #define elf_backend_want_got_plt 1
20310 #define elf_backend_want_plt_sym 0
20311 #define elf_backend_want_dynrelro 1
20312 #define elf_backend_may_use_rel_p 1
20313 #define elf_backend_may_use_rela_p 0
20314 #define elf_backend_default_use_rela_p 0
20315 #define elf_backend_dtrel_excludes_plt 1
20317 #define elf_backend_got_header_size 12
20318 #define elf_backend_extern_protected_data 0
20320 #undef elf_backend_obj_attrs_vendor
20322 #undef elf_backend_obj_attrs_section
20324 #undef elf_backend_obj_attrs_arg_type
20325 #define elf_backend_obj_attrs_arg_type elf32_arm_obj_attrs_arg_type
20326 #undef elf_backend_obj_attrs_section_type
20327 #define elf_backend_obj_attrs_section_type SHT_ARM_ATTRIBUTES
20328 #define elf_backend_obj_attrs_order elf32_arm_obj_attrs_order
20329 #define elf_backend_obj_attrs_handle_unknown elf32_arm_obj_attrs_handle_unknown
20331 #undef elf_backend_section_flags
20332 #define elf_backend_section_flags elf32_arm_section_flags
20333 #undef elf_backend_lookup_section_flags_hook
20334 #define elf_backend_lookup_section_flags_hook elf32_arm_lookup_section_flags
20336 #define elf_backend_linux_prpsinfo32_ugid16 true
20340 /* Native Client targets. */
20342 #undef TARGET_LITTLE_SYM
20343 #define TARGET_LITTLE_SYM arm_elf32_nacl_le_vec
20344 #undef TARGET_LITTLE_NAME
20346 #undef TARGET_BIG_SYM
20347 #define TARGET_BIG_SYM arm_elf32_nacl_be_vec
20348 #undef TARGET_BIG_NAME
20351 /* Like elf32_arm_link_hash_table_create -- but overrides
20352 appropriately for NaCl. */
20356 {
20361 {
20367 }
20369 }
20371 /* Since NaCl doesn't use the ARM-specific unwind format, we don't
20372 really need to use elf32_arm_modify_segment_map. But we do it
20373 anyway just to reduce gratuitous differences with the stock ARM backend. */
20375 static bool
20377 {
20380 }
20382 static bool
20384 {
20387 }
20389 static bfd_vma
20392 {
20396 }
20398 #undef elf32_bed
20399 #define elf32_bed elf32_arm_nacl_bed
20400 #undef bfd_elf32_bfd_link_hash_table_create
20401 #define bfd_elf32_bfd_link_hash_table_create \
20402 elf32_arm_nacl_link_hash_table_create
20403 #undef elf_backend_plt_alignment
20404 #define elf_backend_plt_alignment 4
20405 #undef elf_backend_modify_segment_map
20406 #define elf_backend_modify_segment_map elf32_arm_nacl_modify_segment_map
20407 #undef elf_backend_modify_headers
20408 #define elf_backend_modify_headers nacl_modify_headers
20409 #undef elf_backend_final_write_processing
20410 #define elf_backend_final_write_processing elf32_arm_nacl_final_write_processing
20411 #undef bfd_elf32_get_synthetic_symtab
20412 #undef elf_backend_plt_sym_val
20413 #define elf_backend_plt_sym_val elf32_arm_nacl_plt_sym_val
20414 #undef elf_backend_copy_special_section_fields
20416 #undef ELF_MINPAGESIZE
20417 #undef ELF_COMMONPAGESIZE
20419 #undef ELF_TARGET_OS
20420 #define ELF_TARGET_OS is_nacl
20424 /* Reset to defaults. */
20425 #undef elf_backend_plt_alignment
20426 #undef elf_backend_modify_segment_map
20427 #define elf_backend_modify_segment_map elf32_arm_modify_segment_map
20428 #undef elf_backend_modify_headers
20429 #undef elf_backend_final_write_processing
20430 #define elf_backend_final_write_processing elf32_arm_final_write_processing
20431 #undef ELF_MINPAGESIZE
20432 #undef ELF_COMMONPAGESIZE
20433 #define ELF_COMMONPAGESIZE 0x1000
20436 /* FDPIC Targets. */
20438 #undef TARGET_LITTLE_SYM
20439 #define TARGET_LITTLE_SYM arm_elf32_fdpic_le_vec
20440 #undef TARGET_LITTLE_NAME
20442 #undef TARGET_BIG_SYM
20443 #define TARGET_BIG_SYM arm_elf32_fdpic_be_vec
20444 #undef TARGET_BIG_NAME
20446 #undef elf_match_priority
20447 #define elf_match_priority 128
20448 #undef ELF_OSABI
20449 #define ELF_OSABI ELFOSABI_ARM_FDPIC
20451 /* Like elf32_arm_link_hash_table_create -- but overrides
20452 appropriately for FDPIC. */
20456 {
20461 {
20465 }
20467 }
20469 /* We need dynamic symbols for every section, since segments can
20470 relocate independently. */
20471 static bool
20474 ATTRIBUTE_UNUSED,
20476 {
20478 {
20481 /* If sh_type is yet undecided, assume it could be
20482 SHT_PROGBITS/SHT_NOBITS. */
20486 /* There shouldn't be section relative relocations
20487 against any other section. */
20490 }
20491 }
20493 #undef elf32_bed
20494 #define elf32_bed elf32_arm_fdpic_bed
20496 #undef bfd_elf32_bfd_link_hash_table_create
20497 #define bfd_elf32_bfd_link_hash_table_create elf32_arm_fdpic_link_hash_table_create
20499 #undef elf_backend_omit_section_dynsym
20500 #define elf_backend_omit_section_dynsym elf32_arm_fdpic_omit_section_dynsym
20502 #undef ELF_TARGET_OS
20506 #undef elf_match_priority
20507 #undef ELF_OSABI
20508 #undef elf_backend_omit_section_dynsym
20510 /* VxWorks Targets. */
20512 #undef TARGET_LITTLE_SYM
20513 #define TARGET_LITTLE_SYM arm_elf32_vxworks_le_vec
20514 #undef TARGET_LITTLE_NAME
20516 #undef TARGET_BIG_SYM
20517 #define TARGET_BIG_SYM arm_elf32_vxworks_be_vec
20518 #undef TARGET_BIG_NAME
20521 /* Like elf32_arm_link_hash_table_create -- but overrides
20522 appropriately for VxWorks. */
20526 {
20531 {
20535 }
20537 }
20539 static bool
20541 {
20544 }
20546 #undef elf32_bed
20547 #define elf32_bed elf32_arm_vxworks_bed
20549 #undef bfd_elf32_bfd_link_hash_table_create
20550 #define bfd_elf32_bfd_link_hash_table_create elf32_arm_vxworks_link_hash_table_create
20551 #undef elf_backend_final_write_processing
20552 #define elf_backend_final_write_processing elf32_arm_vxworks_final_write_processing
20553 #undef elf_backend_emit_relocs
20554 #define elf_backend_emit_relocs elf_vxworks_emit_relocs
20556 #undef elf_backend_may_use_rel_p
20557 #define elf_backend_may_use_rel_p 0
20558 #undef elf_backend_may_use_rela_p
20559 #define elf_backend_may_use_rela_p 1
20560 #undef elf_backend_default_use_rela_p
20561 #define elf_backend_default_use_rela_p 1
20562 #undef elf_backend_want_plt_sym
20563 #define elf_backend_want_plt_sym 1
20564 #undef ELF_MAXPAGESIZE
20565 #define ELF_MAXPAGESIZE 0x1000
20566 #undef ELF_TARGET_OS
20567 #define ELF_TARGET_OS is_vxworks
20572 /* Merge backend specific data from an object file to the output
20573 object file when linking. */
20575 static bool
20577 {
20579 flagword out_flags;
20580 flagword in_flags;
20584 /* Check if we have the same endianness. */
20594 /* The input BFD must have had its flags initialised. */
20595 /* The following seems bogus to me -- The flags are initialized in
20596 the assembler but I don't think an elf_flags_init field is
20597 written into the object. */
20598 /* BFD_ASSERT (elf_flags_init (ibfd)); */
20603 /* In theory there is no reason why we couldn't handle this. However
20604 in practice it isn't even close to working and there is no real
20605 reason to want it. */
20609 {
20611 ibfd);
20613 }
20616 {
20617 /* If the input is the default architecture and had the default
20618 flags then do not bother setting the flags for the output
20619 architecture, instead allow future merges to do this. If no
20620 future merges ever set these flags then they will retain their
20621 uninitialised values, which surprise surprise, correspond
20622 to the default values. */
20635 }
20637 /* Determine what should happen if the input ARM architecture
20638 does not match the output ARM architecture. */
20642 /* Identical flags must be compatible. */
20646 /* Check to see if the input BFD actually contains any sections. If
20647 not, its flags may not have been initialised either, but it
20648 cannot actually cause any incompatiblity. Do not short-circuit
20649 dynamic objects; their section list may be emptied by
20650 elf_link_add_object_symbols.
20652 Also check to see if there are no code sections in the input.
20653 In this case there is no need to check for code specific flags.
20654 XXX - do we need to worry about floating-point format compatability
20655 in data sections ? */
20657 {
20662 {
20663 /* Ignore synthetic glue sections. */
20666 {
20674 }
20675 }
20679 }
20681 /* Complain about various flag mismatches. */
20684 {
20685 _bfd_error_handler
20690 }
20692 /* Not sure what needs to be checked for EABI versions >= 1. */
20693 /* VxWorks libraries do not use these flags. */
20697 {
20699 {
20700 _bfd_error_handler
20705 }
20708 {
20710 _bfd_error_handler
20711 (_("error: %pB passes floats in float registers, whereas %pB passes them in integer registers"),
20713 else
20714 _bfd_error_handler
20715 (_("error: %pB passes floats in integer registers, whereas %pB passes them in float registers"),
20719 }
20722 {
20724 _bfd_error_handler
20727 else
20728 _bfd_error_handler
20733 }
20736 {
20738 _bfd_error_handler
20741 else
20742 _bfd_error_handler
20747 }
20749 #ifdef EF_ARM_SOFT_FLOAT
20751 {
20752 /* We can allow interworking between code that is VFP format
20753 layout, and uses either soft float or integer regs for
20754 passing floating point arguments and results. We already
20755 know that the APCS_FLOAT flags match; similarly for VFP
20756 flags. */
20759 {
20761 _bfd_error_handler
20764 else
20765 _bfd_error_handler
20770 }
20771 }
20772 #endif
20774 /* Interworking mismatch is only a warning. */
20776 {
20778 {
20779 _bfd_error_handler
20782 }
20783 else
20784 {
20785 _bfd_error_handler
20788 }
20789 }
20790 }
20793 }