1 /* BFD back-end for Renesas Super-H COFF binaries.
2 Copyright (C) 1993-2023 Free Software Foundation, Inc.
3 Contributed by Cygnus Support.
4 Written by Steve Chamberlain, <sac@cygnus.com>.
5 Relaxing code written by Ian Lance Taylor, <ian@cygnus.com>.
7 This file is part of BFD, the Binary File Descriptor library.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
22 MA 02110-1301, USA. */
26 #include "libiberty.h"
30 #include "coff/internal.h"
32 #undef bfd_pe_print_pdata
37 #ifndef COFF_IMAGE_WITH_PE
38 static bool sh_align_load_span
39 (bfd
*, asection
*, bfd_byte
*,
40 bool (*) (bfd
*, asection
*, void *, bfd_byte
*, bfd_vma
),
41 void *, bfd_vma
**, bfd_vma
*, bfd_vma
, bfd_vma
, bool *);
43 #define _bfd_sh_align_load_span sh_align_load_span
46 #define bfd_pe_print_pdata _bfd_pe_print_ce_compressed_pdata
50 #define bfd_pe_print_pdata NULL
52 #endif /* COFF_WITH_PE. */
56 /* Internal functions. */
59 /* Can't build import tables with 2**4 alignment. */
60 #define COFF_DEFAULT_SECTION_ALIGNMENT_POWER 2
62 /* Default section alignment to 2**4. */
63 #define COFF_DEFAULT_SECTION_ALIGNMENT_POWER 4
66 #ifdef COFF_IMAGE_WITH_PE
67 /* Align PE executables. */
68 #define COFF_PAGE_SIZE 0x1000
71 /* Generate long file names. */
72 #define COFF_LONG_FILENAMES
75 /* Return TRUE if this relocation should
76 appear in the output .reloc section. */
79 in_reloc_p (bfd
* abfd ATTRIBUTE_UNUSED
,
80 reloc_howto_type
* howto
)
82 return ! howto
->pc_relative
&& howto
->type
!= R_SH_IMAGEBASE
;
86 static bfd_reloc_status_type
87 sh_reloc (bfd
*, arelent
*, asymbol
*, void *, asection
*, bfd
*, char **);
89 sh_relocate_section (bfd
*, struct bfd_link_info
*, bfd
*, asection
*,
90 bfd_byte
*, struct internal_reloc
*,
91 struct internal_syment
*, asection
**);
93 sh_align_loads (bfd
*, asection
*, struct internal_reloc
*,
96 /* The supported relocations. There are a lot of relocations defined
97 in coff/internal.h which we do not expect to ever see. */
98 static reloc_howto_type sh_coff_howtos
[] =
104 HOWTO (R_SH_IMM32CE
, /* type */
108 false, /* pc_relative */
110 complain_overflow_bitfield
, /* complain_on_overflow */
111 sh_reloc
, /* special_function */
112 "r_imm32ce", /* name */
113 true, /* partial_inplace */
114 0xffffffff, /* src_mask */
115 0xffffffff, /* dst_mask */
116 false), /* pcrel_offset */
120 EMPTY_HOWTO (3), /* R_SH_PCREL8 */
121 EMPTY_HOWTO (4), /* R_SH_PCREL16 */
122 EMPTY_HOWTO (5), /* R_SH_HIGH8 */
123 EMPTY_HOWTO (6), /* R_SH_IMM24 */
124 EMPTY_HOWTO (7), /* R_SH_LOW16 */
126 EMPTY_HOWTO (9), /* R_SH_PCDISP8BY4 */
128 HOWTO (R_SH_PCDISP8BY2
, /* type */
132 true, /* pc_relative */
134 complain_overflow_signed
, /* complain_on_overflow */
135 sh_reloc
, /* special_function */
136 "r_pcdisp8by2", /* name */
137 true, /* partial_inplace */
140 true), /* pcrel_offset */
142 EMPTY_HOWTO (11), /* R_SH_PCDISP8 */
144 HOWTO (R_SH_PCDISP
, /* type */
148 true, /* pc_relative */
150 complain_overflow_signed
, /* complain_on_overflow */
151 sh_reloc
, /* special_function */
152 "r_pcdisp12by2", /* name */
153 true, /* partial_inplace */
154 0xfff, /* src_mask */
155 0xfff, /* dst_mask */
156 true), /* pcrel_offset */
160 HOWTO (R_SH_IMM32
, /* type */
164 false, /* pc_relative */
166 complain_overflow_bitfield
, /* complain_on_overflow */
167 sh_reloc
, /* special_function */
168 "r_imm32", /* name */
169 true, /* partial_inplace */
170 0xffffffff, /* src_mask */
171 0xffffffff, /* dst_mask */
172 false), /* pcrel_offset */
176 HOWTO (R_SH_IMAGEBASE
, /* type */
180 false, /* pc_relative */
182 complain_overflow_bitfield
, /* complain_on_overflow */
183 sh_reloc
, /* special_function */
185 true, /* partial_inplace */
186 0xffffffff, /* src_mask */
187 0xffffffff, /* dst_mask */
188 false), /* pcrel_offset */
190 EMPTY_HOWTO (16), /* R_SH_IMM8 */
192 EMPTY_HOWTO (17), /* R_SH_IMM8BY2 */
193 EMPTY_HOWTO (18), /* R_SH_IMM8BY4 */
194 EMPTY_HOWTO (19), /* R_SH_IMM4 */
195 EMPTY_HOWTO (20), /* R_SH_IMM4BY2 */
196 EMPTY_HOWTO (21), /* R_SH_IMM4BY4 */
198 HOWTO (R_SH_PCRELIMM8BY2
, /* type */
202 true, /* pc_relative */
204 complain_overflow_unsigned
, /* complain_on_overflow */
205 sh_reloc
, /* special_function */
206 "r_pcrelimm8by2", /* name */
207 true, /* partial_inplace */
210 true), /* pcrel_offset */
212 HOWTO (R_SH_PCRELIMM8BY4
, /* type */
216 true, /* pc_relative */
218 complain_overflow_unsigned
, /* complain_on_overflow */
219 sh_reloc
, /* special_function */
220 "r_pcrelimm8by4", /* name */
221 true, /* partial_inplace */
224 true), /* pcrel_offset */
226 HOWTO (R_SH_IMM16
, /* type */
230 false, /* pc_relative */
232 complain_overflow_bitfield
, /* complain_on_overflow */
233 sh_reloc
, /* special_function */
234 "r_imm16", /* name */
235 true, /* partial_inplace */
236 0xffff, /* src_mask */
237 0xffff, /* dst_mask */
238 false), /* pcrel_offset */
240 HOWTO (R_SH_SWITCH16
, /* type */
244 false, /* pc_relative */
246 complain_overflow_bitfield
, /* complain_on_overflow */
247 sh_reloc
, /* special_function */
248 "r_switch16", /* name */
249 true, /* partial_inplace */
250 0xffff, /* src_mask */
251 0xffff, /* dst_mask */
252 false), /* pcrel_offset */
254 HOWTO (R_SH_SWITCH32
, /* type */
258 false, /* pc_relative */
260 complain_overflow_bitfield
, /* complain_on_overflow */
261 sh_reloc
, /* special_function */
262 "r_switch32", /* name */
263 true, /* partial_inplace */
264 0xffffffff, /* src_mask */
265 0xffffffff, /* dst_mask */
266 false), /* pcrel_offset */
268 HOWTO (R_SH_USES
, /* type */
272 false, /* pc_relative */
274 complain_overflow_bitfield
, /* complain_on_overflow */
275 sh_reloc
, /* special_function */
277 true, /* partial_inplace */
278 0xffff, /* src_mask */
279 0xffff, /* dst_mask */
280 false), /* pcrel_offset */
282 HOWTO (R_SH_COUNT
, /* type */
286 false, /* pc_relative */
288 complain_overflow_bitfield
, /* complain_on_overflow */
289 sh_reloc
, /* special_function */
290 "r_count", /* name */
291 true, /* partial_inplace */
292 0xffffffff, /* src_mask */
293 0xffffffff, /* dst_mask */
294 false), /* pcrel_offset */
296 HOWTO (R_SH_ALIGN
, /* type */
300 false, /* pc_relative */
302 complain_overflow_bitfield
, /* complain_on_overflow */
303 sh_reloc
, /* special_function */
304 "r_align", /* name */
305 true, /* partial_inplace */
306 0xffffffff, /* src_mask */
307 0xffffffff, /* dst_mask */
308 false), /* pcrel_offset */
310 HOWTO (R_SH_CODE
, /* type */
314 false, /* pc_relative */
316 complain_overflow_bitfield
, /* complain_on_overflow */
317 sh_reloc
, /* special_function */
319 true, /* partial_inplace */
320 0xffffffff, /* src_mask */
321 0xffffffff, /* dst_mask */
322 false), /* pcrel_offset */
324 HOWTO (R_SH_DATA
, /* type */
328 false, /* pc_relative */
330 complain_overflow_bitfield
, /* complain_on_overflow */
331 sh_reloc
, /* special_function */
333 true, /* partial_inplace */
334 0xffffffff, /* src_mask */
335 0xffffffff, /* dst_mask */
336 false), /* pcrel_offset */
338 HOWTO (R_SH_LABEL
, /* type */
342 false, /* pc_relative */
344 complain_overflow_bitfield
, /* complain_on_overflow */
345 sh_reloc
, /* special_function */
346 "r_label", /* name */
347 true, /* partial_inplace */
348 0xffffffff, /* src_mask */
349 0xffffffff, /* dst_mask */
350 false), /* pcrel_offset */
352 HOWTO (R_SH_SWITCH8
, /* type */
356 false, /* pc_relative */
358 complain_overflow_bitfield
, /* complain_on_overflow */
359 sh_reloc
, /* special_function */
360 "r_switch8", /* name */
361 true, /* partial_inplace */
364 false) /* pcrel_offset */
367 #define SH_COFF_HOWTO_COUNT (sizeof sh_coff_howtos / sizeof sh_coff_howtos[0])
369 /* Check for a bad magic number. */
370 #define BADMAG(x) SHBADMAG(x)
372 /* Customize coffcode.h (this is not currently used). */
375 /* FIXME: This should not be set here. */
376 #define __A_MAGIC_SET__
379 /* Swap the r_offset field in and out. */
380 #define SWAP_IN_RELOC_OFFSET H_GET_32
381 #define SWAP_OUT_RELOC_OFFSET H_PUT_32
383 /* Swap out extra information in the reloc structure. */
384 #define SWAP_OUT_RELOC_EXTRA(abfd, src, dst) \
387 dst->r_stuff[0] = 'S'; \
388 dst->r_stuff[1] = 'C'; \
393 /* Get the value of a symbol, when performing a relocation. */
396 get_symbol_value (asymbol
*symbol
)
400 if (bfd_is_com_section (symbol
->section
))
403 relocation
= (symbol
->value
+
404 symbol
->section
->output_section
->vma
+
405 symbol
->section
->output_offset
);
411 /* Convert an rtype to howto for the COFF backend linker.
412 Copied from coff-i386. */
413 #define coff_rtype_to_howto coff_sh_rtype_to_howto
416 static reloc_howto_type
*
417 coff_sh_rtype_to_howto (bfd
* abfd ATTRIBUTE_UNUSED
,
419 struct internal_reloc
* rel
,
420 struct coff_link_hash_entry
* h
,
421 struct internal_syment
* sym
,
424 reloc_howto_type
* howto
;
426 howto
= sh_coff_howtos
+ rel
->r_type
;
430 if (howto
->pc_relative
)
431 *addendp
+= sec
->vma
;
433 if (sym
!= NULL
&& sym
->n_scnum
== 0 && sym
->n_value
!= 0)
435 /* This is a common symbol. The section contents include the
436 size (sym->n_value) as an addend. The relocate_section
437 function will be adding in the final value of the symbol. We
438 need to subtract out the current size in order to get the
440 BFD_ASSERT (h
!= NULL
);
443 if (howto
->pc_relative
)
447 /* If the symbol is defined, then the generic code is going to
448 add back the symbol value in order to cancel out an
449 adjustment it made to the addend. However, we set the addend
450 to 0 at the start of this function. We need to adjust here,
451 to avoid the adjustment the generic code will make. FIXME:
452 This is getting a bit hackish. */
453 if (sym
!= NULL
&& sym
->n_scnum
!= 0)
454 *addendp
-= sym
->n_value
;
457 if (rel
->r_type
== R_SH_IMAGEBASE
)
458 *addendp
-= pe_data (sec
->output_section
->owner
)->pe_opthdr
.ImageBase
;
463 #endif /* COFF_WITH_PE */
465 /* This structure is used to map BFD reloc codes to SH PE relocs. */
466 struct shcoff_reloc_map
468 bfd_reloc_code_real_type bfd_reloc_val
;
469 unsigned char shcoff_reloc_val
;
473 /* An array mapping BFD reloc codes to SH PE relocs. */
474 static const struct shcoff_reloc_map sh_reloc_map
[] =
476 { BFD_RELOC_32
, R_SH_IMM32CE
},
477 { BFD_RELOC_RVA
, R_SH_IMAGEBASE
},
478 { BFD_RELOC_CTOR
, R_SH_IMM32CE
},
481 /* An array mapping BFD reloc codes to SH PE relocs. */
482 static const struct shcoff_reloc_map sh_reloc_map
[] =
484 { BFD_RELOC_32
, R_SH_IMM32
},
485 { BFD_RELOC_CTOR
, R_SH_IMM32
},
489 /* Given a BFD reloc code, return the howto structure for the
490 corresponding SH PE reloc. */
491 #define coff_bfd_reloc_type_lookup sh_coff_reloc_type_lookup
492 #define coff_bfd_reloc_name_lookup sh_coff_reloc_name_lookup
494 static reloc_howto_type
*
495 sh_coff_reloc_type_lookup (bfd
*abfd
,
496 bfd_reloc_code_real_type code
)
500 for (i
= ARRAY_SIZE (sh_reloc_map
); i
--;)
501 if (sh_reloc_map
[i
].bfd_reloc_val
== code
)
502 return &sh_coff_howtos
[(int) sh_reloc_map
[i
].shcoff_reloc_val
];
504 _bfd_error_handler (_("%pB: unsupported relocation type %#x"),
505 abfd
, (unsigned int) code
);
509 static reloc_howto_type
*
510 sh_coff_reloc_name_lookup (bfd
*abfd ATTRIBUTE_UNUSED
,
515 for (i
= 0; i
< sizeof (sh_coff_howtos
) / sizeof (sh_coff_howtos
[0]); i
++)
516 if (sh_coff_howtos
[i
].name
!= NULL
517 && strcasecmp (sh_coff_howtos
[i
].name
, r_name
) == 0)
518 return &sh_coff_howtos
[i
];
523 /* This macro is used in coffcode.h to get the howto corresponding to
524 an internal reloc. */
526 #define RTYPE2HOWTO(relent, internal) \
528 ((internal)->r_type < SH_COFF_HOWTO_COUNT \
529 ? &sh_coff_howtos[(internal)->r_type] \
530 : (reloc_howto_type *) NULL))
532 /* This is the same as the macro in coffcode.h, except that it copies
533 r_offset into reloc_entry->addend for some relocs. */
534 #define CALC_ADDEND(abfd, ptr, reloc, cache_ptr) \
536 coff_symbol_type *coffsym = (coff_symbol_type *) NULL; \
537 if (ptr && bfd_asymbol_bfd (ptr) != abfd) \
538 coffsym = (obj_symbols (abfd) \
539 + (cache_ptr->sym_ptr_ptr - symbols)); \
541 coffsym = coff_symbol_from (ptr); \
542 if (coffsym != (coff_symbol_type *) NULL \
543 && coffsym->native->u.syment.n_scnum == 0) \
544 cache_ptr->addend = 0; \
545 else if (ptr && bfd_asymbol_bfd (ptr) == abfd \
546 && ptr->section != (asection *) NULL) \
547 cache_ptr->addend = - (ptr->section->vma + ptr->value); \
549 cache_ptr->addend = 0; \
550 if ((reloc).r_type == R_SH_SWITCH8 \
551 || (reloc).r_type == R_SH_SWITCH16 \
552 || (reloc).r_type == R_SH_SWITCH32 \
553 || (reloc).r_type == R_SH_USES \
554 || (reloc).r_type == R_SH_COUNT \
555 || (reloc).r_type == R_SH_ALIGN) \
556 cache_ptr->addend = (reloc).r_offset; \
559 /* This is the howto function for the SH relocations. */
561 static bfd_reloc_status_type
562 sh_reloc (bfd
* abfd
,
563 arelent
* reloc_entry
,
566 asection
* input_section
,
568 char ** error_message ATTRIBUTE_UNUSED
)
572 unsigned short r_type
;
573 bfd_vma addr
= reloc_entry
->address
;
574 bfd_byte
*hit_data
= addr
+ (bfd_byte
*) data
;
576 r_type
= reloc_entry
->howto
->type
;
578 if (output_bfd
!= NULL
)
580 /* Partial linking--do nothing. */
581 reloc_entry
->address
+= input_section
->output_offset
;
585 /* Almost all relocs have to do with relaxing. If any work must be
586 done for them, it has been done in sh_relax_section. */
587 if (r_type
!= R_SH_IMM32
589 && r_type
!= R_SH_IMM32CE
590 && r_type
!= R_SH_IMAGEBASE
592 && (r_type
!= R_SH_PCDISP
593 || (symbol_in
->flags
& BSF_LOCAL
) != 0))
596 if (symbol_in
!= NULL
597 && bfd_is_und_section (symbol_in
->section
))
598 return bfd_reloc_undefined
;
600 if (!bfd_reloc_offset_in_range (reloc_entry
->howto
, abfd
, input_section
,
602 return bfd_reloc_outofrange
;
604 sym_value
= get_symbol_value (symbol_in
);
612 insn
= bfd_get_32 (abfd
, hit_data
);
613 insn
+= sym_value
+ reloc_entry
->addend
;
614 bfd_put_32 (abfd
, insn
, hit_data
);
618 insn
= bfd_get_32 (abfd
, hit_data
);
619 insn
+= sym_value
+ reloc_entry
->addend
;
620 insn
-= pe_data (input_section
->output_section
->owner
)->pe_opthdr
.ImageBase
;
621 bfd_put_32 (abfd
, insn
, hit_data
);
625 insn
= bfd_get_16 (abfd
, hit_data
);
626 sym_value
+= reloc_entry
->addend
;
627 sym_value
-= (input_section
->output_section
->vma
628 + input_section
->output_offset
631 sym_value
+= (((insn
& 0xfff) ^ 0x800) - 0x800) << 1;
632 insn
= (insn
& 0xf000) | ((sym_value
>> 1) & 0xfff);
633 bfd_put_16 (abfd
, insn
, hit_data
);
634 if (sym_value
+ 0x1000 >= 0x2000 || (sym_value
& 1) != 0)
635 return bfd_reloc_overflow
;
645 #define coff_bfd_merge_private_bfd_data _bfd_generic_verify_endian_match
647 /* We can do relaxing. */
648 #define coff_bfd_relax_section sh_relax_section
650 /* We use the special COFF backend linker. */
651 #define coff_relocate_section sh_relocate_section
653 /* When relaxing, we need to use special code to get the relocated
655 #define coff_bfd_get_relocated_section_contents \
656 sh_coff_get_relocated_section_contents
658 #include "coffcode.h"
661 sh_relax_delete_bytes (bfd
*, asection
*, bfd_vma
, int);
663 /* This function handles relaxing on the SH.
665 Function calls on the SH look like this:
674 The compiler and assembler will cooperate to create R_SH_USES
675 relocs on the jsr instructions. The r_offset field of the
676 R_SH_USES reloc is the PC relative offset to the instruction which
677 loads the register (the r_offset field is computed as though it
678 were a jump instruction, so the offset value is actually from four
679 bytes past the instruction). The linker can use this reloc to
680 determine just which function is being called, and thus decide
681 whether it is possible to replace the jsr with a bsr.
683 If multiple function calls are all based on a single register load
684 (i.e., the same function is called multiple times), the compiler
685 guarantees that each function call will have an R_SH_USES reloc.
686 Therefore, if the linker is able to convert each R_SH_USES reloc
687 which refers to that address, it can safely eliminate the register
690 When the assembler creates an R_SH_USES reloc, it examines it to
691 determine which address is being loaded (L1 in the above example).
692 It then counts the number of references to that address, and
693 creates an R_SH_COUNT reloc at that address. The r_offset field of
694 the R_SH_COUNT reloc will be the number of references. If the
695 linker is able to eliminate a register load, it can use the
696 R_SH_COUNT reloc to see whether it can also eliminate the function
699 SH relaxing also handles another, unrelated, matter. On the SH, if
700 a load or store instruction is not aligned on a four byte boundary,
701 the memory cycle interferes with the 32 bit instruction fetch,
702 causing a one cycle bubble in the pipeline. Therefore, we try to
703 align load and store instructions on four byte boundaries if we
704 can, by swapping them with one of the adjacent instructions. */
707 sh_relax_section (bfd
*abfd
,
709 struct bfd_link_info
*link_info
,
712 struct internal_reloc
*internal_relocs
;
714 struct internal_reloc
*irel
, *irelend
;
715 bfd_byte
*contents
= NULL
;
719 if (bfd_link_relocatable (link_info
)
720 || (sec
->flags
& SEC_HAS_CONTENTS
) == 0
721 || (sec
->flags
& SEC_RELOC
) == 0
722 || sec
->reloc_count
== 0)
725 if (coff_section_data (abfd
, sec
) == NULL
)
727 size_t amt
= sizeof (struct coff_section_tdata
);
728 sec
->used_by_bfd
= bfd_zalloc (abfd
, amt
);
729 if (sec
->used_by_bfd
== NULL
)
733 internal_relocs
= (_bfd_coff_read_internal_relocs
734 (abfd
, sec
, link_info
->keep_memory
,
735 (bfd_byte
*) NULL
, false,
736 (struct internal_reloc
*) NULL
));
737 if (internal_relocs
== NULL
)
742 irelend
= internal_relocs
+ sec
->reloc_count
;
743 for (irel
= internal_relocs
; irel
< irelend
; irel
++)
745 bfd_vma laddr
, paddr
, symval
;
747 struct internal_reloc
*irelfn
, *irelscan
, *irelcount
;
748 struct internal_syment sym
;
751 if (irel
->r_type
== R_SH_CODE
)
754 if (irel
->r_type
!= R_SH_USES
)
757 /* Get the section contents. */
758 if (contents
== NULL
)
760 if (coff_section_data (abfd
, sec
)->contents
!= NULL
)
761 contents
= coff_section_data (abfd
, sec
)->contents
;
764 if (!bfd_malloc_and_get_section (abfd
, sec
, &contents
))
769 /* The r_offset field of the R_SH_USES reloc will point us to
770 the register load. The 4 is because the r_offset field is
771 computed as though it were a jump offset, which are based
772 from 4 bytes after the jump instruction. */
773 laddr
= irel
->r_vaddr
- sec
->vma
+ 4;
774 /* Careful to sign extend the 32-bit offset. */
775 laddr
+= ((irel
->r_offset
& 0xffffffff) ^ 0x80000000) - 0x80000000;
776 if (laddr
>= sec
->size
)
778 /* xgettext: c-format */
780 (_("%pB: %#" PRIx64
": warning: bad R_SH_USES offset"),
781 abfd
, (uint64_t) irel
->r_vaddr
);
784 insn
= bfd_get_16 (abfd
, contents
+ laddr
);
786 /* If the instruction is not mov.l NN,rN, we don't know what to do. */
787 if ((insn
& 0xf000) != 0xd000)
790 /* xgettext: c-format */
791 (_("%pB: %#" PRIx64
": warning: R_SH_USES points to unrecognized insn %#x"),
792 abfd
, (uint64_t) irel
->r_vaddr
, insn
);
796 /* Get the address from which the register is being loaded. The
797 displacement in the mov.l instruction is quadrupled. It is a
798 displacement from four bytes after the movl instruction, but,
799 before adding in the PC address, two least significant bits
800 of the PC are cleared. We assume that the section is aligned
801 on a four byte boundary. */
804 paddr
+= (laddr
+ 4) &~ (bfd_vma
) 3;
805 if (paddr
>= sec
->size
)
808 /* xgettext: c-format */
809 (_("%pB: %#" PRIx64
": warning: bad R_SH_USES load offset"),
810 abfd
, (uint64_t) irel
->r_vaddr
);
814 /* Get the reloc for the address from which the register is
815 being loaded. This reloc will tell us which function is
816 actually being called. */
818 for (irelfn
= internal_relocs
; irelfn
< irelend
; irelfn
++)
819 if (irelfn
->r_vaddr
== paddr
821 && (irelfn
->r_type
== R_SH_IMM32
822 || irelfn
->r_type
== R_SH_IMM32CE
823 || irelfn
->r_type
== R_SH_IMAGEBASE
)
826 && irelfn
->r_type
== R_SH_IMM32
830 if (irelfn
>= irelend
)
833 /* xgettext: c-format */
834 (_("%pB: %#" PRIx64
": warning: could not find expected reloc"),
835 abfd
, (uint64_t) paddr
);
839 /* Get the value of the symbol referred to by the reloc. */
840 if (! _bfd_coff_get_external_symbols (abfd
))
842 bfd_coff_swap_sym_in (abfd
,
843 ((bfd_byte
*) obj_coff_external_syms (abfd
)
845 * bfd_coff_symesz (abfd
))),
847 if (sym
.n_scnum
!= 0 && sym
.n_scnum
!= sec
->target_index
)
850 /* xgettext: c-format */
851 (_("%pB: %#" PRIx64
": warning: symbol in unexpected section"),
852 abfd
, (uint64_t) paddr
);
856 if (sym
.n_sclass
!= C_EXT
)
858 symval
= (sym
.n_value
860 + sec
->output_section
->vma
861 + sec
->output_offset
);
865 struct coff_link_hash_entry
*h
;
867 h
= obj_coff_sym_hashes (abfd
)[irelfn
->r_symndx
];
868 BFD_ASSERT (h
!= NULL
);
869 if (h
->root
.type
!= bfd_link_hash_defined
870 && h
->root
.type
!= bfd_link_hash_defweak
)
872 /* This appears to be a reference to an undefined
873 symbol. Just ignore it--it will be caught by the
874 regular reloc processing. */
878 symval
= (h
->root
.u
.def
.value
879 + h
->root
.u
.def
.section
->output_section
->vma
880 + h
->root
.u
.def
.section
->output_offset
);
883 symval
+= bfd_get_32 (abfd
, contents
+ paddr
- sec
->vma
);
885 /* See if this function call can be shortened. */
889 + sec
->output_section
->vma
892 if (foff
< -0x1000 || foff
>= 0x1000)
894 /* After all that work, we can't shorten this function call. */
898 /* Shorten the function call. */
900 /* For simplicity of coding, we are going to modify the section
901 contents, the section relocs, and the BFD symbol table. We
902 must tell the rest of the code not to free up this
903 information. It would be possible to instead create a table
904 of changes which have to be made, as is done in coff-mips.c;
905 that would be more work, but would require less memory when
906 the linker is run. */
908 coff_section_data (abfd
, sec
)->relocs
= internal_relocs
;
909 coff_section_data (abfd
, sec
)->contents
= contents
;
911 /* Replace the jsr with a bsr. */
913 /* Change the R_SH_USES reloc into an R_SH_PCDISP reloc, and
914 replace the jsr with a bsr. */
915 irel
->r_type
= R_SH_PCDISP
;
916 irel
->r_symndx
= irelfn
->r_symndx
;
917 if (sym
.n_sclass
!= C_EXT
)
919 /* If this needs to be changed because of future relaxing,
920 it will be handled here like other internal PCDISP
923 (bfd_vma
) 0xb000 | ((foff
>> 1) & 0xfff),
924 contents
+ irel
->r_vaddr
- sec
->vma
);
928 /* We can't fully resolve this yet, because the external
929 symbol value may be changed by future relaxing. We let
930 the final link phase handle it. */
931 bfd_put_16 (abfd
, (bfd_vma
) 0xb000,
932 contents
+ irel
->r_vaddr
- sec
->vma
);
935 /* See if there is another R_SH_USES reloc referring to the same
937 for (irelscan
= internal_relocs
; irelscan
< irelend
; irelscan
++)
938 if (irelscan
->r_type
== R_SH_USES
939 && laddr
== irelscan
->r_vaddr
- sec
->vma
+ 4 + irelscan
->r_offset
)
941 if (irelscan
< irelend
)
943 /* Some other function call depends upon this register load,
944 and we have not yet converted that function call.
945 Indeed, we may never be able to convert it. There is
946 nothing else we can do at this point. */
950 /* Look for a R_SH_COUNT reloc on the location where the
951 function address is stored. Do this before deleting any
952 bytes, to avoid confusion about the address. */
953 for (irelcount
= internal_relocs
; irelcount
< irelend
; irelcount
++)
954 if (irelcount
->r_vaddr
== paddr
955 && irelcount
->r_type
== R_SH_COUNT
)
958 /* Delete the register load. */
959 if (! sh_relax_delete_bytes (abfd
, sec
, laddr
, 2))
962 /* That will change things, so, just in case it permits some
963 other function call to come within range, we should relax
964 again. Note that this is not required, and it may be slow. */
967 /* Now check whether we got a COUNT reloc. */
968 if (irelcount
>= irelend
)
971 /* xgettext: c-format */
972 (_("%pB: %#" PRIx64
": warning: could not find expected COUNT reloc"),
973 abfd
, (uint64_t) paddr
);
977 /* The number of uses is stored in the r_offset field. We've
979 if (irelcount
->r_offset
== 0)
981 /* xgettext: c-format */
982 _bfd_error_handler (_("%pB: %#" PRIx64
": warning: bad count"),
983 abfd
, (uint64_t) paddr
);
987 --irelcount
->r_offset
;
989 /* If there are no more uses, we can delete the address. Reload
990 the address from irelfn, in case it was changed by the
991 previous call to sh_relax_delete_bytes. */
992 if (irelcount
->r_offset
== 0)
994 if (! sh_relax_delete_bytes (abfd
, sec
,
995 irelfn
->r_vaddr
- sec
->vma
, 4))
999 /* We've done all we can with that function call. */
1002 /* Look for load and store instructions that we can align on four
1008 /* Get the section contents. */
1009 if (contents
== NULL
)
1011 if (coff_section_data (abfd
, sec
)->contents
!= NULL
)
1012 contents
= coff_section_data (abfd
, sec
)->contents
;
1015 if (!bfd_malloc_and_get_section (abfd
, sec
, &contents
))
1020 if (! sh_align_loads (abfd
, sec
, internal_relocs
, contents
, &swapped
))
1025 coff_section_data (abfd
, sec
)->relocs
= internal_relocs
;
1026 coff_section_data (abfd
, sec
)->contents
= contents
;
1030 if (internal_relocs
!= NULL
1031 && internal_relocs
!= coff_section_data (abfd
, sec
)->relocs
)
1033 if (! link_info
->keep_memory
)
1034 free (internal_relocs
);
1036 coff_section_data (abfd
, sec
)->relocs
= internal_relocs
;
1039 if (contents
!= NULL
&& contents
!= coff_section_data (abfd
, sec
)->contents
)
1041 if (! link_info
->keep_memory
)
1044 /* Cache the section contents for coff_link_input_bfd. */
1045 coff_section_data (abfd
, sec
)->contents
= contents
;
1051 if (internal_relocs
!= coff_section_data (abfd
, sec
)->relocs
)
1052 free (internal_relocs
);
1053 if (contents
!= coff_section_data (abfd
, sec
)->contents
)
1058 /* Delete some bytes from a section while relaxing. */
1061 sh_relax_delete_bytes (bfd
*abfd
,
1067 struct internal_reloc
*irel
, *irelend
;
1068 struct internal_reloc
*irelalign
;
1070 bfd_byte
*esym
, *esymend
;
1071 bfd_size_type symesz
;
1072 struct coff_link_hash_entry
**sym_hash
;
1075 contents
= coff_section_data (abfd
, sec
)->contents
;
1077 /* The deletion must stop at the next ALIGN reloc for an alignment
1078 power larger than the number of bytes we are deleting. */
1083 irel
= coff_section_data (abfd
, sec
)->relocs
;
1084 irelend
= irel
+ sec
->reloc_count
;
1085 for (; irel
< irelend
; irel
++)
1087 if (irel
->r_type
== R_SH_ALIGN
1088 && irel
->r_vaddr
- sec
->vma
> addr
1089 && count
< (1 << irel
->r_offset
))
1092 toaddr
= irel
->r_vaddr
- sec
->vma
;
1097 /* Actually delete the bytes. */
1098 memmove (contents
+ addr
, contents
+ addr
+ count
,
1099 (size_t) (toaddr
- addr
- count
));
1100 if (irelalign
== NULL
)
1106 #define NOP_OPCODE (0x0009)
1108 BFD_ASSERT ((count
& 1) == 0);
1109 for (i
= 0; i
< count
; i
+= 2)
1110 bfd_put_16 (abfd
, (bfd_vma
) NOP_OPCODE
, contents
+ toaddr
- count
+ i
);
1113 /* Adjust all the relocs. */
1114 for (irel
= coff_section_data (abfd
, sec
)->relocs
; irel
< irelend
; irel
++)
1116 bfd_vma nraddr
, stop
;
1119 struct internal_syment sym
;
1120 int off
, adjust
, oinsn
;
1121 bfd_signed_vma voff
= 0;
1124 /* Get the new reloc address. */
1125 nraddr
= irel
->r_vaddr
- sec
->vma
;
1126 if ((irel
->r_vaddr
- sec
->vma
> addr
1127 && irel
->r_vaddr
- sec
->vma
< toaddr
)
1128 || (irel
->r_type
== R_SH_ALIGN
1129 && irel
->r_vaddr
- sec
->vma
== toaddr
))
1132 /* See if this reloc was for the bytes we have deleted, in which
1133 case we no longer care about it. Don't delete relocs which
1134 represent addresses, though. */
1135 if (irel
->r_vaddr
- sec
->vma
>= addr
1136 && irel
->r_vaddr
- sec
->vma
< addr
+ count
1137 && irel
->r_type
!= R_SH_ALIGN
1138 && irel
->r_type
!= R_SH_CODE
1139 && irel
->r_type
!= R_SH_DATA
1140 && irel
->r_type
!= R_SH_LABEL
)
1141 irel
->r_type
= R_SH_UNUSED
;
1143 /* If this is a PC relative reloc, see if the range it covers
1144 includes the bytes we have deleted. */
1145 switch (irel
->r_type
)
1150 case R_SH_PCDISP8BY2
:
1152 case R_SH_PCRELIMM8BY2
:
1153 case R_SH_PCRELIMM8BY4
:
1154 start
= irel
->r_vaddr
- sec
->vma
;
1155 insn
= bfd_get_16 (abfd
, contents
+ nraddr
);
1159 switch (irel
->r_type
)
1162 start
= stop
= addr
;
1168 case R_SH_IMAGEBASE
:
1170 /* If this reloc is against a symbol defined in this
1171 section, and the symbol will not be adjusted below, we
1172 must check the addend to see it will put the value in
1173 range to be adjusted, and hence must be changed. */
1174 bfd_coff_swap_sym_in (abfd
,
1175 ((bfd_byte
*) obj_coff_external_syms (abfd
)
1177 * bfd_coff_symesz (abfd
))),
1179 if (sym
.n_sclass
!= C_EXT
1180 && sym
.n_scnum
== sec
->target_index
1181 && ((bfd_vma
) sym
.n_value
<= addr
1182 || (bfd_vma
) sym
.n_value
>= toaddr
))
1186 val
= bfd_get_32 (abfd
, contents
+ nraddr
);
1188 if (val
> addr
&& val
< toaddr
)
1189 bfd_put_32 (abfd
, val
- count
, contents
+ nraddr
);
1191 start
= stop
= addr
;
1194 case R_SH_PCDISP8BY2
:
1198 stop
= (bfd_vma
) ((bfd_signed_vma
) start
+ 4 + off
* 2);
1202 bfd_coff_swap_sym_in (abfd
,
1203 ((bfd_byte
*) obj_coff_external_syms (abfd
)
1205 * bfd_coff_symesz (abfd
))),
1207 if (sym
.n_sclass
== C_EXT
)
1208 start
= stop
= addr
;
1214 stop
= (bfd_vma
) ((bfd_signed_vma
) start
+ 4 + off
* 2);
1218 case R_SH_PCRELIMM8BY2
:
1220 stop
= start
+ 4 + off
* 2;
1223 case R_SH_PCRELIMM8BY4
:
1225 stop
= (start
&~ (bfd_vma
) 3) + 4 + off
* 4;
1231 /* These relocs types represent
1233 The r_offset field holds the difference between the reloc
1234 address and L1. That is the start of the reloc, and
1235 adding in the contents gives us the top. We must adjust
1236 both the r_offset field and the section contents. */
1238 start
= irel
->r_vaddr
- sec
->vma
;
1239 stop
= (bfd_vma
) ((bfd_signed_vma
) start
- (long) irel
->r_offset
);
1243 && (stop
<= addr
|| stop
>= toaddr
))
1244 irel
->r_offset
+= count
;
1245 else if (stop
> addr
1247 && (start
<= addr
|| start
>= toaddr
))
1248 irel
->r_offset
-= count
;
1252 if (irel
->r_type
== R_SH_SWITCH16
)
1253 voff
= bfd_get_signed_16 (abfd
, contents
+ nraddr
);
1254 else if (irel
->r_type
== R_SH_SWITCH8
)
1255 voff
= bfd_get_8 (abfd
, contents
+ nraddr
);
1257 voff
= bfd_get_signed_32 (abfd
, contents
+ nraddr
);
1258 stop
= (bfd_vma
) ((bfd_signed_vma
) start
+ voff
);
1263 start
= irel
->r_vaddr
- sec
->vma
;
1264 stop
= (bfd_vma
) ((bfd_signed_vma
) start
1265 + (long) irel
->r_offset
1272 && (stop
<= addr
|| stop
>= toaddr
))
1274 else if (stop
> addr
1276 && (start
<= addr
|| start
>= toaddr
))
1285 switch (irel
->r_type
)
1291 case R_SH_PCDISP8BY2
:
1292 case R_SH_PCRELIMM8BY2
:
1294 if ((oinsn
& 0xff00) != (insn
& 0xff00))
1296 bfd_put_16 (abfd
, (bfd_vma
) insn
, contents
+ nraddr
);
1301 if ((oinsn
& 0xf000) != (insn
& 0xf000))
1303 bfd_put_16 (abfd
, (bfd_vma
) insn
, contents
+ nraddr
);
1306 case R_SH_PCRELIMM8BY4
:
1307 BFD_ASSERT (adjust
== count
|| count
>= 4);
1312 if ((irel
->r_vaddr
& 3) == 0)
1315 if ((oinsn
& 0xff00) != (insn
& 0xff00))
1317 bfd_put_16 (abfd
, (bfd_vma
) insn
, contents
+ nraddr
);
1322 if (voff
< 0 || voff
>= 0xff)
1324 bfd_put_8 (abfd
, (bfd_vma
) voff
, contents
+ nraddr
);
1329 if (voff
< - 0x8000 || voff
>= 0x8000)
1331 bfd_put_signed_16 (abfd
, (bfd_vma
) voff
, contents
+ nraddr
);
1336 bfd_put_signed_32 (abfd
, (bfd_vma
) voff
, contents
+ nraddr
);
1340 irel
->r_offset
+= adjust
;
1347 /* xgettext: c-format */
1348 (_("%pB: %#" PRIx64
": fatal: reloc overflow while relaxing"),
1349 abfd
, (uint64_t) irel
->r_vaddr
);
1350 bfd_set_error (bfd_error_bad_value
);
1355 irel
->r_vaddr
= nraddr
+ sec
->vma
;
1358 /* Look through all the other sections. If there contain any IMM32
1359 relocs against internal symbols which we are not going to adjust
1360 below, we may need to adjust the addends. */
1361 for (o
= abfd
->sections
; o
!= NULL
; o
= o
->next
)
1363 struct internal_reloc
*internal_relocs
;
1364 struct internal_reloc
*irelscan
, *irelscanend
;
1365 bfd_byte
*ocontents
;
1368 || (o
->flags
& SEC_HAS_CONTENTS
) == 0
1369 || (o
->flags
& SEC_RELOC
) == 0
1370 || o
->reloc_count
== 0)
1373 /* We always cache the relocs. Perhaps, if info->keep_memory is
1374 FALSE, we should free them, if we are permitted to, when we
1375 leave sh_coff_relax_section. */
1376 internal_relocs
= (_bfd_coff_read_internal_relocs
1377 (abfd
, o
, true, (bfd_byte
*) NULL
, false,
1378 (struct internal_reloc
*) NULL
));
1379 if (internal_relocs
== NULL
)
1383 irelscanend
= internal_relocs
+ o
->reloc_count
;
1384 for (irelscan
= internal_relocs
; irelscan
< irelscanend
; irelscan
++)
1386 struct internal_syment sym
;
1389 if (irelscan
->r_type
!= R_SH_IMM32
1390 && irelscan
->r_type
!= R_SH_IMAGEBASE
1391 && irelscan
->r_type
!= R_SH_IMM32CE
)
1393 if (irelscan
->r_type
!= R_SH_IMM32
)
1397 bfd_coff_swap_sym_in (abfd
,
1398 ((bfd_byte
*) obj_coff_external_syms (abfd
)
1399 + (irelscan
->r_symndx
1400 * bfd_coff_symesz (abfd
))),
1402 if (sym
.n_sclass
!= C_EXT
1403 && sym
.n_scnum
== sec
->target_index
1404 && ((bfd_vma
) sym
.n_value
<= addr
1405 || (bfd_vma
) sym
.n_value
>= toaddr
))
1409 if (ocontents
== NULL
)
1411 if (coff_section_data (abfd
, o
)->contents
!= NULL
)
1412 ocontents
= coff_section_data (abfd
, o
)->contents
;
1415 if (!bfd_malloc_and_get_section (abfd
, o
, &ocontents
))
1417 /* We always cache the section contents.
1418 Perhaps, if info->keep_memory is FALSE, we
1419 should free them, if we are permitted to,
1420 when we leave sh_coff_relax_section. */
1421 coff_section_data (abfd
, o
)->contents
= ocontents
;
1425 val
= bfd_get_32 (abfd
, ocontents
+ irelscan
->r_vaddr
- o
->vma
);
1427 if (val
> addr
&& val
< toaddr
)
1428 bfd_put_32 (abfd
, val
- count
,
1429 ocontents
+ irelscan
->r_vaddr
- o
->vma
);
1434 /* Adjusting the internal symbols will not work if something has
1435 already retrieved the generic symbols. It would be possible to
1436 make this work by adjusting the generic symbols at the same time.
1437 However, this case should not arise in normal usage. */
1438 if (obj_symbols (abfd
) != NULL
1439 || obj_raw_syments (abfd
) != NULL
)
1442 (_("%pB: fatal: generic symbols retrieved before relaxing"), abfd
);
1443 bfd_set_error (bfd_error_invalid_operation
);
1447 /* Adjust all the symbols. */
1448 sym_hash
= obj_coff_sym_hashes (abfd
);
1449 symesz
= bfd_coff_symesz (abfd
);
1450 esym
= (bfd_byte
*) obj_coff_external_syms (abfd
);
1451 esymend
= esym
+ obj_raw_syment_count (abfd
) * symesz
;
1452 while (esym
< esymend
)
1454 struct internal_syment isym
;
1456 bfd_coff_swap_sym_in (abfd
, esym
, &isym
);
1458 if (isym
.n_scnum
== sec
->target_index
1459 && (bfd_vma
) isym
.n_value
> addr
1460 && (bfd_vma
) isym
.n_value
< toaddr
)
1462 isym
.n_value
-= count
;
1464 bfd_coff_swap_sym_out (abfd
, &isym
, esym
);
1466 if (*sym_hash
!= NULL
)
1468 BFD_ASSERT ((*sym_hash
)->root
.type
== bfd_link_hash_defined
1469 || (*sym_hash
)->root
.type
== bfd_link_hash_defweak
);
1470 BFD_ASSERT ((*sym_hash
)->root
.u
.def
.value
>= addr
1471 && (*sym_hash
)->root
.u
.def
.value
< toaddr
);
1472 (*sym_hash
)->root
.u
.def
.value
-= count
;
1476 esym
+= (isym
.n_numaux
+ 1) * symesz
;
1477 sym_hash
+= isym
.n_numaux
+ 1;
1480 /* See if we can move the ALIGN reloc forward. We have adjusted
1481 r_vaddr for it already. */
1482 if (irelalign
!= NULL
)
1484 bfd_vma alignto
, alignaddr
;
1486 alignto
= BFD_ALIGN (toaddr
, 1 << irelalign
->r_offset
);
1487 alignaddr
= BFD_ALIGN (irelalign
->r_vaddr
- sec
->vma
,
1488 1 << irelalign
->r_offset
);
1489 if (alignto
!= alignaddr
)
1491 /* Tail recursion. */
1492 return sh_relax_delete_bytes (abfd
, sec
, alignaddr
,
1493 (int) (alignto
- alignaddr
));
1500 /* This is yet another version of the SH opcode table, used to rapidly
1501 get information about a particular instruction. */
1503 /* The opcode map is represented by an array of these structures. The
1504 array is indexed by the high order four bits in the instruction. */
1506 struct sh_major_opcode
1508 /* A pointer to the instruction list. This is an array which
1509 contains all the instructions with this major opcode. */
1510 const struct sh_minor_opcode
*minor_opcodes
;
1511 /* The number of elements in minor_opcodes. */
1512 unsigned short count
;
1515 /* This structure holds information for a set of SH opcodes. The
1516 instruction code is anded with the mask value, and the resulting
1517 value is used to search the order opcode list. */
1519 struct sh_minor_opcode
1521 /* The sorted opcode list. */
1522 const struct sh_opcode
*opcodes
;
1523 /* The number of elements in opcodes. */
1524 unsigned short count
;
1525 /* The mask value to use when searching the opcode list. */
1526 unsigned short mask
;
1529 /* This structure holds information for an SH instruction. An array
1530 of these structures is sorted in order by opcode. */
1534 /* The code for this instruction, after it has been anded with the
1535 mask value in the sh_major_opcode structure. */
1536 unsigned short opcode
;
1537 /* Flags for this instruction. */
1538 unsigned long flags
;
1541 /* Flag which appear in the sh_opcode structure. */
1543 /* This instruction loads a value from memory. */
1546 /* This instruction stores a value to memory. */
1549 /* This instruction is a branch. */
1550 #define BRANCH (0x4)
1552 /* This instruction has a delay slot. */
1555 /* This instruction uses the value in the register in the field at
1556 mask 0x0f00 of the instruction. */
1557 #define USES1 (0x10)
1558 #define USES1_REG(x) ((x & 0x0f00) >> 8)
1560 /* This instruction uses the value in the register in the field at
1561 mask 0x00f0 of the instruction. */
1562 #define USES2 (0x20)
1563 #define USES2_REG(x) ((x & 0x00f0) >> 4)
1565 /* This instruction uses the value in register 0. */
1566 #define USESR0 (0x40)
1568 /* This instruction sets the value in the register in the field at
1569 mask 0x0f00 of the instruction. */
1570 #define SETS1 (0x80)
1571 #define SETS1_REG(x) ((x & 0x0f00) >> 8)
1573 /* This instruction sets the value in the register in the field at
1574 mask 0x00f0 of the instruction. */
1575 #define SETS2 (0x100)
1576 #define SETS2_REG(x) ((x & 0x00f0) >> 4)
1578 /* This instruction sets register 0. */
1579 #define SETSR0 (0x200)
1581 /* This instruction sets a special register. */
1582 #define SETSSP (0x400)
1584 /* This instruction uses a special register. */
1585 #define USESSP (0x800)
1587 /* This instruction uses the floating point register in the field at
1588 mask 0x0f00 of the instruction. */
1589 #define USESF1 (0x1000)
1590 #define USESF1_REG(x) ((x & 0x0f00) >> 8)
1592 /* This instruction uses the floating point register in the field at
1593 mask 0x00f0 of the instruction. */
1594 #define USESF2 (0x2000)
1595 #define USESF2_REG(x) ((x & 0x00f0) >> 4)
1597 /* This instruction uses floating point register 0. */
1598 #define USESF0 (0x4000)
1600 /* This instruction sets the floating point register in the field at
1601 mask 0x0f00 of the instruction. */
1602 #define SETSF1 (0x8000)
1603 #define SETSF1_REG(x) ((x & 0x0f00) >> 8)
1605 #define USESAS (0x10000)
1606 #define USESAS_REG(x) (((((x) >> 8) - 2) & 3) + 2)
1607 #define USESR8 (0x20000)
1608 #define SETSAS (0x40000)
1609 #define SETSAS_REG(x) USESAS_REG (x)
1611 #define MAP(a) a, sizeof a / sizeof a[0]
1613 #ifndef COFF_IMAGE_WITH_PE
1615 /* The opcode maps. */
1617 static const struct sh_opcode sh_opcode00
[] =
1619 { 0x0008, SETSSP
}, /* clrt */
1620 { 0x0009, 0 }, /* nop */
1621 { 0x000b, BRANCH
| DELAY
| USESSP
}, /* rts */
1622 { 0x0018, SETSSP
}, /* sett */
1623 { 0x0019, SETSSP
}, /* div0u */
1624 { 0x001b, 0 }, /* sleep */
1625 { 0x0028, SETSSP
}, /* clrmac */
1626 { 0x002b, BRANCH
| DELAY
| SETSSP
}, /* rte */
1627 { 0x0038, USESSP
| SETSSP
}, /* ldtlb */
1628 { 0x0048, SETSSP
}, /* clrs */
1629 { 0x0058, SETSSP
} /* sets */
1632 static const struct sh_opcode sh_opcode01
[] =
1634 { 0x0003, BRANCH
| DELAY
| USES1
| SETSSP
}, /* bsrf rn */
1635 { 0x000a, SETS1
| USESSP
}, /* sts mach,rn */
1636 { 0x001a, SETS1
| USESSP
}, /* sts macl,rn */
1637 { 0x0023, BRANCH
| DELAY
| USES1
}, /* braf rn */
1638 { 0x0029, SETS1
| USESSP
}, /* movt rn */
1639 { 0x002a, SETS1
| USESSP
}, /* sts pr,rn */
1640 { 0x005a, SETS1
| USESSP
}, /* sts fpul,rn */
1641 { 0x006a, SETS1
| USESSP
}, /* sts fpscr,rn / sts dsr,rn */
1642 { 0x0083, LOAD
| USES1
}, /* pref @rn */
1643 { 0x007a, SETS1
| USESSP
}, /* sts a0,rn */
1644 { 0x008a, SETS1
| USESSP
}, /* sts x0,rn */
1645 { 0x009a, SETS1
| USESSP
}, /* sts x1,rn */
1646 { 0x00aa, SETS1
| USESSP
}, /* sts y0,rn */
1647 { 0x00ba, SETS1
| USESSP
} /* sts y1,rn */
1650 static const struct sh_opcode sh_opcode02
[] =
1652 { 0x0002, SETS1
| USESSP
}, /* stc <special_reg>,rn */
1653 { 0x0004, STORE
| USES1
| USES2
| USESR0
}, /* mov.b rm,@(r0,rn) */
1654 { 0x0005, STORE
| USES1
| USES2
| USESR0
}, /* mov.w rm,@(r0,rn) */
1655 { 0x0006, STORE
| USES1
| USES2
| USESR0
}, /* mov.l rm,@(r0,rn) */
1656 { 0x0007, SETSSP
| USES1
| USES2
}, /* mul.l rm,rn */
1657 { 0x000c, LOAD
| SETS1
| USES2
| USESR0
}, /* mov.b @(r0,rm),rn */
1658 { 0x000d, LOAD
| SETS1
| USES2
| USESR0
}, /* mov.w @(r0,rm),rn */
1659 { 0x000e, LOAD
| SETS1
| USES2
| USESR0
}, /* mov.l @(r0,rm),rn */
1660 { 0x000f, LOAD
|SETS1
|SETS2
|SETSSP
|USES1
|USES2
|USESSP
}, /* mac.l @rm+,@rn+ */
1663 static const struct sh_minor_opcode sh_opcode0
[] =
1665 { MAP (sh_opcode00
), 0xffff },
1666 { MAP (sh_opcode01
), 0xf0ff },
1667 { MAP (sh_opcode02
), 0xf00f }
1670 static const struct sh_opcode sh_opcode10
[] =
1672 { 0x1000, STORE
| USES1
| USES2
} /* mov.l rm,@(disp,rn) */
1675 static const struct sh_minor_opcode sh_opcode1
[] =
1677 { MAP (sh_opcode10
), 0xf000 }
1680 static const struct sh_opcode sh_opcode20
[] =
1682 { 0x2000, STORE
| USES1
| USES2
}, /* mov.b rm,@rn */
1683 { 0x2001, STORE
| USES1
| USES2
}, /* mov.w rm,@rn */
1684 { 0x2002, STORE
| USES1
| USES2
}, /* mov.l rm,@rn */
1685 { 0x2004, STORE
| SETS1
| USES1
| USES2
}, /* mov.b rm,@-rn */
1686 { 0x2005, STORE
| SETS1
| USES1
| USES2
}, /* mov.w rm,@-rn */
1687 { 0x2006, STORE
| SETS1
| USES1
| USES2
}, /* mov.l rm,@-rn */
1688 { 0x2007, SETSSP
| USES1
| USES2
| USESSP
}, /* div0s */
1689 { 0x2008, SETSSP
| USES1
| USES2
}, /* tst rm,rn */
1690 { 0x2009, SETS1
| USES1
| USES2
}, /* and rm,rn */
1691 { 0x200a, SETS1
| USES1
| USES2
}, /* xor rm,rn */
1692 { 0x200b, SETS1
| USES1
| USES2
}, /* or rm,rn */
1693 { 0x200c, SETSSP
| USES1
| USES2
}, /* cmp/str rm,rn */
1694 { 0x200d, SETS1
| USES1
| USES2
}, /* xtrct rm,rn */
1695 { 0x200e, SETSSP
| USES1
| USES2
}, /* mulu.w rm,rn */
1696 { 0x200f, SETSSP
| USES1
| USES2
} /* muls.w rm,rn */
1699 static const struct sh_minor_opcode sh_opcode2
[] =
1701 { MAP (sh_opcode20
), 0xf00f }
1704 static const struct sh_opcode sh_opcode30
[] =
1706 { 0x3000, SETSSP
| USES1
| USES2
}, /* cmp/eq rm,rn */
1707 { 0x3002, SETSSP
| USES1
| USES2
}, /* cmp/hs rm,rn */
1708 { 0x3003, SETSSP
| USES1
| USES2
}, /* cmp/ge rm,rn */
1709 { 0x3004, SETSSP
| USESSP
| USES1
| USES2
}, /* div1 rm,rn */
1710 { 0x3005, SETSSP
| USES1
| USES2
}, /* dmulu.l rm,rn */
1711 { 0x3006, SETSSP
| USES1
| USES2
}, /* cmp/hi rm,rn */
1712 { 0x3007, SETSSP
| USES1
| USES2
}, /* cmp/gt rm,rn */
1713 { 0x3008, SETS1
| USES1
| USES2
}, /* sub rm,rn */
1714 { 0x300a, SETS1
| SETSSP
| USES1
| USES2
| USESSP
}, /* subc rm,rn */
1715 { 0x300b, SETS1
| SETSSP
| USES1
| USES2
}, /* subv rm,rn */
1716 { 0x300c, SETS1
| USES1
| USES2
}, /* add rm,rn */
1717 { 0x300d, SETSSP
| USES1
| USES2
}, /* dmuls.l rm,rn */
1718 { 0x300e, SETS1
| SETSSP
| USES1
| USES2
| USESSP
}, /* addc rm,rn */
1719 { 0x300f, SETS1
| SETSSP
| USES1
| USES2
} /* addv rm,rn */
1722 static const struct sh_minor_opcode sh_opcode3
[] =
1724 { MAP (sh_opcode30
), 0xf00f }
1727 static const struct sh_opcode sh_opcode40
[] =
1729 { 0x4000, SETS1
| SETSSP
| USES1
}, /* shll rn */
1730 { 0x4001, SETS1
| SETSSP
| USES1
}, /* shlr rn */
1731 { 0x4002, STORE
| SETS1
| USES1
| USESSP
}, /* sts.l mach,@-rn */
1732 { 0x4004, SETS1
| SETSSP
| USES1
}, /* rotl rn */
1733 { 0x4005, SETS1
| SETSSP
| USES1
}, /* rotr rn */
1734 { 0x4006, LOAD
| SETS1
| SETSSP
| USES1
}, /* lds.l @rm+,mach */
1735 { 0x4008, SETS1
| USES1
}, /* shll2 rn */
1736 { 0x4009, SETS1
| USES1
}, /* shlr2 rn */
1737 { 0x400a, SETSSP
| USES1
}, /* lds rm,mach */
1738 { 0x400b, BRANCH
| DELAY
| USES1
}, /* jsr @rn */
1739 { 0x4010, SETS1
| SETSSP
| USES1
}, /* dt rn */
1740 { 0x4011, SETSSP
| USES1
}, /* cmp/pz rn */
1741 { 0x4012, STORE
| SETS1
| USES1
| USESSP
}, /* sts.l macl,@-rn */
1742 { 0x4014, SETSSP
| USES1
}, /* setrc rm */
1743 { 0x4015, SETSSP
| USES1
}, /* cmp/pl rn */
1744 { 0x4016, LOAD
| SETS1
| SETSSP
| USES1
}, /* lds.l @rm+,macl */
1745 { 0x4018, SETS1
| USES1
}, /* shll8 rn */
1746 { 0x4019, SETS1
| USES1
}, /* shlr8 rn */
1747 { 0x401a, SETSSP
| USES1
}, /* lds rm,macl */
1748 { 0x401b, LOAD
| SETSSP
| USES1
}, /* tas.b @rn */
1749 { 0x4020, SETS1
| SETSSP
| USES1
}, /* shal rn */
1750 { 0x4021, SETS1
| SETSSP
| USES1
}, /* shar rn */
1751 { 0x4022, STORE
| SETS1
| USES1
| USESSP
}, /* sts.l pr,@-rn */
1752 { 0x4024, SETS1
| SETSSP
| USES1
| USESSP
}, /* rotcl rn */
1753 { 0x4025, SETS1
| SETSSP
| USES1
| USESSP
}, /* rotcr rn */
1754 { 0x4026, LOAD
| SETS1
| SETSSP
| USES1
}, /* lds.l @rm+,pr */
1755 { 0x4028, SETS1
| USES1
}, /* shll16 rn */
1756 { 0x4029, SETS1
| USES1
}, /* shlr16 rn */
1757 { 0x402a, SETSSP
| USES1
}, /* lds rm,pr */
1758 { 0x402b, BRANCH
| DELAY
| USES1
}, /* jmp @rn */
1759 { 0x4052, STORE
| SETS1
| USES1
| USESSP
}, /* sts.l fpul,@-rn */
1760 { 0x4056, LOAD
| SETS1
| SETSSP
| USES1
}, /* lds.l @rm+,fpul */
1761 { 0x405a, SETSSP
| USES1
}, /* lds.l rm,fpul */
1762 { 0x4062, STORE
| SETS1
| USES1
| USESSP
}, /* sts.l fpscr / dsr,@-rn */
1763 { 0x4066, LOAD
| SETS1
| SETSSP
| USES1
}, /* lds.l @rm+,fpscr / dsr */
1764 { 0x406a, SETSSP
| USES1
}, /* lds rm,fpscr / lds rm,dsr */
1765 { 0x4072, STORE
| SETS1
| USES1
| USESSP
}, /* sts.l a0,@-rn */
1766 { 0x4076, LOAD
| SETS1
| SETSSP
| USES1
}, /* lds.l @rm+,a0 */
1767 { 0x407a, SETSSP
| USES1
}, /* lds.l rm,a0 */
1768 { 0x4082, STORE
| SETS1
| USES1
| USESSP
}, /* sts.l x0,@-rn */
1769 { 0x4086, LOAD
| SETS1
| SETSSP
| USES1
}, /* lds.l @rm+,x0 */
1770 { 0x408a, SETSSP
| USES1
}, /* lds.l rm,x0 */
1771 { 0x4092, STORE
| SETS1
| USES1
| USESSP
}, /* sts.l x1,@-rn */
1772 { 0x4096, LOAD
| SETS1
| SETSSP
| USES1
}, /* lds.l @rm+,x1 */
1773 { 0x409a, SETSSP
| USES1
}, /* lds.l rm,x1 */
1774 { 0x40a2, STORE
| SETS1
| USES1
| USESSP
}, /* sts.l y0,@-rn */
1775 { 0x40a6, LOAD
| SETS1
| SETSSP
| USES1
}, /* lds.l @rm+,y0 */
1776 { 0x40aa, SETSSP
| USES1
}, /* lds.l rm,y0 */
1777 { 0x40b2, STORE
| SETS1
| USES1
| USESSP
}, /* sts.l y1,@-rn */
1778 { 0x40b6, LOAD
| SETS1
| SETSSP
| USES1
}, /* lds.l @rm+,y1 */
1779 { 0x40ba, SETSSP
| USES1
} /* lds.l rm,y1 */
1782 static const struct sh_opcode sh_opcode41
[] =
1784 { 0x4003, STORE
| SETS1
| USES1
| USESSP
}, /* stc.l <special_reg>,@-rn */
1785 { 0x4007, LOAD
| SETS1
| SETSSP
| USES1
}, /* ldc.l @rm+,<special_reg> */
1786 { 0x400c, SETS1
| USES1
| USES2
}, /* shad rm,rn */
1787 { 0x400d, SETS1
| USES1
| USES2
}, /* shld rm,rn */
1788 { 0x400e, SETSSP
| USES1
}, /* ldc rm,<special_reg> */
1789 { 0x400f, LOAD
|SETS1
|SETS2
|SETSSP
|USES1
|USES2
|USESSP
}, /* mac.w @rm+,@rn+ */
1792 static const struct sh_minor_opcode sh_opcode4
[] =
1794 { MAP (sh_opcode40
), 0xf0ff },
1795 { MAP (sh_opcode41
), 0xf00f }
1798 static const struct sh_opcode sh_opcode50
[] =
1800 { 0x5000, LOAD
| SETS1
| USES2
} /* mov.l @(disp,rm),rn */
1803 static const struct sh_minor_opcode sh_opcode5
[] =
1805 { MAP (sh_opcode50
), 0xf000 }
1808 static const struct sh_opcode sh_opcode60
[] =
1810 { 0x6000, LOAD
| SETS1
| USES2
}, /* mov.b @rm,rn */
1811 { 0x6001, LOAD
| SETS1
| USES2
}, /* mov.w @rm,rn */
1812 { 0x6002, LOAD
| SETS1
| USES2
}, /* mov.l @rm,rn */
1813 { 0x6003, SETS1
| USES2
}, /* mov rm,rn */
1814 { 0x6004, LOAD
| SETS1
| SETS2
| USES2
}, /* mov.b @rm+,rn */
1815 { 0x6005, LOAD
| SETS1
| SETS2
| USES2
}, /* mov.w @rm+,rn */
1816 { 0x6006, LOAD
| SETS1
| SETS2
| USES2
}, /* mov.l @rm+,rn */
1817 { 0x6007, SETS1
| USES2
}, /* not rm,rn */
1818 { 0x6008, SETS1
| USES2
}, /* swap.b rm,rn */
1819 { 0x6009, SETS1
| USES2
}, /* swap.w rm,rn */
1820 { 0x600a, SETS1
| SETSSP
| USES2
| USESSP
}, /* negc rm,rn */
1821 { 0x600b, SETS1
| USES2
}, /* neg rm,rn */
1822 { 0x600c, SETS1
| USES2
}, /* extu.b rm,rn */
1823 { 0x600d, SETS1
| USES2
}, /* extu.w rm,rn */
1824 { 0x600e, SETS1
| USES2
}, /* exts.b rm,rn */
1825 { 0x600f, SETS1
| USES2
} /* exts.w rm,rn */
1828 static const struct sh_minor_opcode sh_opcode6
[] =
1830 { MAP (sh_opcode60
), 0xf00f }
1833 static const struct sh_opcode sh_opcode70
[] =
1835 { 0x7000, SETS1
| USES1
} /* add #imm,rn */
1838 static const struct sh_minor_opcode sh_opcode7
[] =
1840 { MAP (sh_opcode70
), 0xf000 }
1843 static const struct sh_opcode sh_opcode80
[] =
1845 { 0x8000, STORE
| USES2
| USESR0
}, /* mov.b r0,@(disp,rn) */
1846 { 0x8100, STORE
| USES2
| USESR0
}, /* mov.w r0,@(disp,rn) */
1847 { 0x8200, SETSSP
}, /* setrc #imm */
1848 { 0x8400, LOAD
| SETSR0
| USES2
}, /* mov.b @(disp,rm),r0 */
1849 { 0x8500, LOAD
| SETSR0
| USES2
}, /* mov.w @(disp,rn),r0 */
1850 { 0x8800, SETSSP
| USESR0
}, /* cmp/eq #imm,r0 */
1851 { 0x8900, BRANCH
| USESSP
}, /* bt label */
1852 { 0x8b00, BRANCH
| USESSP
}, /* bf label */
1853 { 0x8c00, SETSSP
}, /* ldrs @(disp,pc) */
1854 { 0x8d00, BRANCH
| DELAY
| USESSP
}, /* bt/s label */
1855 { 0x8e00, SETSSP
}, /* ldre @(disp,pc) */
1856 { 0x8f00, BRANCH
| DELAY
| USESSP
} /* bf/s label */
1859 static const struct sh_minor_opcode sh_opcode8
[] =
1861 { MAP (sh_opcode80
), 0xff00 }
1864 static const struct sh_opcode sh_opcode90
[] =
1866 { 0x9000, LOAD
| SETS1
} /* mov.w @(disp,pc),rn */
1869 static const struct sh_minor_opcode sh_opcode9
[] =
1871 { MAP (sh_opcode90
), 0xf000 }
1874 static const struct sh_opcode sh_opcodea0
[] =
1876 { 0xa000, BRANCH
| DELAY
} /* bra label */
1879 static const struct sh_minor_opcode sh_opcodea
[] =
1881 { MAP (sh_opcodea0
), 0xf000 }
1884 static const struct sh_opcode sh_opcodeb0
[] =
1886 { 0xb000, BRANCH
| DELAY
} /* bsr label */
1889 static const struct sh_minor_opcode sh_opcodeb
[] =
1891 { MAP (sh_opcodeb0
), 0xf000 }
1894 static const struct sh_opcode sh_opcodec0
[] =
1896 { 0xc000, STORE
| USESR0
| USESSP
}, /* mov.b r0,@(disp,gbr) */
1897 { 0xc100, STORE
| USESR0
| USESSP
}, /* mov.w r0,@(disp,gbr) */
1898 { 0xc200, STORE
| USESR0
| USESSP
}, /* mov.l r0,@(disp,gbr) */
1899 { 0xc300, BRANCH
| USESSP
}, /* trapa #imm */
1900 { 0xc400, LOAD
| SETSR0
| USESSP
}, /* mov.b @(disp,gbr),r0 */
1901 { 0xc500, LOAD
| SETSR0
| USESSP
}, /* mov.w @(disp,gbr),r0 */
1902 { 0xc600, LOAD
| SETSR0
| USESSP
}, /* mov.l @(disp,gbr),r0 */
1903 { 0xc700, SETSR0
}, /* mova @(disp,pc),r0 */
1904 { 0xc800, SETSSP
| USESR0
}, /* tst #imm,r0 */
1905 { 0xc900, SETSR0
| USESR0
}, /* and #imm,r0 */
1906 { 0xca00, SETSR0
| USESR0
}, /* xor #imm,r0 */
1907 { 0xcb00, SETSR0
| USESR0
}, /* or #imm,r0 */
1908 { 0xcc00, LOAD
| SETSSP
| USESR0
| USESSP
}, /* tst.b #imm,@(r0,gbr) */
1909 { 0xcd00, LOAD
| STORE
| USESR0
| USESSP
}, /* and.b #imm,@(r0,gbr) */
1910 { 0xce00, LOAD
| STORE
| USESR0
| USESSP
}, /* xor.b #imm,@(r0,gbr) */
1911 { 0xcf00, LOAD
| STORE
| USESR0
| USESSP
} /* or.b #imm,@(r0,gbr) */
1914 static const struct sh_minor_opcode sh_opcodec
[] =
1916 { MAP (sh_opcodec0
), 0xff00 }
1919 static const struct sh_opcode sh_opcoded0
[] =
1921 { 0xd000, LOAD
| SETS1
} /* mov.l @(disp,pc),rn */
1924 static const struct sh_minor_opcode sh_opcoded
[] =
1926 { MAP (sh_opcoded0
), 0xf000 }
1929 static const struct sh_opcode sh_opcodee0
[] =
1931 { 0xe000, SETS1
} /* mov #imm,rn */
1934 static const struct sh_minor_opcode sh_opcodee
[] =
1936 { MAP (sh_opcodee0
), 0xf000 }
1939 static const struct sh_opcode sh_opcodef0
[] =
1941 { 0xf000, SETSF1
| USESF1
| USESF2
}, /* fadd fm,fn */
1942 { 0xf001, SETSF1
| USESF1
| USESF2
}, /* fsub fm,fn */
1943 { 0xf002, SETSF1
| USESF1
| USESF2
}, /* fmul fm,fn */
1944 { 0xf003, SETSF1
| USESF1
| USESF2
}, /* fdiv fm,fn */
1945 { 0xf004, SETSSP
| USESF1
| USESF2
}, /* fcmp/eq fm,fn */
1946 { 0xf005, SETSSP
| USESF1
| USESF2
}, /* fcmp/gt fm,fn */
1947 { 0xf006, LOAD
| SETSF1
| USES2
| USESR0
}, /* fmov.s @(r0,rm),fn */
1948 { 0xf007, STORE
| USES1
| USESF2
| USESR0
}, /* fmov.s fm,@(r0,rn) */
1949 { 0xf008, LOAD
| SETSF1
| USES2
}, /* fmov.s @rm,fn */
1950 { 0xf009, LOAD
| SETS2
| SETSF1
| USES2
}, /* fmov.s @rm+,fn */
1951 { 0xf00a, STORE
| USES1
| USESF2
}, /* fmov.s fm,@rn */
1952 { 0xf00b, STORE
| SETS1
| USES1
| USESF2
}, /* fmov.s fm,@-rn */
1953 { 0xf00c, SETSF1
| USESF2
}, /* fmov fm,fn */
1954 { 0xf00e, SETSF1
| USESF1
| USESF2
| USESF0
} /* fmac f0,fm,fn */
1957 static const struct sh_opcode sh_opcodef1
[] =
1959 { 0xf00d, SETSF1
| USESSP
}, /* fsts fpul,fn */
1960 { 0xf01d, SETSSP
| USESF1
}, /* flds fn,fpul */
1961 { 0xf02d, SETSF1
| USESSP
}, /* float fpul,fn */
1962 { 0xf03d, SETSSP
| USESF1
}, /* ftrc fn,fpul */
1963 { 0xf04d, SETSF1
| USESF1
}, /* fneg fn */
1964 { 0xf05d, SETSF1
| USESF1
}, /* fabs fn */
1965 { 0xf06d, SETSF1
| USESF1
}, /* fsqrt fn */
1966 { 0xf07d, SETSSP
| USESF1
}, /* ftst/nan fn */
1967 { 0xf08d, SETSF1
}, /* fldi0 fn */
1968 { 0xf09d, SETSF1
} /* fldi1 fn */
1971 static const struct sh_minor_opcode sh_opcodef
[] =
1973 { MAP (sh_opcodef0
), 0xf00f },
1974 { MAP (sh_opcodef1
), 0xf0ff }
1977 static struct sh_major_opcode sh_opcodes
[] =
1979 { MAP (sh_opcode0
) },
1980 { MAP (sh_opcode1
) },
1981 { MAP (sh_opcode2
) },
1982 { MAP (sh_opcode3
) },
1983 { MAP (sh_opcode4
) },
1984 { MAP (sh_opcode5
) },
1985 { MAP (sh_opcode6
) },
1986 { MAP (sh_opcode7
) },
1987 { MAP (sh_opcode8
) },
1988 { MAP (sh_opcode9
) },
1989 { MAP (sh_opcodea
) },
1990 { MAP (sh_opcodeb
) },
1991 { MAP (sh_opcodec
) },
1992 { MAP (sh_opcoded
) },
1993 { MAP (sh_opcodee
) },
1994 { MAP (sh_opcodef
) }
1997 /* The double data transfer / parallel processing insns are not
1998 described here. This will cause sh_align_load_span to leave them alone. */
2000 static const struct sh_opcode sh_dsp_opcodef0
[] =
2002 { 0xf400, USESAS
| SETSAS
| LOAD
| SETSSP
}, /* movs.x @-as,ds */
2003 { 0xf401, USESAS
| SETSAS
| STORE
| USESSP
}, /* movs.x ds,@-as */
2004 { 0xf404, USESAS
| LOAD
| SETSSP
}, /* movs.x @as,ds */
2005 { 0xf405, USESAS
| STORE
| USESSP
}, /* movs.x ds,@as */
2006 { 0xf408, USESAS
| SETSAS
| LOAD
| SETSSP
}, /* movs.x @as+,ds */
2007 { 0xf409, USESAS
| SETSAS
| STORE
| USESSP
}, /* movs.x ds,@as+ */
2008 { 0xf40c, USESAS
| SETSAS
| LOAD
| SETSSP
| USESR8
}, /* movs.x @as+r8,ds */
2009 { 0xf40d, USESAS
| SETSAS
| STORE
| USESSP
| USESR8
} /* movs.x ds,@as+r8 */
2012 static const struct sh_minor_opcode sh_dsp_opcodef
[] =
2014 { MAP (sh_dsp_opcodef0
), 0xfc0d }
2017 /* Given an instruction, return a pointer to the corresponding
2018 sh_opcode structure. Return NULL if the instruction is not
2021 static const struct sh_opcode
*
2022 sh_insn_info (unsigned int insn
)
2024 const struct sh_major_opcode
*maj
;
2025 const struct sh_minor_opcode
*min
, *minend
;
2027 maj
= &sh_opcodes
[(insn
& 0xf000) >> 12];
2028 min
= maj
->minor_opcodes
;
2029 minend
= min
+ maj
->count
;
2030 for (; min
< minend
; min
++)
2033 const struct sh_opcode
*op
, *opend
;
2035 l
= insn
& min
->mask
;
2037 opend
= op
+ min
->count
;
2039 /* Since the opcodes tables are sorted, we could use a binary
2040 search here if the count were above some cutoff value. */
2041 for (; op
< opend
; op
++)
2042 if (op
->opcode
== l
)
2049 /* See whether an instruction uses a general purpose register. */
2052 sh_insn_uses_reg (unsigned int insn
,
2053 const struct sh_opcode
*op
,
2060 if ((f
& USES1
) != 0
2061 && USES1_REG (insn
) == reg
)
2063 if ((f
& USES2
) != 0
2064 && USES2_REG (insn
) == reg
)
2066 if ((f
& USESR0
) != 0
2069 if ((f
& USESAS
) && reg
== USESAS_REG (insn
))
2071 if ((f
& USESR8
) && reg
== 8)
2077 /* See whether an instruction sets a general purpose register. */
2080 sh_insn_sets_reg (unsigned int insn
,
2081 const struct sh_opcode
*op
,
2088 if ((f
& SETS1
) != 0
2089 && SETS1_REG (insn
) == reg
)
2091 if ((f
& SETS2
) != 0
2092 && SETS2_REG (insn
) == reg
)
2094 if ((f
& SETSR0
) != 0
2097 if ((f
& SETSAS
) && reg
== SETSAS_REG (insn
))
2103 /* See whether an instruction uses or sets a general purpose register */
2106 sh_insn_uses_or_sets_reg (unsigned int insn
,
2107 const struct sh_opcode
*op
,
2110 if (sh_insn_uses_reg (insn
, op
, reg
))
2113 return sh_insn_sets_reg (insn
, op
, reg
);
2116 /* See whether an instruction uses a floating point register. */
2119 sh_insn_uses_freg (unsigned int insn
,
2120 const struct sh_opcode
*op
,
2127 /* We can't tell if this is a double-precision insn, so just play safe
2128 and assume that it might be. So not only have we test FREG against
2129 itself, but also even FREG against FREG+1 - if the using insn uses
2130 just the low part of a double precision value - but also an odd
2131 FREG against FREG-1 - if the setting insn sets just the low part
2132 of a double precision value.
2133 So what this all boils down to is that we have to ignore the lowest
2134 bit of the register number. */
2136 if ((f
& USESF1
) != 0
2137 && (USESF1_REG (insn
) & 0xe) == (freg
& 0xe))
2139 if ((f
& USESF2
) != 0
2140 && (USESF2_REG (insn
) & 0xe) == (freg
& 0xe))
2142 if ((f
& USESF0
) != 0
2149 /* See whether an instruction sets a floating point register. */
2152 sh_insn_sets_freg (unsigned int insn
,
2153 const struct sh_opcode
*op
,
2160 /* We can't tell if this is a double-precision insn, so just play safe
2161 and assume that it might be. So not only have we test FREG against
2162 itself, but also even FREG against FREG+1 - if the using insn uses
2163 just the low part of a double precision value - but also an odd
2164 FREG against FREG-1 - if the setting insn sets just the low part
2165 of a double precision value.
2166 So what this all boils down to is that we have to ignore the lowest
2167 bit of the register number. */
2169 if ((f
& SETSF1
) != 0
2170 && (SETSF1_REG (insn
) & 0xe) == (freg
& 0xe))
2176 /* See whether an instruction uses or sets a floating point register */
2179 sh_insn_uses_or_sets_freg (unsigned int insn
,
2180 const struct sh_opcode
*op
,
2183 if (sh_insn_uses_freg (insn
, op
, reg
))
2186 return sh_insn_sets_freg (insn
, op
, reg
);
2189 /* See whether instructions I1 and I2 conflict, assuming I1 comes
2190 before I2. OP1 and OP2 are the corresponding sh_opcode structures.
2191 This should return TRUE if there is a conflict, or FALSE if the
2192 instructions can be swapped safely. */
2195 sh_insns_conflict (unsigned int i1
,
2196 const struct sh_opcode
*op1
,
2198 const struct sh_opcode
*op2
)
2200 unsigned int f1
, f2
;
2205 /* Load of fpscr conflicts with floating point operations.
2206 FIXME: shouldn't test raw opcodes here. */
2207 if (((i1
& 0xf0ff) == 0x4066 && (i2
& 0xf000) == 0xf000)
2208 || ((i2
& 0xf0ff) == 0x4066 && (i1
& 0xf000) == 0xf000))
2211 if ((f1
& (BRANCH
| DELAY
)) != 0
2212 || (f2
& (BRANCH
| DELAY
)) != 0)
2215 if (((f1
| f2
) & SETSSP
)
2216 && (f1
& (SETSSP
| USESSP
))
2217 && (f2
& (SETSSP
| USESSP
)))
2220 if ((f1
& SETS1
) != 0
2221 && sh_insn_uses_or_sets_reg (i2
, op2
, SETS1_REG (i1
)))
2223 if ((f1
& SETS2
) != 0
2224 && sh_insn_uses_or_sets_reg (i2
, op2
, SETS2_REG (i1
)))
2226 if ((f1
& SETSR0
) != 0
2227 && sh_insn_uses_or_sets_reg (i2
, op2
, 0))
2230 && sh_insn_uses_or_sets_reg (i2
, op2
, SETSAS_REG (i1
)))
2232 if ((f1
& SETSF1
) != 0
2233 && sh_insn_uses_or_sets_freg (i2
, op2
, SETSF1_REG (i1
)))
2236 if ((f2
& SETS1
) != 0
2237 && sh_insn_uses_or_sets_reg (i1
, op1
, SETS1_REG (i2
)))
2239 if ((f2
& SETS2
) != 0
2240 && sh_insn_uses_or_sets_reg (i1
, op1
, SETS2_REG (i2
)))
2242 if ((f2
& SETSR0
) != 0
2243 && sh_insn_uses_or_sets_reg (i1
, op1
, 0))
2246 && sh_insn_uses_or_sets_reg (i1
, op1
, SETSAS_REG (i2
)))
2248 if ((f2
& SETSF1
) != 0
2249 && sh_insn_uses_or_sets_freg (i1
, op1
, SETSF1_REG (i2
)))
2252 /* The instructions do not conflict. */
2256 /* I1 is a load instruction, and I2 is some other instruction. Return
2257 TRUE if I1 loads a register which I2 uses. */
2260 sh_load_use (unsigned int i1
,
2261 const struct sh_opcode
*op1
,
2263 const struct sh_opcode
*op2
)
2269 if ((f1
& LOAD
) == 0)
2272 /* If both SETS1 and SETSSP are set, that means a load to a special
2273 register using postincrement addressing mode, which we don't care
2275 if ((f1
& SETS1
) != 0
2276 && (f1
& SETSSP
) == 0
2277 && sh_insn_uses_reg (i2
, op2
, (i1
& 0x0f00) >> 8))
2280 if ((f1
& SETSR0
) != 0
2281 && sh_insn_uses_reg (i2
, op2
, 0))
2284 if ((f1
& SETSF1
) != 0
2285 && sh_insn_uses_freg (i2
, op2
, (i1
& 0x0f00) >> 8))
2291 /* Try to align loads and stores within a span of memory. This is
2292 called by both the ELF and the COFF sh targets. ABFD and SEC are
2293 the BFD and section we are examining. CONTENTS is the contents of
2294 the section. SWAP is the routine to call to swap two instructions.
2295 RELOCS is a pointer to the internal relocation information, to be
2296 passed to SWAP. PLABEL is a pointer to the current label in a
2297 sorted list of labels; LABEL_END is the end of the list. START and
2298 STOP are the range of memory to examine. If a swap is made,
2299 *PSWAPPED is set to TRUE. */
2305 _bfd_sh_align_load_span (bfd
*abfd
,
2308 bool (*swap
) (bfd
*, asection
*, void *, bfd_byte
*, bfd_vma
),
2316 int dsp
= (abfd
->arch_info
->mach
== bfd_mach_sh_dsp
2317 || abfd
->arch_info
->mach
== bfd_mach_sh3_dsp
);
2320 /* The SH4 has a Harvard architecture, hence aligning loads is not
2321 desirable. In fact, it is counter-productive, since it interferes
2322 with the schedules generated by the compiler. */
2323 if (abfd
->arch_info
->mach
== bfd_mach_sh4
)
2326 /* If we are linking sh[3]-dsp code, swap the FPU instructions for DSP
2330 sh_opcodes
[0xf].minor_opcodes
= sh_dsp_opcodef
;
2331 sh_opcodes
[0xf].count
= sizeof sh_dsp_opcodef
/ sizeof sh_dsp_opcodef
[0];
2334 /* Instructions should be aligned on 2 byte boundaries. */
2335 if ((start
& 1) == 1)
2338 /* Now look through the unaligned addresses. */
2342 for (; i
< stop
; i
+= 4)
2345 const struct sh_opcode
*op
;
2346 unsigned int prev_insn
= 0;
2347 const struct sh_opcode
*prev_op
= NULL
;
2349 insn
= bfd_get_16 (abfd
, contents
+ i
);
2350 op
= sh_insn_info (insn
);
2352 || (op
->flags
& (LOAD
| STORE
)) == 0)
2355 /* This is a load or store which is not on a four byte boundary. */
2357 while (*plabel
< label_end
&& **plabel
< i
)
2362 prev_insn
= bfd_get_16 (abfd
, contents
+ i
- 2);
2363 /* If INSN is the field b of a parallel processing insn, it is not
2364 a load / store after all. Note that the test here might mistake
2365 the field_b of a pcopy insn for the starting code of a parallel
2366 processing insn; this might miss a swapping opportunity, but at
2367 least we're on the safe side. */
2368 if (dsp
&& (prev_insn
& 0xfc00) == 0xf800)
2371 /* Check if prev_insn is actually the field b of a parallel
2372 processing insn. Again, this can give a spurious match
2374 if (dsp
&& i
- 2 > start
)
2376 unsigned pprev_insn
= bfd_get_16 (abfd
, contents
+ i
- 4);
2378 if ((pprev_insn
& 0xfc00) == 0xf800)
2381 prev_op
= sh_insn_info (prev_insn
);
2384 prev_op
= sh_insn_info (prev_insn
);
2386 /* If the load/store instruction is in a delay slot, we
2389 || (prev_op
->flags
& DELAY
) != 0)
2393 && (*plabel
>= label_end
|| **plabel
!= i
)
2395 && (prev_op
->flags
& (LOAD
| STORE
)) == 0
2396 && ! sh_insns_conflict (prev_insn
, prev_op
, insn
, op
))
2400 /* The load/store instruction does not have a label, and
2401 there is a previous instruction; PREV_INSN is not
2402 itself a load/store instruction, and PREV_INSN and
2403 INSN do not conflict. */
2409 unsigned int prev2_insn
;
2410 const struct sh_opcode
*prev2_op
;
2412 prev2_insn
= bfd_get_16 (abfd
, contents
+ i
- 4);
2413 prev2_op
= sh_insn_info (prev2_insn
);
2415 /* If the instruction before PREV_INSN has a delay
2416 slot--that is, PREV_INSN is in a delay slot--we
2418 if (prev2_op
== NULL
2419 || (prev2_op
->flags
& DELAY
) != 0)
2422 /* If the instruction before PREV_INSN is a load,
2423 and it sets a register which INSN uses, then
2424 putting INSN immediately after PREV_INSN will
2425 cause a pipeline bubble, so there is no point to
2428 && (prev2_op
->flags
& LOAD
) != 0
2429 && sh_load_use (prev2_insn
, prev2_op
, insn
, op
))
2435 if (! (*swap
) (abfd
, sec
, relocs
, contents
, i
- 2))
2442 while (*plabel
< label_end
&& **plabel
< i
+ 2)
2446 && (*plabel
>= label_end
|| **plabel
!= i
+ 2))
2448 unsigned int next_insn
;
2449 const struct sh_opcode
*next_op
;
2451 /* There is an instruction after the load/store
2452 instruction, and it does not have a label. */
2453 next_insn
= bfd_get_16 (abfd
, contents
+ i
+ 2);
2454 next_op
= sh_insn_info (next_insn
);
2456 && (next_op
->flags
& (LOAD
| STORE
)) == 0
2457 && ! sh_insns_conflict (insn
, op
, next_insn
, next_op
))
2461 /* NEXT_INSN is not itself a load/store instruction,
2462 and it does not conflict with INSN. */
2466 /* If PREV_INSN is a load, and it sets a register
2467 which NEXT_INSN uses, then putting NEXT_INSN
2468 immediately after PREV_INSN will cause a pipeline
2469 bubble, so there is no reason to make this swap. */
2471 && (prev_op
->flags
& LOAD
) != 0
2472 && sh_load_use (prev_insn
, prev_op
, next_insn
, next_op
))
2475 /* If INSN is a load, and it sets a register which
2476 the insn after NEXT_INSN uses, then doing the
2477 swap will cause a pipeline bubble, so there is no
2478 reason to make the swap. However, if the insn
2479 after NEXT_INSN is itself a load or store
2480 instruction, then it is misaligned, so
2481 optimistically hope that it will be swapped
2482 itself, and just live with the pipeline bubble if
2486 && (op
->flags
& LOAD
) != 0)
2488 unsigned int next2_insn
;
2489 const struct sh_opcode
*next2_op
;
2491 next2_insn
= bfd_get_16 (abfd
, contents
+ i
+ 4);
2492 next2_op
= sh_insn_info (next2_insn
);
2493 if (next2_op
== NULL
2494 || ((next2_op
->flags
& (LOAD
| STORE
)) == 0
2495 && sh_load_use (insn
, op
, next2_insn
, next2_op
)))
2501 if (! (*swap
) (abfd
, sec
, relocs
, contents
, i
))
2512 #endif /* not COFF_IMAGE_WITH_PE */
2514 /* Swap two SH instructions. */
2517 sh_swap_insns (bfd
* abfd
,
2520 bfd_byte
* contents
,
2523 struct internal_reloc
*internal_relocs
= (struct internal_reloc
*) relocs
;
2524 unsigned short i1
, i2
;
2525 struct internal_reloc
*irel
, *irelend
;
2527 /* Swap the instructions themselves. */
2528 i1
= bfd_get_16 (abfd
, contents
+ addr
);
2529 i2
= bfd_get_16 (abfd
, contents
+ addr
+ 2);
2530 bfd_put_16 (abfd
, (bfd_vma
) i2
, contents
+ addr
);
2531 bfd_put_16 (abfd
, (bfd_vma
) i1
, contents
+ addr
+ 2);
2533 /* Adjust all reloc addresses. */
2534 irelend
= internal_relocs
+ sec
->reloc_count
;
2535 for (irel
= internal_relocs
; irel
< irelend
; irel
++)
2539 /* There are a few special types of relocs that we don't want to
2540 adjust. These relocs do not apply to the instruction itself,
2541 but are only associated with the address. */
2542 type
= irel
->r_type
;
2543 if (type
== R_SH_ALIGN
2544 || type
== R_SH_CODE
2545 || type
== R_SH_DATA
2546 || type
== R_SH_LABEL
)
2549 /* If an R_SH_USES reloc points to one of the addresses being
2550 swapped, we must adjust it. It would be incorrect to do this
2551 for a jump, though, since we want to execute both
2552 instructions after the jump. (We have avoided swapping
2553 around a label, so the jump will not wind up executing an
2554 instruction it shouldn't). */
2555 if (type
== R_SH_USES
)
2559 off
= irel
->r_vaddr
- sec
->vma
+ 4 + irel
->r_offset
;
2561 irel
->r_offset
+= 2;
2562 else if (off
== addr
+ 2)
2563 irel
->r_offset
-= 2;
2566 if (irel
->r_vaddr
- sec
->vma
== addr
)
2571 else if (irel
->r_vaddr
- sec
->vma
== addr
+ 2)
2582 unsigned short insn
, oinsn
;
2585 loc
= contents
+ irel
->r_vaddr
- sec
->vma
;
2592 case R_SH_PCDISP8BY2
:
2593 case R_SH_PCRELIMM8BY2
:
2594 insn
= bfd_get_16 (abfd
, loc
);
2597 if ((oinsn
& 0xff00) != (insn
& 0xff00))
2599 bfd_put_16 (abfd
, (bfd_vma
) insn
, loc
);
2603 insn
= bfd_get_16 (abfd
, loc
);
2606 if ((oinsn
& 0xf000) != (insn
& 0xf000))
2608 bfd_put_16 (abfd
, (bfd_vma
) insn
, loc
);
2611 case R_SH_PCRELIMM8BY4
:
2612 /* This reloc ignores the least significant 3 bits of
2613 the program counter before adding in the offset.
2614 This means that if ADDR is at an even address, the
2615 swap will not affect the offset. If ADDR is an at an
2616 odd address, then the instruction will be crossing a
2617 four byte boundary, and must be adjusted. */
2618 if ((addr
& 3) != 0)
2620 insn
= bfd_get_16 (abfd
, loc
);
2623 if ((oinsn
& 0xff00) != (insn
& 0xff00))
2625 bfd_put_16 (abfd
, (bfd_vma
) insn
, loc
);
2634 /* xgettext: c-format */
2635 (_("%pB: %#" PRIx64
": fatal: reloc overflow while relaxing"),
2636 abfd
, (uint64_t) irel
->r_vaddr
);
2637 bfd_set_error (bfd_error_bad_value
);
2646 /* Look for loads and stores which we can align to four byte
2647 boundaries. See the longer comment above sh_relax_section for why
2648 this is desirable. This sets *PSWAPPED if some instruction was
2652 sh_align_loads (bfd
*abfd
,
2654 struct internal_reloc
*internal_relocs
,
2658 struct internal_reloc
*irel
, *irelend
;
2659 bfd_vma
*labels
= NULL
;
2660 bfd_vma
*label
, *label_end
;
2665 irelend
= internal_relocs
+ sec
->reloc_count
;
2667 /* Get all the addresses with labels on them. */
2668 amt
= (bfd_size_type
) sec
->reloc_count
* sizeof (bfd_vma
);
2669 labels
= (bfd_vma
*) bfd_malloc (amt
);
2673 for (irel
= internal_relocs
; irel
< irelend
; irel
++)
2675 if (irel
->r_type
== R_SH_LABEL
)
2677 *label_end
= irel
->r_vaddr
- sec
->vma
;
2682 /* Note that the assembler currently always outputs relocs in
2683 address order. If that ever changes, this code will need to sort
2684 the label values and the relocs. */
2688 for (irel
= internal_relocs
; irel
< irelend
; irel
++)
2690 bfd_vma start
, stop
;
2692 if (irel
->r_type
!= R_SH_CODE
)
2695 start
= irel
->r_vaddr
- sec
->vma
;
2697 for (irel
++; irel
< irelend
; irel
++)
2698 if (irel
->r_type
== R_SH_DATA
)
2701 stop
= irel
->r_vaddr
- sec
->vma
;
2705 if (! _bfd_sh_align_load_span (abfd
, sec
, contents
, sh_swap_insns
,
2706 internal_relocs
, &label
,
2707 label_end
, start
, stop
, pswapped
))
2720 /* This is a modification of _bfd_coff_generic_relocate_section, which
2721 will handle SH relaxing. */
2724 sh_relocate_section (bfd
*output_bfd ATTRIBUTE_UNUSED
,
2725 struct bfd_link_info
*info
,
2727 asection
*input_section
,
2729 struct internal_reloc
*relocs
,
2730 struct internal_syment
*syms
,
2731 asection
**sections
)
2733 struct internal_reloc
*rel
;
2734 struct internal_reloc
*relend
;
2737 relend
= rel
+ input_section
->reloc_count
;
2738 for (; rel
< relend
; rel
++)
2741 struct coff_link_hash_entry
*h
;
2742 struct internal_syment
*sym
;
2745 reloc_howto_type
*howto
;
2746 bfd_reloc_status_type rstat
;
2748 /* Almost all relocs have to do with relaxing. If any work must
2749 be done for them, it has been done in sh_relax_section. */
2750 if (rel
->r_type
!= R_SH_IMM32
2752 && rel
->r_type
!= R_SH_IMM32CE
2753 && rel
->r_type
!= R_SH_IMAGEBASE
2755 && rel
->r_type
!= R_SH_PCDISP
)
2758 symndx
= rel
->r_symndx
;
2768 || (unsigned long) symndx
>= obj_raw_syment_count (input_bfd
))
2771 /* xgettext: c-format */
2772 (_("%pB: illegal symbol index %ld in relocs"),
2774 bfd_set_error (bfd_error_bad_value
);
2777 h
= obj_coff_sym_hashes (input_bfd
)[symndx
];
2778 sym
= syms
+ symndx
;
2781 if (sym
!= NULL
&& sym
->n_scnum
!= 0)
2782 addend
= - sym
->n_value
;
2786 if (rel
->r_type
== R_SH_PCDISP
)
2789 if (rel
->r_type
>= SH_COFF_HOWTO_COUNT
)
2792 howto
= &sh_coff_howtos
[rel
->r_type
];
2796 bfd_set_error (bfd_error_bad_value
);
2801 if (rel
->r_type
== R_SH_IMAGEBASE
)
2802 addend
-= pe_data (input_section
->output_section
->owner
)->pe_opthdr
.ImageBase
;
2811 /* There is nothing to do for an internal PCDISP reloc. */
2812 if (rel
->r_type
== R_SH_PCDISP
)
2817 sec
= bfd_abs_section_ptr
;
2822 sec
= sections
[symndx
];
2823 val
= (sec
->output_section
->vma
2824 + sec
->output_offset
2831 if (h
->root
.type
== bfd_link_hash_defined
2832 || h
->root
.type
== bfd_link_hash_defweak
)
2836 sec
= h
->root
.u
.def
.section
;
2837 val
= (h
->root
.u
.def
.value
2838 + sec
->output_section
->vma
2839 + sec
->output_offset
);
2841 else if (! bfd_link_relocatable (info
))
2842 (*info
->callbacks
->undefined_symbol
)
2843 (info
, h
->root
.root
.string
, input_bfd
, input_section
,
2844 rel
->r_vaddr
- input_section
->vma
, true);
2847 rstat
= _bfd_final_link_relocate (howto
, input_bfd
, input_section
,
2849 rel
->r_vaddr
- input_section
->vma
,
2858 case bfd_reloc_overflow
:
2861 char buf
[SYMNMLEN
+ 1];
2867 else if (sym
->_n
._n_n
._n_zeroes
== 0
2868 && sym
->_n
._n_n
._n_offset
!= 0)
2869 name
= obj_coff_strings (input_bfd
) + sym
->_n
._n_n
._n_offset
;
2872 strncpy (buf
, sym
->_n
._n_name
, SYMNMLEN
);
2873 buf
[SYMNMLEN
] = '\0';
2877 (*info
->callbacks
->reloc_overflow
)
2878 (info
, (h
? &h
->root
: NULL
), name
, howto
->name
,
2879 (bfd_vma
) 0, input_bfd
, input_section
,
2880 rel
->r_vaddr
- input_section
->vma
);
2888 /* This is a version of bfd_generic_get_relocated_section_contents
2889 which uses sh_relocate_section. */
2892 sh_coff_get_relocated_section_contents (bfd
*output_bfd
,
2893 struct bfd_link_info
*link_info
,
2894 struct bfd_link_order
*link_order
,
2899 asection
*input_section
= link_order
->u
.indirect
.section
;
2900 bfd
*input_bfd
= input_section
->owner
;
2901 asection
**sections
= NULL
;
2902 struct internal_reloc
*internal_relocs
= NULL
;
2903 struct internal_syment
*internal_syms
= NULL
;
2905 /* We only need to handle the case of relaxing, or of having a
2906 particular set of section contents, specially. */
2908 || coff_section_data (input_bfd
, input_section
) == NULL
2909 || coff_section_data (input_bfd
, input_section
)->contents
== NULL
)
2910 return bfd_generic_get_relocated_section_contents (output_bfd
, link_info
,
2915 bfd_byte
*orig_data
= data
;
2918 data
= bfd_malloc (input_section
->size
);
2922 memcpy (data
, coff_section_data (input_bfd
, input_section
)->contents
,
2923 (size_t) input_section
->size
);
2925 if ((input_section
->flags
& SEC_RELOC
) != 0
2926 && input_section
->reloc_count
> 0)
2928 bfd_size_type symesz
= bfd_coff_symesz (input_bfd
);
2929 bfd_byte
*esym
, *esymend
;
2930 struct internal_syment
*isymp
;
2934 if (! _bfd_coff_get_external_symbols (input_bfd
))
2937 internal_relocs
= (_bfd_coff_read_internal_relocs
2938 (input_bfd
, input_section
, false, (bfd_byte
*) NULL
,
2939 false, (struct internal_reloc
*) NULL
));
2940 if (internal_relocs
== NULL
)
2943 amt
= obj_raw_syment_count (input_bfd
);
2944 amt
*= sizeof (struct internal_syment
);
2945 internal_syms
= (struct internal_syment
*) bfd_malloc (amt
);
2946 if (internal_syms
== NULL
)
2949 amt
= obj_raw_syment_count (input_bfd
);
2950 amt
*= sizeof (asection
*);
2951 sections
= (asection
**) bfd_malloc (amt
);
2952 if (sections
== NULL
)
2955 isymp
= internal_syms
;
2957 esym
= (bfd_byte
*) obj_coff_external_syms (input_bfd
);
2958 esymend
= esym
+ obj_raw_syment_count (input_bfd
) * symesz
;
2959 while (esym
< esymend
)
2961 bfd_coff_swap_sym_in (input_bfd
, esym
, isymp
);
2963 if (isymp
->n_scnum
!= 0)
2964 *secpp
= coff_section_from_bfd_index (input_bfd
, isymp
->n_scnum
);
2967 if (isymp
->n_value
== 0)
2968 *secpp
= bfd_und_section_ptr
;
2970 *secpp
= bfd_com_section_ptr
;
2973 esym
+= (isymp
->n_numaux
+ 1) * symesz
;
2974 secpp
+= isymp
->n_numaux
+ 1;
2975 isymp
+= isymp
->n_numaux
+ 1;
2978 if (! sh_relocate_section (output_bfd
, link_info
, input_bfd
,
2979 input_section
, data
, internal_relocs
,
2980 internal_syms
, sections
))
2985 free (internal_syms
);
2986 internal_syms
= NULL
;
2987 free (internal_relocs
);
2988 internal_relocs
= NULL
;
2994 free (internal_relocs
);
2995 free (internal_syms
);
2997 if (orig_data
== NULL
)
3002 /* The target vectors. */
3004 #ifndef TARGET_SHL_SYM
3005 CREATE_BIG_COFF_TARGET_VEC (sh_coff_vec
, "coff-sh", BFD_IS_RELAXABLE
, 0, '_', NULL
, COFF_SWAP_TABLE
)
3008 #ifdef TARGET_SHL_SYM
3009 #define TARGET_SYM TARGET_SHL_SYM
3011 #define TARGET_SYM sh_coff_le_vec
3014 #ifndef TARGET_SHL_NAME
3015 #define TARGET_SHL_NAME "coff-shl"
3019 CREATE_LITTLE_COFF_TARGET_VEC (TARGET_SYM
, TARGET_SHL_NAME
, BFD_IS_RELAXABLE
,
3020 SEC_CODE
| SEC_DATA
, '_', NULL
, COFF_SWAP_TABLE
);
3022 CREATE_LITTLE_COFF_TARGET_VEC (TARGET_SYM
, TARGET_SHL_NAME
, BFD_IS_RELAXABLE
,
3023 0, '_', NULL
, COFF_SWAP_TABLE
)
3026 #ifndef TARGET_SHL_SYM
3028 /* Some people want versions of the SH COFF target which do not align
3029 to 16 byte boundaries. We implement that by adding a couple of new
3030 target vectors. These are just like the ones above, but they
3031 change the default section alignment. To generate them in the
3032 assembler, use -small. To use them in the linker, use -b
3033 coff-sh{l}-small and -oformat coff-sh{l}-small.
3035 Yes, this is a horrible hack. A general solution for setting
3036 section alignment in COFF is rather complex. ELF handles this
3039 /* Only recognize the small versions if the target was not defaulted.
3040 Otherwise we won't recognize the non default endianness. */
3043 coff_small_object_p (bfd
*abfd
)
3045 if (abfd
->target_defaulted
)
3047 bfd_set_error (bfd_error_wrong_format
);
3050 return coff_object_p (abfd
);
3053 /* Set the section alignment for the small versions. */
3056 coff_small_new_section_hook (bfd
*abfd
, asection
*section
)
3058 if (! coff_new_section_hook (abfd
, section
))
3061 /* We must align to at least a four byte boundary, because longword
3062 accesses must be on a four byte boundary. */
3063 if (section
->alignment_power
== COFF_DEFAULT_SECTION_ALIGNMENT_POWER
)
3064 section
->alignment_power
= 2;
3069 /* This is copied from bfd_coff_std_swap_table so that we can change
3070 the default section alignment power. */
3072 static const bfd_coff_backend_data bfd_coff_small_swap_table
=
3074 coff_swap_aux_in
, coff_swap_sym_in
, coff_swap_lineno_in
,
3075 coff_swap_aux_out
, coff_swap_sym_out
,
3076 coff_swap_lineno_out
, coff_swap_reloc_out
,
3077 coff_swap_filehdr_out
, coff_swap_aouthdr_out
,
3078 coff_swap_scnhdr_out
,
3079 FILHSZ
, AOUTSZ
, SCNHSZ
, SYMESZ
, AUXESZ
, RELSZ
, LINESZ
, FILNMLEN
,
3080 #ifdef COFF_LONG_FILENAMES
3085 COFF_DEFAULT_LONG_SECTION_NAMES
,
3087 #ifdef COFF_FORCE_SYMBOLS_IN_STRINGS
3092 #ifdef COFF_DEBUG_STRING_WIDE_PREFIX
3098 coff_swap_filehdr_in
, coff_swap_aouthdr_in
, coff_swap_scnhdr_in
,
3099 coff_swap_reloc_in
, coff_bad_format_hook
, coff_set_arch_mach_hook
,
3100 coff_mkobject_hook
, styp_to_sec_flags
, coff_set_alignment_hook
,
3101 coff_slurp_symbol_table
, symname_in_debug_hook
, coff_pointerize_aux_hook
,
3102 coff_print_aux
, coff_reloc16_extra_cases
, coff_reloc16_estimate
,
3103 coff_classify_symbol
, coff_compute_section_file_positions
,
3104 coff_start_final_link
, coff_relocate_section
, coff_rtype_to_howto
,
3105 coff_adjust_symndx
, coff_link_add_one_symbol
,
3106 coff_link_output_has_begun
, coff_final_link_postscript
,
3110 #define coff_small_close_and_cleanup \
3111 coff_close_and_cleanup
3112 #define coff_small_bfd_free_cached_info \
3113 coff_bfd_free_cached_info
3114 #define coff_small_get_section_contents \
3115 coff_get_section_contents
3116 #define coff_small_get_section_contents_in_window \
3117 coff_get_section_contents_in_window
3119 extern const bfd_target sh_coff_small_le_vec
;
3121 const bfd_target sh_coff_small_vec
=
3123 "coff-sh-small", /* name */
3124 bfd_target_coff_flavour
,
3125 BFD_ENDIAN_BIG
, /* data byte order is big */
3126 BFD_ENDIAN_BIG
, /* header byte order is big */
3128 (HAS_RELOC
| EXEC_P
/* object flags */
3129 | HAS_LINENO
| HAS_DEBUG
3130 | HAS_SYMS
| HAS_LOCALS
| WP_TEXT
| BFD_IS_RELAXABLE
),
3132 (SEC_HAS_CONTENTS
| SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
),
3133 '_', /* leading symbol underscore */
3134 '/', /* ar_pad_char */
3135 15, /* ar_max_namelen */
3136 0, /* match priority. */
3137 TARGET_KEEP_UNUSED_SECTION_SYMBOLS
, /* keep unused section symbols. */
3138 bfd_getb64
, bfd_getb_signed_64
, bfd_putb64
,
3139 bfd_getb32
, bfd_getb_signed_32
, bfd_putb32
,
3140 bfd_getb16
, bfd_getb_signed_16
, bfd_putb16
, /* data */
3141 bfd_getb64
, bfd_getb_signed_64
, bfd_putb64
,
3142 bfd_getb32
, bfd_getb_signed_32
, bfd_putb32
,
3143 bfd_getb16
, bfd_getb_signed_16
, bfd_putb16
, /* hdrs */
3145 { /* bfd_check_format */
3147 coff_small_object_p
,
3148 bfd_generic_archive_p
,
3151 { /* bfd_set_format */
3152 _bfd_bool_bfd_false_error
,
3154 _bfd_generic_mkarchive
,
3155 _bfd_bool_bfd_false_error
3157 { /* bfd_write_contents */
3158 _bfd_bool_bfd_false_error
,
3159 coff_write_object_contents
,
3160 _bfd_write_archive_contents
,
3161 _bfd_bool_bfd_false_error
3164 BFD_JUMP_TABLE_GENERIC (coff_small
),
3165 BFD_JUMP_TABLE_COPY (coff
),
3166 BFD_JUMP_TABLE_CORE (_bfd_nocore
),
3167 BFD_JUMP_TABLE_ARCHIVE (_bfd_archive_coff
),
3168 BFD_JUMP_TABLE_SYMBOLS (coff
),
3169 BFD_JUMP_TABLE_RELOCS (coff
),
3170 BFD_JUMP_TABLE_WRITE (coff
),
3171 BFD_JUMP_TABLE_LINK (coff
),
3172 BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic
),
3174 &sh_coff_small_le_vec
,
3176 &bfd_coff_small_swap_table
3179 const bfd_target sh_coff_small_le_vec
=
3181 "coff-shl-small", /* name */
3182 bfd_target_coff_flavour
,
3183 BFD_ENDIAN_LITTLE
, /* data byte order is little */
3184 BFD_ENDIAN_LITTLE
, /* header byte order is little endian too*/
3186 (HAS_RELOC
| EXEC_P
/* object flags */
3187 | HAS_LINENO
| HAS_DEBUG
3188 | HAS_SYMS
| HAS_LOCALS
| WP_TEXT
| BFD_IS_RELAXABLE
),
3190 (SEC_HAS_CONTENTS
| SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
),
3191 '_', /* leading symbol underscore */
3192 '/', /* ar_pad_char */
3193 15, /* ar_max_namelen */
3194 0, /* match priority. */
3195 TARGET_KEEP_UNUSED_SECTION_SYMBOLS
, /* keep unused section symbols. */
3196 bfd_getl64
, bfd_getl_signed_64
, bfd_putl64
,
3197 bfd_getl32
, bfd_getl_signed_32
, bfd_putl32
,
3198 bfd_getl16
, bfd_getl_signed_16
, bfd_putl16
, /* data */
3199 bfd_getl64
, bfd_getl_signed_64
, bfd_putl64
,
3200 bfd_getl32
, bfd_getl_signed_32
, bfd_putl32
,
3201 bfd_getl16
, bfd_getl_signed_16
, bfd_putl16
, /* hdrs */
3203 { /* bfd_check_format */
3205 coff_small_object_p
,
3206 bfd_generic_archive_p
,
3209 { /* bfd_set_format */
3210 _bfd_bool_bfd_false_error
,
3212 _bfd_generic_mkarchive
,
3213 _bfd_bool_bfd_false_error
3215 { /* bfd_write_contents */
3216 _bfd_bool_bfd_false_error
,
3217 coff_write_object_contents
,
3218 _bfd_write_archive_contents
,
3219 _bfd_bool_bfd_false_error
3222 BFD_JUMP_TABLE_GENERIC (coff_small
),
3223 BFD_JUMP_TABLE_COPY (coff
),
3224 BFD_JUMP_TABLE_CORE (_bfd_nocore
),
3225 BFD_JUMP_TABLE_ARCHIVE (_bfd_archive_coff
),
3226 BFD_JUMP_TABLE_SYMBOLS (coff
),
3227 BFD_JUMP_TABLE_RELOCS (coff
),
3228 BFD_JUMP_TABLE_WRITE (coff
),
3229 BFD_JUMP_TABLE_LINK (coff
),
3230 BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic
),
3234 &bfd_coff_small_swap_table