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[binutils-gdb.git] / opcodes / v850-opc.c
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1 /* Assemble V850 instructions.
2 Copyright (C) 1996-2024 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
21 #include "sysdep.h"
22 #include <stdio.h>
23 #include "opcode/v850.h"
24 #include "bfd.h"
25 #include "opintl.h"
27 /* Regular opcodes. */
28 #define OP(x) ((x & 0x3f) << 5)
29 #define OP_MASK OP (0x3f)
31 /* Conditional branch opcodes (Format III). */
32 #define BOP(x) ((0x58 << 4) | (x & 0x0f))
33 #define BOP_MASK ((0x78 << 4) | 0x0f)
35 /* Conditional branch opcodes (Format VII). */
36 #define BOP7(x) (0x107e0 | (x & 0xf))
37 #define BOP7_MASK (0x1ffe0 | 0xf)
39 /* One-word opcodes. */
40 #define one(x) ((unsigned int) (x))
42 /* Two-word opcodes. */
43 #define two(x,y) ((unsigned int) (x) | ((unsigned int) (y) << 16))
46 /* The functions used to insert and extract complicated operands. */
48 /* Note: There is a conspiracy between these functions and
49 v850_insert_operand() in gas/config/tc-v850.c. Error messages
50 containing the string 'out of range' will be ignored unless a
51 specific command line option is given to GAS. */
53 static const char * not_valid = N_ ("displacement value is not in range and is not aligned");
54 static const char * out_of_range = N_ ("displacement value is out of range");
55 static const char * not_aligned = N_ ("displacement value is not aligned");
57 static const char * immediate_out_of_range = N_ ("immediate value is out of range");
58 static const char * branch_out_of_range = N_ ("branch value out of range");
59 static const char * branch_out_of_range_and_odd_offset = N_ ("branch value not in range and to odd offset");
60 static const char * branch_to_odd_offset = N_ ("branch to odd offset");
61 static const char * pos_out_of_range = N_ ("position value is out of range");
62 static const char * width_out_of_range = N_ ("width value is out of range");
63 static const char * selid_out_of_range = N_ ("SelID is out of range");
64 static const char * vector8_out_of_range = N_ ("vector8 is out of range");
65 static const char * vector5_out_of_range = N_ ("vector5 is out of range");
66 static const char * imm10_out_of_range = N_ ("imm10 is out of range");
67 static const char * sr_selid_out_of_range = N_ ("SR/SelID is out of range");
69 int
70 v850_msg_is_out_of_range (const char* msg)
72 return msg == out_of_range
73 || msg == immediate_out_of_range
74 || msg == branch_out_of_range;
77 static unsigned long
78 insert_i5div1 (unsigned long insn, unsigned long value, const char ** errmsg)
80 if (value > 30 || value < 2)
82 if (value & 1)
83 * errmsg = _(not_valid);
84 else
85 * errmsg = _(out_of_range);
87 else if (value & 1)
88 * errmsg = _(not_aligned);
90 value = (32 - value)/2;
92 return (insn | ((value << (2+16)) & 0x3c0000));
95 static unsigned long
96 extract_i5div1 (unsigned long insn, int * invalid)
98 unsigned long ret = (insn & 0x003c0000) >> (16+2);
99 ret = 32 - (ret * 2);
101 if (invalid != 0)
102 *invalid = (ret > 30 || ret < 2) ? 1 : 0;
103 return ret;
106 static unsigned long
107 insert_i5div2 (unsigned long insn, unsigned long value, const char ** errmsg)
109 if (value > 30 || value < 4)
111 if (value & 1)
112 * errmsg = _(not_valid);
113 else
114 * errmsg = _(out_of_range);
116 else if (value & 1)
117 * errmsg = _(not_aligned);
119 value = (32 - value)/2;
121 return insn | ((value << (2 + 16)) & 0x3c0000);
124 static unsigned long
125 extract_i5div2 (unsigned long insn, int * invalid)
127 unsigned long ret = (insn & 0x003c0000) >> (16+2);
128 ret = 32 - (ret * 2);
130 if (invalid != 0)
131 *invalid = (ret > 30 || ret < 4) ? 1 : 0;
132 return ret;
135 static unsigned long
136 insert_i5div3 (unsigned long insn, unsigned long value, const char ** errmsg)
138 if (value > 32 || value < 2)
140 if (value & 1)
141 * errmsg = _(not_valid);
142 else
143 * errmsg = _(out_of_range);
145 else if (value & 1)
146 * errmsg = _(not_aligned);
148 value = (32 - value)/2;
150 return insn | ((value << (2+16)) & 0x3c0000);
153 static unsigned long
154 extract_i5div3 (unsigned long insn, int * invalid)
156 unsigned long ret = (insn & 0x003c0000) >> (16+2);
157 ret = 32 - (ret * 2);
159 if (invalid != 0)
160 *invalid = (ret > 32 || ret < 2) ? 1 : 0;
161 return ret;
164 static unsigned long
165 insert_d5_4 (unsigned long insn, unsigned long value, const char ** errmsg)
167 if (value > 0x1f)
169 if (value & 1)
170 * errmsg = _(not_valid);
171 else
172 * errmsg = _(out_of_range);
174 else if (value & 1)
175 * errmsg = _(not_aligned);
177 value >>= 1;
179 return insn | (value & 0x0f);
182 static unsigned long
183 extract_d5_4 (unsigned long insn, int * invalid)
185 unsigned long ret = (insn & 0x0f);
187 ret <<= 1;
189 if (invalid != 0)
190 *invalid = 0;
191 return ret;
194 static unsigned long
195 insert_d8_6 (unsigned long insn, unsigned long value, const char ** errmsg)
197 if (value > 0xff)
199 if ((value % 4) != 0)
200 * errmsg = _(not_valid);
201 else
202 * errmsg = _(out_of_range);
204 else if ((value % 4) != 0)
205 * errmsg = _(not_aligned);
207 value >>= 1;
209 return insn | (value & 0x7e);
212 static unsigned long
213 extract_d8_6 (unsigned long insn, int * invalid)
215 unsigned long ret = (insn & 0x7e);
217 ret <<= 1;
219 if (invalid != 0)
220 *invalid = 0;
221 return ret;
224 static unsigned long
225 insert_d8_7 (unsigned long insn, unsigned long value, const char ** errmsg)
227 if (value > 0xff)
229 if ((value % 2) != 0)
230 * errmsg = _(not_valid);
231 else
232 * errmsg = _(out_of_range);
234 else if ((value % 2) != 0)
235 * errmsg = _(not_aligned);
237 value >>= 1;
239 return insn | (value & 0x7f);
242 static unsigned long
243 extract_d8_7 (unsigned long insn, int * invalid)
245 unsigned long ret = (insn & 0x7f);
247 ret <<= 1;
249 if (invalid != 0)
250 *invalid = 0;
251 return ret;
254 static unsigned long
255 insert_v8 (unsigned long insn, unsigned long value, const char ** errmsg)
257 if (value > 0xff)
258 * errmsg = _(immediate_out_of_range);
260 return insn | (value & 0x1f) | ((value & 0xe0) << (27-5));
263 static unsigned long
264 extract_v8 (unsigned long insn, int * invalid)
266 unsigned long ret = (insn & 0x1f) | ((insn >> (27-5)) & 0xe0);
268 if (invalid != 0)
269 *invalid = 0;
270 return ret;
273 static unsigned long
274 insert_d9 (unsigned long insn, unsigned long value, const char ** errmsg)
276 if (value + 0x100 > 0x1ff)
278 if ((value % 2) != 0)
279 * errmsg = branch_out_of_range_and_odd_offset;
280 else
281 * errmsg = branch_out_of_range;
283 else if ((value % 2) != 0)
284 * errmsg = branch_to_odd_offset;
286 return insn | ((value & 0x1f0) << 7) | ((value & 0x0e) << 3);
289 static unsigned long
290 extract_d9 (unsigned long insn, int * invalid)
292 unsigned long ret = ((insn >> 7) & 0x1f0) | ((insn >> 3) & 0x0e);
294 ret = (ret ^ 0x100) - 0x100;
296 if (invalid != 0)
297 *invalid = 0;
298 return ret;
301 static unsigned long
302 insert_u16_loop (unsigned long insn, unsigned long value, const char ** errmsg)
304 /* Loop displacement is encoded as a positive value,
305 even though the instruction branches backwards. */
306 if (value > 0xffff)
308 if ((value % 2) != 0)
309 * errmsg = branch_out_of_range_and_odd_offset;
310 else
311 * errmsg = branch_out_of_range;
313 else if ((value % 2) != 0)
314 * errmsg = branch_to_odd_offset;
316 return insn | ((value & 0xfffe) << 16);
319 static unsigned long
320 extract_u16_loop (unsigned long insn, int * invalid)
322 long ret = (insn >> 16) & 0xfffe;
324 if (invalid != 0)
325 *invalid = 0;
326 return ret;
329 static unsigned long
330 insert_d16_15 (unsigned long insn, unsigned long value, const char ** errmsg)
332 if (value + 0x8000 > 0xffff)
334 if ((value % 2) != 0)
335 * errmsg = _(not_valid);
336 else
337 * errmsg = _(out_of_range);
339 else if ((value % 2) != 0)
340 * errmsg = _(not_aligned);
342 return insn | ((value & 0xfffe) << 16);
345 static unsigned long
346 extract_d16_15 (unsigned long insn, int * invalid)
348 unsigned long ret = (insn >> 16) & 0xfffe;
350 ret = (ret ^ 0x8000) - 0x8000;
352 if (invalid != 0)
353 *invalid = 0;
354 return ret;
357 static unsigned long
358 insert_d16_16 (unsigned long insn, unsigned long value, const char ** errmsg)
360 if (value + 0x8000 > 0xffff)
361 * errmsg = _(out_of_range);
363 return insn | ((value & 0xfffe) << 16) | ((value & 1) << 5);
366 static unsigned long
367 extract_d16_16 (unsigned long insn, int * invalid)
369 unsigned long ret = ((insn >> 16) & 0xfffe) | ((insn >> 5) & 1);
371 ret = (ret ^ 0x8000) - 0x8000;
373 if (invalid != 0)
374 *invalid = 0;
375 return ret;
378 static unsigned long
379 insert_d17_16 (unsigned long insn, unsigned long value, const char ** errmsg)
381 if (value + 0x10000 > 0x1ffff)
382 * errmsg = _(out_of_range);
384 return insn | ((value & 0xfffe) << 16) | ((value & 0x10000) >> (16 - 4));
387 static unsigned long
388 extract_d17_16 (unsigned long insn, int * invalid)
390 unsigned long ret = ((insn >> 16) & 0xfffe) | ((insn << (16 - 4)) & 0x10000);
392 ret = (ret ^ 0x10000) - 0x10000;
394 if (invalid != 0)
395 *invalid = 0;
396 return ret;
399 static unsigned long
400 insert_d22 (unsigned long insn, unsigned long value, const char ** errmsg)
402 if (value + 0x200000 > 0x3fffff)
404 if ((value % 2) != 0)
405 * errmsg = branch_out_of_range_and_odd_offset;
406 else
407 * errmsg = branch_out_of_range;
409 else if ((value % 2) != 0)
410 * errmsg = branch_to_odd_offset;
412 return insn | ((value & 0xfffe) << 16) | ((value & 0x3f0000) >> 16);
415 static unsigned long
416 extract_d22 (unsigned long insn, int * invalid)
418 unsigned long ret = ((insn >> 16) & 0xfffe) | ((insn << 16) & 0x3f0000);
420 ret = (ret ^ 0x200000) - 0x200000;
422 if (invalid != 0)
423 *invalid = 0;
424 return ret;
427 static unsigned long
428 insert_d23 (unsigned long insn, unsigned long value, const char ** errmsg)
430 if (value + 0x400000 > 0x7fffff)
431 * errmsg = out_of_range;
433 return insn | ((value & 0x7f) << 4) | ((value & 0x7fff80) << (16-7));
436 static unsigned long
437 insert_d23_align1 (unsigned long insn, unsigned long value, const char ** errmsg)
439 if (value + 0x400000 > 0x7fffff)
441 if (value & 0x1)
442 * errmsg = _(not_valid);
443 else
444 * errmsg = _(out_of_range);
446 else if (value & 0x1)
447 * errmsg = _(not_aligned);
449 return insn | ((value & 0x7e) << 4) | ((value & 0x7fff80) << (16 - 7));
452 static unsigned long
453 extract_d23 (unsigned long insn, int * invalid)
455 unsigned long ret = ((insn >> 4) & 0x7f) | ((insn >> (16-7)) & 0x7fff80);
457 ret = (ret ^ 0x400000) - 0x400000;
459 if (invalid != 0)
460 *invalid = 0;
461 return ret;
464 static unsigned long
465 insert_i9 (unsigned long insn, unsigned long value, const char ** errmsg)
467 if (value + 0x100 > 0x1ff)
468 * errmsg = _(immediate_out_of_range);
470 return insn | ((value & 0x1e0) << 13) | (value & 0x1f);
473 static unsigned long
474 extract_i9 (unsigned long insn, int * invalid)
476 unsigned long ret = ((insn >> 13) & 0x1e0) | (insn & 0x1f);
478 ret = (ret ^ 0x100) - 0x100;
480 if (invalid != 0)
481 *invalid = 0;
482 return ret;
485 static unsigned long
486 insert_u9 (unsigned long insn, unsigned long value, const char ** errmsg)
488 if (value > 0x1ff)
489 * errmsg = _(immediate_out_of_range);
491 return insn | ((value & 0x1e0) << 13) | (value & 0x1f);
494 static unsigned long
495 extract_u9 (unsigned long insn, int * invalid)
497 unsigned long ret = ((insn >> 13) & 0x1e0) | (insn & 0x1f);
499 if (invalid != 0)
500 *invalid = 0;
501 return ret;
504 static unsigned long
505 insert_spe (unsigned long insn, unsigned long value, const char ** errmsg)
507 if (value != 3)
508 * errmsg = _("invalid register for stack adjustment");
510 return insn & ~0x180000;
513 static unsigned long
514 extract_spe (unsigned long insn ATTRIBUTE_UNUSED, int * invalid)
516 if (invalid != 0)
517 *invalid = 0;
519 return 3;
522 static unsigned long
523 insert_r4 (unsigned long insn, unsigned long value, const char ** errmsg)
525 if (value >= 32)
526 * errmsg = _("invalid register name");
528 return insn | ((value & 0x01) << 23) | ((value & 0x1e) << 16);
531 static unsigned long
532 extract_r4 (unsigned long insn, int * invalid)
534 unsigned long r4;
535 unsigned long insn2;
537 insn2 = insn >> 16;
538 r4 = (((insn2 & 0x0080) >> 7) | (insn2 & 0x001e));
540 if (invalid != 0)
541 *invalid = 0;
543 return r4;
546 static unsigned long G_pos;
548 static unsigned long
549 insert_POS (unsigned long insn, unsigned long pos, const char ** errmsg)
551 if (pos > 0x1f)
552 * errmsg = _(pos_out_of_range);
554 G_pos = pos;
556 return insn; /* Not an oparaton until WIDTH. */
559 static unsigned long
560 extract_POS_U (unsigned long insn, int * invalid)
562 unsigned long pos,lsb;
563 unsigned long insn2;
564 insn2 = insn >> 16;
566 lsb = ((insn2 & 0x0800) >> 8)
567 | ((insn2 & 0x000e) >> 1);
568 lsb += 16;
569 pos = lsb;
571 if (invalid != 0)
572 *invalid = 0;
574 return pos;
577 static unsigned long
578 extract_POS_L (unsigned long insn, int * invalid)
580 unsigned long pos,lsb;
581 unsigned long insn2;
582 insn2 = insn >> 16;
584 lsb = ((insn2 & 0x0800) >> 8)
585 | ((insn2 & 0x000e) >> 1);
586 pos = lsb;
588 if (invalid != 0)
589 *invalid = 0;
591 return pos;
594 static unsigned long
595 insert_WIDTH (unsigned long insn, unsigned long width, const char ** errmsg)
597 unsigned long msb, lsb, opc, ret;
598 unsigned long msb_expand, lsb_expand;
600 msb = width + G_pos - 1;
601 lsb = G_pos;
602 opc = 0;
603 G_pos = 0;
605 if (width > 0x20)
606 * errmsg = _(width_out_of_range);
608 if ((msb >= 16) && (lsb >= 16))
609 opc = 0x0090;
610 else if ((msb >= 16) && (lsb < 16))
611 opc = 0x00b0;
612 else if ((msb < 16) && (lsb < 16))
613 opc = 0x00d0;
614 else
615 * errmsg = _(width_out_of_range);
617 msb &= 0x0f;
618 msb_expand = msb << 12;
619 lsb &= 0x0f;
620 lsb_expand = ((lsb & 0x8) << 8)|((lsb & 0x7) << 1);
622 ret = (insn & 0x0000ffff) | ((opc | msb_expand | lsb_expand) << 16);
624 return ret;
627 static unsigned long
628 extract_WIDTH_U (unsigned long insn, int * invalid)
630 unsigned long width, msb, lsb;
631 unsigned long insn2;
632 insn2 = insn >> 16;
634 msb = ((insn2 & 0xf000) >> 12);
635 msb += 16;
636 lsb = ((insn2 & 0x0800) >> 8)
637 | ((insn2 & 0x000e) >> 1);
638 lsb += 16;
640 if (invalid != 0)
641 *invalid = 0;
643 width = msb - lsb + 1;
645 return width;
648 static unsigned long
649 extract_WIDTH_M (unsigned long insn, int * invalid)
651 unsigned long width, msb, lsb;
652 unsigned long insn2;
653 insn2 = insn >> 16;
655 msb = ((insn2 & 0xf000) >> 12) ;
656 msb += 16;
657 lsb = ((insn2 & 0x0800) >> 8)
658 | ((insn2 & 0x000e) >> 1);
660 if (invalid != 0)
661 *invalid = 0;
663 width = msb - lsb + 1;
665 return width;
668 static unsigned long
669 extract_WIDTH_L (unsigned long insn, int * invalid)
671 unsigned long width, msb, lsb;
672 unsigned long insn2;
673 insn2 = insn >> 16;
675 msb = ((insn2 & 0xf000) >> 12) ;
676 lsb = ((insn2 & 0x0800) >> 8)
677 | ((insn2 & 0x000e) >> 1);
679 if (invalid != 0)
680 *invalid = 0;
682 width = msb - lsb + 1;
684 return width;
687 static unsigned long
688 insert_SELID (unsigned long insn, unsigned long selid, const char ** errmsg)
690 if (selid > 0x1f)
691 * errmsg = _(selid_out_of_range);
693 return insn | ((selid & 0x1fUL) << 27);
696 static unsigned long
697 extract_SELID (unsigned long insn, int * invalid)
699 unsigned long selid;
700 unsigned long insn2;
702 insn2 = insn >> 16;
704 selid = ((insn2 & 0xf800) >> 11);
706 if (invalid != 0)
707 *invalid = 0;
709 return selid;
712 static unsigned long
713 insert_VECTOR8 (unsigned long insn, unsigned long vector8, const char ** errmsg)
715 unsigned long ret;
716 unsigned long VVV, vvvvv;
718 if (vector8 > 0xff)
719 * errmsg = _(vector8_out_of_range);
721 VVV = (vector8 & 0xe0) >> 5;
722 vvvvv = (vector8 & 0x1f);
724 ret = (insn | (VVV << 27) | vvvvv);
726 return ret;
729 static unsigned long
730 extract_VECTOR8 (unsigned long insn, int * invalid)
732 unsigned long vector8;
733 unsigned long VVV,vvvvv;
734 unsigned long insn2;
736 insn2 = insn >> 16;
737 VVV = ((insn2 & 0x3800) >> 11);
738 vvvvv = (insn & 0x001f);
739 vector8 = VVV << 5 | vvvvv;
741 if (invalid != 0)
742 *invalid = 0;
744 return vector8;
747 static unsigned long
748 insert_VECTOR5 (unsigned long insn, unsigned long vector5, const char ** errmsg)
750 unsigned long ret;
751 unsigned long vvvvv;
753 if (vector5 > 0x1f)
754 * errmsg = _(vector5_out_of_range);
756 vvvvv = (vector5 & 0x1f);
758 ret = (insn | vvvvv);
760 return ret;
763 static unsigned long
764 extract_VECTOR5 (unsigned long insn, int * invalid)
766 unsigned long vector5;
768 vector5 = (insn & 0x001f);
770 if (invalid != 0)
771 *invalid = 0;
773 return vector5;
776 static unsigned long
777 insert_CACHEOP (unsigned long insn, unsigned long cacheop, const char ** errmsg ATTRIBUTE_UNUSED)
779 unsigned long ret;
780 unsigned long pp, PPPPP;
782 pp = (cacheop & 0x60) >> 5;
783 PPPPP = (cacheop & 0x1f);
785 ret = insn | (pp << 11) | (PPPPP << 27);
787 return ret;
790 static unsigned long
791 extract_CACHEOP (unsigned long insn, int * invalid)
793 unsigned long ret;
794 unsigned long pp, PPPPP;
795 unsigned long insn2;
797 insn2 = insn >> 16;
799 PPPPP = ((insn2 & 0xf800) >> 11);
800 pp = ((insn & 0x1800) >> 11);
802 ret = (pp << 5) | PPPPP;
804 if (invalid != 0)
805 *invalid = 0;
807 return ret;
810 static unsigned long
811 insert_PREFOP (unsigned long insn, unsigned long prefop, const char ** errmsg ATTRIBUTE_UNUSED)
813 unsigned long ret;
814 unsigned long PPPPP;
816 PPPPP = (prefop & 0x1f);
818 ret = insn | (PPPPP << 27);
820 return ret;
823 static unsigned long
824 extract_PREFOP (unsigned long insn, int * invalid)
826 unsigned long ret;
827 unsigned long PPPPP;
828 unsigned long insn2;
830 insn2 = insn >> 16;
832 PPPPP = (insn2 & 0xf800) >> 11;
834 ret = PPPPP;
836 if (invalid != 0)
837 *invalid = 0;
839 return ret;
842 static unsigned long
843 insert_IMM10U (unsigned long insn, unsigned long value, const char ** errmsg)
845 unsigned long imm10, ret;
846 unsigned long iiiii,IIIII;
848 if (value > 0x3ff)
849 * errmsg = _(imm10_out_of_range);
851 imm10 = value & 0x3ff;
852 IIIII = (imm10 >> 5) & 0x1f;
853 iiiii = imm10 & 0x1f;
855 ret = insn | IIIII << 27 | iiiii;
857 return ret;
860 static unsigned long
861 extract_IMM10U (unsigned long insn, int * invalid)
863 unsigned long ret;
864 unsigned long iiiii,IIIII;
865 unsigned long insn2;
866 insn2 = insn >> 16;
868 IIIII = ((insn2 & 0xf800) >> 11);
869 iiiii = (insn & 0x001f);
871 ret = (IIIII << 5) | iiiii;
873 if (invalid != 0)
874 *invalid = 0;
876 return ret;
879 static unsigned long
880 insert_SRSEL1 (unsigned long insn, unsigned long value, const char ** errmsg)
882 unsigned long imm10, ret;
883 unsigned long sr,selid;
885 if (value > 0x3ff)
886 * errmsg = _(sr_selid_out_of_range);
888 imm10 = value;
889 selid = (imm10 & 0x3e0) >> 5;
890 sr = imm10 & 0x1f;
892 ret = insn | selid << 27 | sr;
894 return ret;
897 static unsigned long
898 extract_SRSEL1 (unsigned long insn, int * invalid)
900 unsigned long ret;
901 unsigned long sr, selid;
902 unsigned long insn2;
904 insn2 = insn >> 16;
906 selid = ((insn2 & 0xf800) >> 11);
907 sr = (insn & 0x001f);
909 ret = (selid << 5) | sr;
911 if (invalid != 0)
912 *invalid = 0;
914 return ret;
917 static unsigned long
918 insert_SRSEL2 (unsigned long insn, unsigned long value, const char ** errmsg)
920 unsigned long imm10, ret;
921 unsigned long sr, selid;
923 if (value > 0x3ff)
924 * errmsg = _(sr_selid_out_of_range);
926 imm10 = value;
927 selid = (imm10 & 0x3e0) >> 5;
928 sr = imm10 & 0x1f;
930 ret = insn | selid << 27 | sr << 11;
932 return ret;
935 static unsigned long
936 extract_SRSEL2 (unsigned long insn, int * invalid)
938 unsigned long ret;
939 unsigned long sr, selid;
940 unsigned long insn2;
942 insn2 = insn >> 16;
944 selid = ((insn2 & 0xf800) >> 11);
945 sr = ((insn & 0xf800) >> 11);
947 ret = (selid << 5) | sr;
949 if (invalid != 0)
950 *invalid = 0;
952 return ret;
955 /* Warning: code in gas/config/tc-v850.c examines the contents of this array.
956 If you change any of the values here, be sure to look for side effects in
957 that code. */
958 const struct v850_operand v850_operands[] =
960 #define UNUSED 0
961 { 0, 0, NULL, NULL, 0, BFD_RELOC_NONE },
963 /* The R1 field in a format 1, 6, 7, 9, C insn. */
964 #define R1 (UNUSED + 1)
965 { 5, 0, NULL, NULL, V850_OPERAND_REG, BFD_RELOC_NONE },
967 /* As above, but register 0 is not allowed. */
968 #define R1_NOTR0 (R1 + 1)
969 { 5, 0, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0, BFD_RELOC_NONE },
971 /* Even register is allowed. */
972 #define R1_EVEN (R1_NOTR0 + 1)
973 { 4, 1, NULL, NULL, V850_OPERAND_REG | V850_REG_EVEN, BFD_RELOC_NONE },
975 /* Bang (bit reverse). */
976 #define R1_BANG (R1_EVEN + 1)
977 { 5, 0, NULL, NULL, V850_OPERAND_REG | V850_OPERAND_BANG, BFD_RELOC_NONE },
979 /* Percent (modulo). */
980 #define R1_PERCENT (R1_BANG + 1)
981 { 5, 0, NULL, NULL, V850_OPERAND_REG | V850_OPERAND_PERCENT, BFD_RELOC_NONE },
983 /* The R2 field in a format 1, 2, 4, 5, 6, 7, 9, C insn. */
984 #define R2 (R1_PERCENT + 1)
985 { 5, 11, NULL, NULL, V850_OPERAND_REG, BFD_RELOC_NONE },
987 /* As above, but register 0 is not allowed. */
988 #define R2_NOTR0 (R2 + 1)
989 { 5, 11, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0, BFD_RELOC_NONE },
991 /* Even register is allowed. */
992 #define R2_EVEN (R2_NOTR0 + 1)
993 { 4, 12, NULL, NULL, V850_OPERAND_REG | V850_REG_EVEN, BFD_RELOC_NONE },
995 /* Reg2 in dispose instruction. */
996 #define R2_DISPOSE (R2_EVEN + 1)
997 { 5, 16, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0, BFD_RELOC_NONE },
999 /* The R3 field in a format 11, 12, C insn. */
1000 #define R3 (R2_DISPOSE + 1)
1001 { 5, 27, NULL, NULL, V850_OPERAND_REG, BFD_RELOC_NONE },
1003 /* As above, but register 0 is not allowed. */
1004 #define R3_NOTR0 (R3 + 1)
1005 { 5, 27, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0, BFD_RELOC_NONE },
1007 /* As above, but odd number registers are not allowed. */
1008 #define R3_EVEN (R3_NOTR0 + 1)
1009 { 4, 28, NULL, NULL, V850_OPERAND_REG | V850_REG_EVEN, BFD_RELOC_NONE },
1011 /* As above, but register 0 is not allowed. */
1012 #define R3_EVEN_NOTR0 (R3_EVEN + 1)
1013 { 4, 28, NULL, NULL, V850_OPERAND_REG | V850_REG_EVEN | V850_NOT_R0, BFD_RELOC_NONE },
1015 /* Forth register in FPU Instruction. */
1016 #define R4 (R3_EVEN_NOTR0 + 1)
1017 { 5, 0, insert_r4, extract_r4, V850_OPERAND_REG, BFD_RELOC_NONE },
1019 /* As above, but odd number registers are not allowed. */
1020 #define R4_EVEN (R4 + 1)
1021 { 4, 17, NULL, NULL, V850_OPERAND_REG | V850_REG_EVEN, BFD_RELOC_NONE },
1023 /* Stack pointer in prepare instruction. */
1024 #define SP (R4_EVEN + 1)
1025 { 2, 0, insert_spe, extract_spe, V850_OPERAND_REG, BFD_RELOC_NONE },
1027 /* EP Register. */
1028 #define EP (SP + 1)
1029 { 0, 0, NULL, NULL, V850_OPERAND_EP, BFD_RELOC_NONE },
1031 /* A list of registers in a prepare/dispose instruction. */
1032 #define LIST12 (EP + 1)
1033 { -1, 0xffe00001, NULL, NULL, V850E_OPERAND_REG_LIST, BFD_RELOC_NONE },
1035 /* System register operands. */
1036 #define OLDSR1 (LIST12 + 1)
1037 { 5, 0, NULL, NULL, V850_OPERAND_SRG, BFD_RELOC_NONE },
1039 #define SR1 (OLDSR1 + 1)
1040 { 0, 0, insert_SRSEL1, extract_SRSEL1, V850_OPERAND_SRG, BFD_RELOC_NONE },
1042 /* The R2 field as a system register. */
1043 #define OLDSR2 (SR1 + 1)
1044 { 5, 11, NULL, NULL, V850_OPERAND_SRG, BFD_RELOC_NONE },
1046 #define SR2 (OLDSR2 + 1)
1047 { 0, 0, insert_SRSEL2, extract_SRSEL2, V850_OPERAND_SRG, BFD_RELOC_NONE },
1049 /* FPU CC bit position. */
1050 #define FFF (SR2 + 1)
1051 { 3, 17, NULL, NULL, 0, BFD_RELOC_NONE },
1053 /* The 4 bit condition code in a setf instruction. */
1054 #define CCCC (FFF + 1)
1055 { 4, 0, NULL, NULL, V850_OPERAND_CC, BFD_RELOC_NONE },
1057 /* Condition code in adf,sdf. */
1058 #define CCCC_NOTSA (CCCC + 1)
1059 { 4, 17, NULL, NULL, V850_OPERAND_CC|V850_NOT_SA, BFD_RELOC_NONE },
1061 /* Condition code in conditional moves. */
1062 #define MOVCC (CCCC_NOTSA + 1)
1063 { 4, 17, NULL, NULL, V850_OPERAND_CC, BFD_RELOC_NONE },
1065 /* Condition code in FPU. */
1066 #define FLOAT_CCCC (MOVCC + 1)
1067 { 4, 27, NULL, NULL, V850_OPERAND_FLOAT_CC, BFD_RELOC_NONE },
1069 /* The 1 bit immediate field in format C insn. */
1070 #define VI1 (FLOAT_CCCC + 1)
1071 { 1, 3, NULL, NULL, 0, BFD_RELOC_NONE },
1073 /* The 1 bit immediate field in format C insn. */
1074 #define VC1 (VI1 + 1)
1075 { 1, 0, NULL, NULL, 0, BFD_RELOC_NONE },
1077 /* The 2 bit immediate field in format C insn. */
1078 #define DI2 (VC1 + 1)
1079 { 2, 17, NULL, NULL, 0, BFD_RELOC_NONE },
1081 /* The 2 bit immediate field in format C insn. */
1082 #define VI2 (DI2 + 1)
1083 { 2, 0, NULL, NULL, 0, BFD_RELOC_NONE },
1085 /* The 2 bit immediate field in format C - DUP insn. */
1086 #define VI2DUP (VI2 + 1)
1087 { 2, 2, NULL, NULL, 0, BFD_RELOC_NONE },
1089 /* The 3 bit immediate field in format 8 insn. */
1090 #define B3 (VI2DUP + 1)
1091 { 3, 11, NULL, NULL, 0, BFD_RELOC_NONE },
1093 /* The 3 bit immediate field in format C insn. */
1094 #define DI3 (B3 + 1)
1095 { 3, 17, NULL, NULL, 0, BFD_RELOC_NONE },
1097 /* The 3 bit immediate field in format C insn. */
1098 #define I3U (DI3 + 1)
1099 { 3, 0, NULL, NULL, 0, BFD_RELOC_NONE },
1101 /* The 4 bit immediate field in format C insn. */
1102 #define I4U (I3U + 1)
1103 { 4, 0, NULL, NULL, 0, BFD_RELOC_NONE },
1105 /* The 4 bit immediate field in fetrap. */
1106 #define I4U_NOTIMM0 (I4U + 1)
1107 { 4, 11, NULL, NULL, V850_NOT_IMM0, BFD_RELOC_NONE },
1109 /* The unsigned disp4 field in a sld.bu. */
1110 #define D4U (I4U_NOTIMM0 + 1)
1111 { 4, 0, NULL, NULL, V850_OPERAND_DISP, BFD_RELOC_V850_TDA_4_4_OFFSET },
1113 /* The imm5 field in a format 2 insn. */
1114 #define I5 (D4U + 1)
1115 { 5, 0, NULL, NULL, V850_OPERAND_SIGNED, BFD_RELOC_NONE },
1117 /* The imm5 field in a format 11 insn. */
1118 #define I5DIV1 (I5 + 1)
1119 { 5, 0, insert_i5div1, extract_i5div1, 0, BFD_RELOC_NONE },
1121 #define I5DIV2 (I5DIV1 + 1)
1122 { 5, 0, insert_i5div2, extract_i5div2, 0, BFD_RELOC_NONE },
1124 #define I5DIV3 (I5DIV2 + 1)
1125 { 5, 0, insert_i5div3, extract_i5div3, 0, BFD_RELOC_NONE },
1127 /* The unsigned imm5 field in a format 2 insn. */
1128 #define I5U (I5DIV3 + 1)
1129 { 5, 0, NULL, NULL, 0, BFD_RELOC_NONE },
1131 /* The imm5 field in a prepare/dispose instruction. */
1132 #define IMM5 (I5U + 1)
1133 { 5, 1, NULL, NULL, 0, BFD_RELOC_NONE },
1135 /* The unsigned disp5 field in a sld.hu. */
1136 #define D5_4U (IMM5 + 1)
1137 { 5, 0, insert_d5_4, extract_d5_4, V850_OPERAND_DISP, BFD_RELOC_V850_TDA_4_5_OFFSET },
1139 /* The IMM6 field in a callt instruction. */
1140 #define IMM6 (D5_4U + 1)
1141 { 6, 0, NULL, NULL, 0, BFD_RELOC_V850_CALLT_6_7_OFFSET },
1143 /* The signed disp7 field in a format 4 insn. */
1144 #define D7U (IMM6 + 1)
1145 { 7, 0, NULL, NULL, V850_OPERAND_DISP, BFD_RELOC_V850_TDA_7_7_OFFSET },
1147 /* The unsigned DISP8 field in a format 4 insn. */
1148 #define D8_7U (D7U + 1)
1149 { 8, 0, insert_d8_7, extract_d8_7, V850_OPERAND_DISP, BFD_RELOC_V850_TDA_7_8_OFFSET },
1151 /* The unsigned DISP8 field in a format 4 insn. */
1152 #define D8_6U (D8_7U + 1)
1153 { 8, 0, insert_d8_6, extract_d8_6, V850_OPERAND_DISP, BFD_RELOC_V850_TDA_6_8_OFFSET },
1155 /* The unsigned DISP8 field in a format 4 insn. */
1156 #define V8 (D8_6U + 1)
1157 { 8, 0, insert_v8, extract_v8, 0, BFD_RELOC_NONE },
1159 /* The imm9 field in a multiply word. */
1160 #define I9 (V8 + 1)
1161 { 9, 0, insert_i9, extract_i9, V850_OPERAND_SIGNED, BFD_RELOC_NONE },
1163 /* The unsigned imm9 field in a multiply word. */
1164 #define U9 (I9 + 1)
1165 { 9, 0, insert_u9, extract_u9, 0, BFD_RELOC_NONE },
1167 /* The DISP9 field in a format 3 insn. */
1168 #define D9 (U9 + 1)
1169 { 9, 0, insert_d9, extract_d9, V850_OPERAND_SIGNED | V850_OPERAND_DISP | V850_PCREL, BFD_RELOC_V850_9_PCREL },
1171 /* The DISP9 field in a format 3 insn, relaxable. */
1172 #define D9_RELAX (D9 + 1)
1173 { 9, 0, insert_d9, extract_d9, V850_OPERAND_RELAX | V850_OPERAND_SIGNED | V850_OPERAND_DISP | V850_PCREL, BFD_RELOC_V850_9_PCREL },
1175 /* The imm16 field in a format 6 insn. */
1176 #define I16 (D9_RELAX + 1)
1177 { 16, 16, NULL, NULL, V850_OPERAND_SIGNED, BFD_RELOC_16 },
1179 /* The signed 16 bit immediate following a prepare instruction. */
1180 #define IMM16LO (I16 + 1)
1181 { 16, 32, NULL, NULL, V850E_IMMEDIATE16 | V850_OPERAND_SIGNED, BFD_RELOC_LO16 },
1183 /* The hi 16 bit immediate following a 32 bit instruction. */
1184 #define IMM16HI (IMM16LO + 1)
1185 { 16, 16, NULL, NULL, V850E_IMMEDIATE16HI, BFD_RELOC_HI16 },
1187 /* The unsigned imm16 in a format 6 insn. */
1188 #define I16U (IMM16HI + 1)
1189 { 16, 16, NULL, NULL, 0, BFD_RELOC_16 },
1191 /* The disp16 field in a format 8 insn. */
1192 #define D16 (I16U + 1)
1193 { 16, 16, NULL, NULL, V850_OPERAND_SIGNED | V850_OPERAND_DISP, BFD_RELOC_V850_LO16_SPLIT_OFFSET },
1195 /* The disp16 field in an format 7 unsigned byte load insn. */
1196 #define D16_16 (D16 + 1)
1197 { 16, 0, insert_d16_16, extract_d16_16, V850_OPERAND_SIGNED | V850_OPERAND_DISP, BFD_RELOC_V850_16_SPLIT_OFFSET },
1199 /* The disp16 field in a format 6 insn. */
1200 #define D16_15 (D16_16 + 1)
1201 { 16, 0, insert_d16_15, extract_d16_15, V850_OPERAND_SIGNED | V850_OPERAND_DISP , BFD_RELOC_V850_16_S1 },
1203 /* The unsigned DISP16 field in a format 7 insn. */
1204 #define D16_LOOP (D16_15 + 1)
1205 { 16, 0, insert_u16_loop, extract_u16_loop, V850_OPERAND_RELAX | V850_OPERAND_DISP | V850_PCREL | V850_INVERSE_PCREL, BFD_RELOC_V850_16_PCREL },
1207 /* The DISP17 field in a format 7 insn. */
1208 #define D17_16 (D16_LOOP + 1)
1209 { 17, 0, insert_d17_16, extract_d17_16, V850_OPERAND_SIGNED | V850_OPERAND_DISP | V850_PCREL, BFD_RELOC_V850_17_PCREL },
1211 /* The DISP22 field in a format 4 insn, relaxable.
1212 This _must_ follow D9_RELAX; the assembler assumes that the longer
1213 version immediately follows the shorter version for relaxing. */
1214 #define D22 (D17_16 + 1)
1215 { 22, 0, insert_d22, extract_d22, V850_OPERAND_SIGNED | V850_OPERAND_DISP | V850_PCREL, BFD_RELOC_V850_22_PCREL },
1217 #define D23 (D22 + 1)
1218 { 23, 0, insert_d23, extract_d23, V850E_IMMEDIATE23 | V850_OPERAND_SIGNED | V850_OPERAND_DISP, BFD_RELOC_V850_23 },
1220 #define D23_ALIGN1 (D23 + 1)
1221 { 23, 0, insert_d23_align1, extract_d23, V850E_IMMEDIATE23 | V850_OPERAND_SIGNED | V850_OPERAND_DISP, BFD_RELOC_V850_23 },
1223 /* The 32 bit immediate following a 32 bit instruction. */
1224 #define IMM32 (D23_ALIGN1 + 1)
1225 { 32, 32, NULL, NULL, V850E_IMMEDIATE32, BFD_RELOC_32 },
1227 #define D32_31 (IMM32 + 1)
1228 { 32, 32, NULL, NULL, V850E_IMMEDIATE32 | V850_OPERAND_SIGNED | V850_OPERAND_DISP, BFD_RELOC_V850_32_ABS },
1230 #define D32_31_PCREL (D32_31 + 1)
1231 { 32, 32, NULL, NULL, V850E_IMMEDIATE32 | V850_OPERAND_SIGNED | V850_OPERAND_DISP | V850_PCREL, BFD_RELOC_V850_32_PCREL },
1233 #define POS_U (D32_31_PCREL + 1)
1234 { 0, 0, insert_POS, extract_POS_U, 0, BFD_RELOC_NONE },
1236 #define POS_M (POS_U + 1)
1237 { 0, 0, insert_POS, extract_POS_L, 0, BFD_RELOC_NONE },
1239 #define POS_L (POS_M + 1)
1240 { 0, 0, insert_POS, extract_POS_L, 0, BFD_RELOC_NONE },
1242 #define WIDTH_U (POS_L + 1)
1243 { 0, 0, insert_WIDTH, extract_WIDTH_U, 0, BFD_RELOC_NONE },
1245 #define WIDTH_M (WIDTH_U + 1)
1246 { 0, 0, insert_WIDTH, extract_WIDTH_M, 0, BFD_RELOC_NONE },
1248 #define WIDTH_L (WIDTH_M + 1)
1249 { 0, 0, insert_WIDTH, extract_WIDTH_L, 0, BFD_RELOC_NONE },
1251 #define SELID (WIDTH_L + 1)
1252 { 5, 27, insert_SELID, extract_SELID, 0, BFD_RELOC_NONE },
1254 #define RIE_IMM5 (SELID + 1)
1255 { 5, 11, NULL, NULL, 0, BFD_RELOC_NONE },
1257 #define RIE_IMM4 (RIE_IMM5 + 1)
1258 { 4, 0, NULL, NULL, 0, BFD_RELOC_NONE },
1260 #define VECTOR8 (RIE_IMM4 + 1)
1261 { 0, 0, insert_VECTOR8, extract_VECTOR8, 0, BFD_RELOC_NONE },
1263 #define VECTOR5 (VECTOR8 + 1)
1264 { 0, 0, insert_VECTOR5, extract_VECTOR5, 0, BFD_RELOC_NONE },
1266 #define VR1 (VECTOR5 + 1)
1267 { 5, 0, NULL, NULL, V850_OPERAND_VREG, BFD_RELOC_NONE },
1269 #define VR2 (VR1 + 1)
1270 { 5, 11, NULL, NULL, V850_OPERAND_VREG, BFD_RELOC_NONE },
1272 #define CACHEOP (VR2 + 1)
1273 { 0, 0, insert_CACHEOP, extract_CACHEOP, V850_OPERAND_CACHEOP, BFD_RELOC_NONE },
1275 #define PREFOP (CACHEOP + 1)
1276 { 0, 0, insert_PREFOP, extract_PREFOP, V850_OPERAND_PREFOP, BFD_RELOC_NONE },
1278 #define IMM10U (PREFOP + 1)
1279 { 0, 0, insert_IMM10U, extract_IMM10U, 0, BFD_RELOC_NONE },
1283 /* Reg - Reg instruction format (Format I). */
1284 #define IF1 {R1, R2}
1286 /* Imm - Reg instruction format (Format II). */
1287 #define IF2 {I5, R2}
1289 /* Conditional branch instruction format (Format III). */
1290 #define IF3 {D9_RELAX}
1292 /* 3 operand instruction (Format VI). */
1293 #define IF6 {I16, R1, R2}
1295 /* 3 operand instruction (Format VI). */
1296 #define IF6U {I16U, R1, R2}
1298 /* Conditional branch instruction format (Format VII). */
1299 #define IF7 {D17_16}
1302 /* The opcode table.
1304 The format of the opcode table is:
1306 NAME OPCODE MASK { OPERANDS } MEMOP PROCESSOR
1308 NAME is the name of the instruction.
1309 OPCODE is the instruction opcode.
1310 MASK is the opcode mask; this is used to tell the disassembler
1311 which bits in the actual opcode must match OPCODE.
1312 OPERANDS is the list of operands.
1313 MEMOP specifies which operand (if any) is a memory operand.
1314 PROCESSORS specifies which CPU(s) support the opcode.
1316 The disassembler reads the table in order and prints the first
1317 instruction which matches, so this table is sorted to put more
1318 specific instructions before more general instructions. It is also
1319 sorted by major opcode.
1321 The table is also sorted by name. This is used by the assembler.
1322 When parsing an instruction the assembler finds the first occurance
1323 of the name of the instruciton in this table and then attempts to
1324 match the instruction's arguments with description of the operands
1325 associated with the entry it has just found in this table. If the
1326 match fails the assembler looks at the next entry in this table.
1327 If that entry has the same name as the previous entry, then it
1328 tries to match the instruction against that entry and so on. This
1329 is how the assembler copes with multiple, different formats of the
1330 same instruction. */
1332 const struct v850_opcode v850_opcodes[] =
1334 /* Standard instructions. */
1335 { "add", OP (0x0e), OP_MASK, IF1, 0, PROCESSOR_ALL },
1336 { "add", OP (0x12), OP_MASK, IF2, 0, PROCESSOR_ALL },
1338 { "addi", OP (0x30), OP_MASK, IF6, 0, PROCESSOR_ALL },
1340 { "adf", two (0x07e0, 0x03a0), two (0x07e0, 0x07e1), {CCCC_NOTSA, R1, R2, R3}, 0, PROCESSOR_V850E2_UP },
1342 { "and", OP (0x0a), OP_MASK, IF1, 0, PROCESSOR_ALL },
1344 { "andi", OP (0x36), OP_MASK, IF6U, 0, PROCESSOR_ALL },
1346 /* Signed integer. */
1347 { "bge", BOP (0xe), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1348 { "bgt", BOP (0xf), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1349 { "ble", BOP (0x7), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1350 { "blt", BOP (0x6), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1351 /* Unsigned integer. */
1352 { "bh", BOP (0xb), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1353 { "bl", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1354 { "bnh", BOP (0x3), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1355 { "bnl", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1356 /* Common. */
1357 { "be", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1358 { "bne", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1359 /* Others. */
1360 { "bc", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1361 { "bf", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1362 { "bn", BOP (0x4), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1363 { "bnc", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1364 { "bnv", BOP (0x8), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1365 { "bnz", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1366 { "bp", BOP (0xc), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1367 { "br", BOP (0x5), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1368 { "bsa", BOP (0xd), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1369 { "bt", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1370 { "bv", BOP (0x0), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1371 { "bz", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1373 /* Signed integer. */
1374 { "bge", two (0x07ee, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
1375 { "bgt", two (0x07ef, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
1376 { "ble", two (0x07e7, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
1377 { "blt", two (0x07e6, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
1378 /* Unsigned integer. */
1379 { "bh", two (0x07eb, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
1380 { "bl", two (0x07e1, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
1381 { "bnh", two (0x07e3, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
1382 { "bnl", two (0x07e9, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
1383 /* Common. */
1384 { "be", two (0x07e2, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
1385 { "bne", two (0x07ea, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
1386 /* Others. */
1387 { "bc", two (0x07e1, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
1388 { "bf", two (0x07ea, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
1389 { "bn", two (0x07e4, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
1390 { "bnc", two (0x07e9, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
1391 { "bnv", two (0x07e8, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
1392 { "bnz", two (0x07ea, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
1393 { "bp", two (0x07ec, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
1394 { "br", two (0x07e5, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
1395 { "bsa", two (0x07ed, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
1396 { "bt", two (0x07e2, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
1397 { "bv", two (0x07e0, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
1398 { "bz", two (0x07e2, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
1399 /* Bcond disp17 Gas local alias(not defined in spec). */
1401 /* Signed integer. */
1402 { "bge17", two (0x07ee, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1403 { "bgt17", two (0x07ef, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1404 { "ble17", two (0x07e7, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1405 { "blt17", two (0x07e6, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1406 /* Unsigned integer. */
1407 { "bh17", two (0x07eb, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1408 { "bl17", two (0x07e1, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1409 { "bnh17", two (0x07e3, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1410 { "bnl17", two (0x07e9, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1411 /* Common. */
1412 { "be17", two (0x07e2, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1413 { "bne17", two (0x07ea, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1414 /* Others. */
1415 { "bc17", two (0x07e1, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1416 { "bf17", two (0x07ea, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1417 { "bn17", two (0x07e4, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1418 { "bnc17", two (0x07e9, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1419 { "bnv17", two (0x07e8, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1420 { "bnz17", two (0x07ea, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1421 { "bp17", two (0x07ec, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1422 { "br17", two (0x07e5, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1423 { "bsa17", two (0x07ed, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1424 { "bt17", two (0x07e2, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1425 { "bv17", two (0x07e0, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1426 { "bz17", two (0x07e2, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1428 { "bsh", two (0x07e0, 0x0342), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_NOT_V850 },
1430 { "bsw", two (0x07e0, 0x0340), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_NOT_V850 },
1432 /* v850e3v5 bitfield instructions. */
1433 { "bins", two (0x07e0, 0x0090), two (0x07e0, 0x07f1), {R1, POS_U, WIDTH_U, R2}, 0, PROCESSOR_V850E3V5_UP },
1434 { "bins", two (0x07e0, 0x00b0), two (0x07e0, 0x07f1), {R1, POS_M, WIDTH_M, R2}, 0, PROCESSOR_V850E3V5_UP },
1435 { "bins", two (0x07e0, 0x00d0), two (0x07e0, 0x07f1), {R1, POS_L, WIDTH_L, R2}, 0, PROCESSOR_V850E3V5_UP },
1436 /* Gas local alias(not defined in spec). */
1437 { "binsu",two (0x07e0, 0x0090), two (0x07e0, 0x07f1), {R1, POS_U, WIDTH_U, R2}, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1438 { "binsm",two (0x07e0, 0x00b0), two (0x07e0, 0x07f1), {R1, POS_M, WIDTH_M, R2}, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1439 { "binsl",two (0x07e0, 0x00d0), two (0x07e0, 0x07f1), {R1, POS_L, WIDTH_L, R2}, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1441 { "cache", two (0xe7e0, 0x0160), two (0xe7e0, 0x07ff), {CACHEOP, R1}, 2, PROCESSOR_V850E3V5_UP },
1443 { "callt", one (0x0200), one (0xffc0), {IMM6}, 0, PROCESSOR_NOT_V850 },
1445 { "caxi", two (0x07e0, 0x00ee), two (0x07e0, 0x07ff), {R1, R2, R3}, 1, PROCESSOR_V850E2_UP },
1447 { "clr1", two (0x87c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 3, PROCESSOR_ALL },
1448 { "clr1", two (0x07e0, 0x00e4), two (0x07e0, 0xffff), {R2, R1}, 3, PROCESSOR_NOT_V850 },
1450 { "cmov", two (0x07e0, 0x0320), two (0x07e0, 0x07e1), {MOVCC, R1, R2, R3}, 0, PROCESSOR_NOT_V850 },
1451 { "cmov", two (0x07e0, 0x0300), two (0x07e0, 0x07e1), {MOVCC, I5, R2, R3}, 0, PROCESSOR_NOT_V850 },
1453 { "cmp", OP (0x0f), OP_MASK, IF1, 0, PROCESSOR_ALL },
1454 { "cmp", OP (0x13), OP_MASK, IF2, 0, PROCESSOR_ALL },
1456 { "ctret", two (0x07e0, 0x0144), two (0xffff, 0xffff), {0}, 0, PROCESSOR_NOT_V850 },
1458 { "dbcp", one (0xe840), one (0xffff), {0}, 0, PROCESSOR_V850E3V5_UP },
1460 { "dbhvtrap", one (0xe040), one (0xffff), {0}, 0, PROCESSOR_V850E3V5_UP },
1462 { "dbpush", two (0x5fe0, 0x0160), two (0xffe0, 0x07ff), {R1, R3}, 0, PROCESSOR_V850E3V5_UP },
1464 { "dbret", two (0x07e0, 0x0146), two (0xffff, 0xffff), {0}, 0, PROCESSOR_NOT_V850 },
1466 { "dbtag", two (0xcfe0, 0x0160), two (0xffe0, 0x07ff), {IMM10U}, 0, PROCESSOR_V850E3V5_UP },
1468 { "dbtrap", one (0xf840), one (0xffff), {0}, 0, PROCESSOR_NOT_V850 },
1470 { "di", two (0x07e0, 0x0160), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL },
1472 { "dispose", two (0x0640, 0x0000), two (0xffc0, 0x0000), {IMM5, LIST12, R2_DISPOSE},3, PROCESSOR_NOT_V850 },
1473 { "dispose", two (0x0640, 0x0000), two (0xffc0, 0x001f), {IMM5, LIST12}, 0, PROCESSOR_NOT_V850 },
1475 { "div", two (0x07e0, 0x02c0), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 },
1477 { "divh", two (0x07e0, 0x0280), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 },
1478 { "divh", OP (0x02), OP_MASK, {R1_NOTR0, R2_NOTR0}, 0, PROCESSOR_ALL },
1480 { "divhn", two (0x07e0, 0x0280), two (0x07e0, 0x07c3), {I5DIV1, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION },
1482 { "divhu", two (0x07e0, 0x0282), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 },
1484 { "divhun", two (0x07e0, 0x0282), two (0x07e0, 0x07c3), {I5DIV1, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION },
1485 { "divn", two (0x07e0, 0x02c0), two (0x07e0, 0x07c3), {I5DIV2, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION },
1487 { "divq", two (0x07e0, 0x02fc), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_UP },
1489 { "divqu", two (0x07e0, 0x02fe), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_UP },
1491 { "divu", two (0x07e0, 0x02c2), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 },
1493 { "divun", two (0x07e0, 0x02c2), two (0x07e0, 0x07c3), {I5DIV2, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION },
1495 { "dst", two (0x07e0, 0x0134), two (0xfffff, 0xffff), {0}, 0, PROCESSOR_V850E3V5_UP },
1497 { "ei", two (0x87e0, 0x0160), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL },
1499 { "eiret", two (0x07e0, 0x0148), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E2_UP },
1501 { "est", two (0x07e0, 0x0132), two (0xfffff, 0xffff), {0}, 0, PROCESSOR_V850E3V5_UP },
1503 { "feret", two (0x07e0, 0x014a), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E2_UP },
1505 { "fetrap", one (0x0040), one (0x87ff), {I4U_NOTIMM0}, 0, PROCESSOR_V850E2_UP },
1507 { "halt", two (0x07e0, 0x0120), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL },
1509 { "hsh", two (0x07e0, 0x0346), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2_UP },
1511 { "hsw", two (0x07e0, 0x0344), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_NOT_V850 },
1513 { "hvcall", two (0xd7e0, 0x4160), two (0xffe0, 0x41ff), {VECTOR8}, 0, PROCESSOR_V850E3V5_UP },
1514 { "hvtrap", two (0x07e0, 0x0110), two (0xffe0, 0xffff), {VECTOR5}, 0, PROCESSOR_V850E3V5_UP },
1516 { "jarl", two (0xc7e0, 0x0160), two (0xffe0, 0x07ff), {R1, R3_NOTR0}, 1, PROCESSOR_V850E3V5_UP},
1517 { "jarl", two (0x0780, 0x0000), two (0x07c0, 0x0001), {D22, R2_NOTR0}, 0, PROCESSOR_ALL},
1518 { "jarl", one (0x02e0), one (0xffe0), {D32_31_PCREL, R1_NOTR0}, 0, PROCESSOR_V850E2_UP },
1519 /* Gas local alias (not defined in spec). */
1520 { "jarlr", two (0xc7e0, 0x0160), two (0xffe0, 0x07ff), {R1, R3_NOTR0}, 1, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS},
1521 /* Gas local alias of jarl imm22 (not defined in spec). */
1522 { "jarl22", two (0x0780, 0x0000), two (0x07c0, 0x0001), {D22, R2_NOTR0}, 0, PROCESSOR_ALL | PROCESSOR_OPTION_ALIAS},
1523 /* Gas local alias of jarl imm32 (not defined in spec). */
1524 { "jarl32", one (0x02e0), one (0xffe0), {D32_31_PCREL, R1_NOTR0}, 0, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS },
1525 { "jarlw", one (0x02e0), one (0xffe0), {D32_31_PCREL, R1_NOTR0}, 0, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS },
1527 { "jmp", two (0x06e0, 0x0000), two (0xffe0, 0x0001), {D32_31, R1}, 2, PROCESSOR_V850E3V5_UP },
1528 { "jmp", one (0x06e0), one (0xffe0), {D32_31, R1}, 2, PROCESSOR_V850E2 | PROCESSOR_V850E2V3 },
1529 { "jmp", one (0x0060), one (0xffe0), {R1}, 1, PROCESSOR_ALL },
1530 /* Gas local alias of jmp disp22(not defined in spec). */
1531 { "jmp22", one (0x0060), one (0xffe0), {R1}, 1, PROCESSOR_ALL | PROCESSOR_OPTION_ALIAS },
1532 /* Gas local alias of jmp disp32(not defined in spec). */
1533 { "jmp32", one (0x06e0), one (0xffe0), {D32_31, R1}, 2, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS },
1534 { "jmpw", one (0x06e0), one (0xffe0), {D32_31, R1}, 2, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS },
1536 { "jr", two (0x0780, 0x0000), two (0xffc0, 0x0001), {D22}, 0, PROCESSOR_ALL },
1537 { "jr", one (0x02e0), one (0xffff), {D32_31_PCREL}, 0, PROCESSOR_V850E2_UP },
1538 /* Gas local alias of mov imm22(not defined in spec). */
1539 { "jr22", two (0x0780, 0x0000), two (0xffc0, 0x0001), {D22}, 0, PROCESSOR_ALL | PROCESSOR_OPTION_ALIAS },
1540 /* Gas local alias of mov imm32(not defined in spec). */
1541 { "jr32", one (0x02e0), one (0xffff), {D32_31_PCREL}, 0, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS },
1543 /* Alias of bcond (same as CA850). */
1544 { "jgt", BOP (0xf), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1545 { "jge", BOP (0xe), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1546 { "jlt", BOP (0x6), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1547 { "jle", BOP (0x7), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1548 /* Unsigned integer. */
1549 { "jh", BOP (0xb), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1550 { "jnh", BOP (0x3), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1551 { "jl", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1552 { "jnl", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1553 /* Common. */
1554 { "je", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1555 { "jne", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1556 /* Others. */
1557 { "jv", BOP (0x0), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1558 { "jnv", BOP (0x8), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1559 { "jn", BOP (0x4), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1560 { "jp", BOP (0xc), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1561 { "jc", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1562 { "jnc", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1563 { "jz", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1564 { "jnz", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1565 { "jbr", BOP (0x5), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1568 { "ldacc", two (0x07e0, 0x0bc4), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_EXTENSION },
1570 { "ld.b", two (0x0700, 0x0000), two (0x07e0, 0x0000), {D16, R1, R2}, 2, PROCESSOR_ALL },
1571 { "ld.b", two (0x0780, 0x0005), two (0xffe0, 0x000f), {D23, R1, R3}, 2, PROCESSOR_V850E2_UP },
1572 { "ld.b23", two (0x0780, 0x0005), two (0x07e0, 0x000f), {D23, R1, R3}, 2, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS },
1574 { "ld.bu", two (0x0780, 0x0001), two (0x07c0, 0x0001), {D16_16, R1, R2_NOTR0}, 2, PROCESSOR_NOT_V850 },
1575 { "ld.bu", two (0x07a0, 0x0005), two (0xffe0, 0x000f), {D23, R1, R3}, 2, PROCESSOR_V850E2_UP },
1576 { "ld.bu23", two (0x07a0, 0x0005), two (0x07e0, 0x000f), {D23, R1, R3}, 2, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS },
1578 { "ld.dw", two (0x07a0, 0x0009), two (0xffe0, 0x001f), {D23_ALIGN1, R1, R3_EVEN}, 2, PROCESSOR_V850E3V5_UP },
1579 { "ld.dw23", two (0x07a0, 0x0009), two (0xffe0, 0x001f), {D23_ALIGN1, R1, R3_EVEN}, 2, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1581 { "ld.h", two (0x0720, 0x0000), two (0x07e0, 0x0001), {D16_15, R1, R2}, 2, PROCESSOR_ALL },
1582 { "ld.h", two (0x0780, 0x0007), two (0x07e0, 0x000f), {D23_ALIGN1, R1, R3}, 2, PROCESSOR_V850E2_UP },
1583 { "ld.h23", two (0x0780, 0x0007), two (0x07e0, 0x000f), {D23_ALIGN1, R1, R3}, 2, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS },
1585 { "ld.hu", two (0x07e0, 0x0001), two (0x07e0, 0x0001), {D16_15, R1, R2_NOTR0}, 2, PROCESSOR_NOT_V850 },
1586 { "ld.hu", two (0x07a0, 0x0007), two (0x07e0, 0x000f), {D23_ALIGN1, R1, R3}, 2, PROCESSOR_V850E2_UP },
1587 { "ld.hu23", two (0x07a0, 0x0007), two (0x07e0, 0x000f), {D23_ALIGN1, R1, R3}, 2, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS },
1589 { "ld.w", two (0x0720, 0x0001), two (0x07e0, 0x0001), {D16_15, R1, R2}, 2, PROCESSOR_ALL },
1590 { "ld.w", two (0x0780, 0x0009), two (0xffe0, 0x001f), {D23_ALIGN1, R1, R3}, 2, PROCESSOR_V850E2_UP },
1591 { "ld.w23", two (0x0780, 0x0009), two (0x07e0, 0x001f), {D23_ALIGN1, R1, R3}, 2, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS },
1593 { "ldl.w", two (0x07e0, 0x0378), two (0xffe0, 0x07ff), {R1, R3}, 1, PROCESSOR_V850E3V5_UP },
1595 { "ldsr", two (0x07e0, 0x0020), two (0x07e0, 0x07ff), {R1, SR2, SELID}, 0, PROCESSOR_V850E3V5_UP },
1596 { "ldsr", two (0x07e0, 0x0020), two (0x07e0, 0x07ff), {R1, SR2}, 0, PROCESSOR_V850E3V5_UP },
1597 { "ldsr", two (0x07e0, 0x0020), two (0x07e0, 0x07ff), {R1, OLDSR2}, 0, (PROCESSOR_ALL & (~ PROCESSOR_V850E3V5_UP)) },
1599 { "ldtc.gr", two (0x07e0, 0x0032), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_V850E3V5_UP },
1600 { "ldtc.sr", two (0x07e0, 0x0030), two (0x07e0, 0x07ff), {R1, SR2, SELID}, 0, PROCESSOR_V850E3V5_UP },
1601 { "ldtc.sr", two (0x07e0, 0x0030), two (0x07e0, 0x07ff), {R1, SR2}, 0, PROCESSOR_V850E3V5_UP },
1603 { "ldtc.vr", two (0x07e0, 0x0832), two (0x07e0, 0xffff), {R1, VR2}, 0, PROCESSOR_V850E3V5_UP },
1604 { "ldtc.pc", two (0x07e0, 0xf832), two (0x07e0, 0xffff), {R1}, 0, PROCESSOR_V850E3V5_UP },
1606 { "ldvc.sr", two (0x07e0, 0x0034), two (0x07e0, 0x07ff), {R1, SR2, SELID}, 0, PROCESSOR_V850E3V5_UP },
1607 { "ldvc.sr", two (0x07e0, 0x0034), two (0x07e0, 0x07ff), {R1, SR2}, 0, PROCESSOR_V850E3V5_UP },
1609 { "loop", two (0x06e0, 0x0001), two (0xffe0, 0x0001), {R1, D16_LOOP}, 0, PROCESSOR_V850E3V5_UP },
1611 { "macacc", two (0x07e0, 0x0bc0), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_EXTENSION },
1613 { "mac", two (0x07e0, 0x03c0), two (0x07e0, 0x0fe1), {R1, R2, R3_EVEN, R4_EVEN}, 0, PROCESSOR_V850E2_UP },
1615 { "macu", two (0x07e0, 0x03e0), two (0x07e0, 0x0fe1), {R1, R2, R3_EVEN, R4_EVEN}, 0, PROCESSOR_V850E2_UP },
1617 { "macuacc", two (0x07e0, 0x0bc2), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_EXTENSION },
1619 { "mov", OP (0x00), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL },
1620 { "mov", OP (0x10), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL },
1621 { "mov", one (0x0620), one (0xffe0), {IMM32, R1}, 0, PROCESSOR_NOT_V850 },
1622 /* Gas local alias of mov imm32(not defined in spec). */
1623 { "movl", one (0x0620), one (0xffe0), {IMM32, R1}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_ALIAS },
1625 { "movea", OP (0x31), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL },
1627 { "movhi", OP (0x32), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL },
1629 { "mul", two (0x07e0, 0x0220), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 },
1630 { "mul", two (0x07e0, 0x0240), two (0x07e0, 0x07c3), {I9, R2, R3}, 0, PROCESSOR_NOT_V850 },
1632 { "mulh", OP (0x17), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL },
1633 { "mulh", OP (0x07), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL },
1635 { "mulhi", OP (0x37), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL },
1637 { "mulu", two (0x07e0, 0x0222), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 },
1638 { "mulu", two (0x07e0, 0x0242), two (0x07e0, 0x07c3), {U9, R2, R3}, 0, PROCESSOR_NOT_V850 },
1640 { "nop", one (0x00), one (0xffff), {0}, 0, PROCESSOR_ALL },
1642 { "not", OP (0x01), OP_MASK, IF1, 0, PROCESSOR_ALL },
1644 { "not1", two (0x47c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 3, PROCESSOR_ALL },
1645 { "not1", two (0x07e0, 0x00e2), two (0x07e0, 0xffff), {R2, R1}, 3, PROCESSOR_NOT_V850 },
1647 { "or", OP (0x08), OP_MASK, IF1, 0, PROCESSOR_ALL },
1649 { "ori", OP (0x34), OP_MASK, IF6U, 0, PROCESSOR_ALL },
1651 { "popsp", two (0x67e0, 0x0160), two (0xffe0, 0x07ff), {R1, R3}, 0, PROCESSOR_V850E3V5_UP },
1653 { "pref", two (0xdfe0, 0x0160), two (0xffe0, 0x07ff), {PREFOP, R1}, 2, PROCESSOR_V850E3V5_UP },
1655 { "prepare", two (0x0780, 0x0003), two (0xffc0, 0x001f), {LIST12, IMM5, SP}, 0, PROCESSOR_NOT_V850 },
1656 { "prepare", two (0x0780, 0x000b), two (0xffc0, 0x001f), {LIST12, IMM5, IMM16LO},0, PROCESSOR_NOT_V850 },
1657 { "prepare", two (0x0780, 0x0013), two (0xffc0, 0x001f), {LIST12, IMM5, IMM16HI},0, PROCESSOR_NOT_V850 },
1658 { "prepare", two (0x0780, 0x001b), two (0xffc0, 0x001f), {LIST12, IMM5, IMM32}, 0, PROCESSOR_NOT_V850 },
1659 { "prepare", two (0x0780, 0x0001), two (0xffc0, 0x001f), {LIST12, IMM5}, 0, PROCESSOR_NOT_V850 },
1661 { "pushsp", two (0x47e0, 0x0160), two (0xffe0, 0x07ff), {R1, R3}, 0, PROCESSOR_V850E3V5_UP },
1663 { "rotl", two (0x07e0, 0x00c6), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E3V5_UP },
1664 { "rotl", two (0x07e0, 0x00c4), two (0x07e0, 0x07ff), {I5U, R2, R3}, 0, PROCESSOR_V850E3V5_UP },
1666 { "reti", two (0x07e0, 0x0140), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL },
1668 { "sar", two (0x07e0, 0x00a2), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_UP },
1669 { "sar", OP (0x15), OP_MASK, {I5U, R2}, 0, PROCESSOR_ALL },
1670 { "sar", two (0x07e0, 0x00a0), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_ALL },
1672 { "sasf", two (0x07e0, 0x0200), two (0x07f0, 0xffff), {CCCC, R2}, 0, PROCESSOR_NOT_V850 },
1674 { "satadd", two (0x07e0, 0x03ba), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_UP },
1675 { "satadd", OP (0x11), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL },
1676 { "satadd", OP (0x06), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL },
1678 { "satsub", two (0x07e0, 0x039a), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_UP },
1679 { "satsub", OP (0x05), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL },
1681 { "satsubi", OP (0x33), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL },
1683 { "satsubr", OP (0x04), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL },
1685 { "sbf", two (0x07e0, 0x0380), two (0x07e0, 0x07e1), {CCCC_NOTSA, R1, R2, R3}, 0, PROCESSOR_V850E2_UP },
1687 { "sch0l", two (0x07e0, 0x0364), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2_UP },
1689 { "sch0r", two (0x07e0, 0x0360), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2_UP },
1691 { "sch1l", two (0x07e0, 0x0366), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2_UP },
1693 { "sch1r", two (0x07e0, 0x0362), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2_UP },
1695 { "sdivhn", two (0x07e0, 0x0180), two (0x07e0, 0x07c3), {I5DIV3, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION },
1696 { "sdivhun", two (0x07e0, 0x0182), two (0x07e0, 0x07c3), {I5DIV3, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION },
1697 { "sdivn", two (0x07e0, 0x01c0), two (0x07e0, 0x07c3), {I5DIV3, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION },
1698 { "sdivun", two (0x07e0, 0x01c2), two (0x07e0, 0x07c3), {I5DIV3, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION },
1700 { "set1", two (0x07c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 3, PROCESSOR_ALL },
1701 { "set1", two (0x07e0, 0x00e0), two (0x07e0, 0xffff), {R2, R1}, 3, PROCESSOR_NOT_V850 },
1703 { "setf", two (0x07e0, 0x0000), two (0x07f0, 0xffff), {CCCC, R2}, 0, PROCESSOR_ALL },
1705 { "shl", two (0x07e0, 0x00c2), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_UP },
1706 { "shl", OP (0x16), OP_MASK, {I5U, R2}, 0, PROCESSOR_ALL },
1707 { "shl", two (0x07e0, 0x00c0), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_ALL },
1709 { "shr", two (0x07e0, 0x0082), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_UP },
1710 { "shr", OP (0x14), OP_MASK, {I5U, R2}, 0, PROCESSOR_ALL },
1711 { "shr", two (0x07e0, 0x0080), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_ALL },
1713 { "sld.b", one (0x0300), one (0x0780), {D7U, EP, R2}, 2, PROCESSOR_ALL },
1715 { "sld.bu", one (0x0060), one (0x07f0), {D4U, EP, R2_NOTR0}, 2, PROCESSOR_NOT_V850 },
1717 { "sld.h", one (0x0400), one (0x0780), {D8_7U,EP, R2}, 2, PROCESSOR_ALL },
1719 { "sld.hu", one (0x0070), one (0x07f0), {D5_4U,EP, R2_NOTR0}, 2, PROCESSOR_NOT_V850 },
1721 { "sld.w", one (0x0500), one (0x0781), {D8_6U,EP, R2}, 2, PROCESSOR_ALL },
1723 { "snooze", two (0x0fe0, 0x0120), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E3V5_UP },
1725 { "sst.b", one (0x0380), one (0x0780), {R2, D7U, EP}, 3, PROCESSOR_ALL },
1727 { "sst.h", one (0x0480), one (0x0780), {R2, D8_7U,EP}, 3, PROCESSOR_ALL },
1729 { "sst.w", one (0x0501), one (0x0781), {R2, D8_6U,EP}, 3, PROCESSOR_ALL },
1731 { "stacch", two (0x07e0, 0x0bca), two (0x07ff, 0xffff), {R2}, 0, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_EXTENSION },
1732 { "staccl", two (0x07e0, 0x0bc8), two (0x07ff, 0xffff), {R2}, 0, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_EXTENSION },
1734 { "st.b", two (0x0740, 0x0000), two (0x07e0, 0x0000), {R2, D16, R1}, 3, PROCESSOR_ALL },
1735 { "st.b", two (0x0780, 0x000d), two (0x07e0, 0x000f), {R3, D23, R1}, 3, PROCESSOR_V850E2_UP },
1736 { "st.b23", two (0x0780, 0x000d), two (0x07e0, 0x000f), {R3, D23, R1}, 3, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS },
1738 { "st.dw", two (0x07a0, 0x000f), two (0xffe0, 0x001f), {R3_EVEN, D23_ALIGN1, R1}, 3, PROCESSOR_V850E3V5_UP },
1739 { "st.dw23", two (0x07a0, 0x000f), two (0xffe0, 0x001f), {R3_EVEN, D23_ALIGN1, R1}, 3, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1741 { "st.h", two (0x0760, 0x0000), two (0x07e0, 0x0001), {R2, D16_15, R1}, 3, PROCESSOR_ALL },
1742 { "st.h", two (0x07a0, 0x000d), two (0x07e0, 0x000f), {R3, D23_ALIGN1, R1}, 3, PROCESSOR_V850E2_UP },
1743 { "st.h23", two (0x07a0, 0x000d), two (0x07e0, 0x000f), {R3, D23_ALIGN1, R1}, 3, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS },
1745 { "st.w", two (0x0760, 0x0001), two (0x07e0, 0x0001), {R2, D16_15, R1}, 3, PROCESSOR_ALL },
1746 { "st.w", two (0x0780, 0x000f), two (0x07e0, 0x000f), {R3, D23_ALIGN1, R1}, 3, PROCESSOR_V850E2_UP },
1747 { "st.w23", two (0x0780, 0x000f), two (0x07e0, 0x000f), {R3, D23_ALIGN1, R1}, 3, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS },
1749 { "stc.w", two (0x07e0, 0x037a), two (0xffe0, 0x07ff), {R3, R1}, 2, PROCESSOR_V850E3V5_UP },
1751 { "stsr", two (0x07e0, 0x0040), two (0x07e0, 0x07ff), {SR1, R2, SELID}, 0, PROCESSOR_V850E3V5_UP },
1752 { "stsr", two (0x07e0, 0x0040), two (0x07e0, 0x07ff), {SR1, R2}, 0, PROCESSOR_V850E3V5_UP },
1753 { "stsr", two (0x07e0, 0x0040), two (0x07e0, 0x07ff), {OLDSR1, R2}, 0, (PROCESSOR_ALL & (~ PROCESSOR_V850E3V5_UP)) },
1755 { "sttc.gr", two (0x07e0, 0x0052), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_V850E3V5_UP },
1756 { "sttc.sr", two (0x07e0, 0x0050), two (0x07e0, 0x07ff), {SR1, R2, SELID}, 0, PROCESSOR_V850E3V5_UP },
1757 { "sttc.sr", two (0x07e0, 0x0050), two (0x07e0, 0x07ff), {SR1, R2}, 0, PROCESSOR_V850E3V5_UP },
1758 { "sttc.vr", two (0x07e0, 0x0852), two (0x07e0, 0xffff), {VR1, R2}, 0, PROCESSOR_V850E3V5_UP },
1759 { "sttc.pc", two (0x07e0, 0xf852), two (0x07e0, 0xffff), {R2}, 0, PROCESSOR_V850E3V5_UP },
1761 { "stvc.sr", two (0x07e0, 0x0054), two (0x07e0, 0x07ff), {SR1, R2, SELID}, 0, PROCESSOR_V850E3V5_UP },
1762 { "stvc.sr", two (0x07e0, 0x0054), two (0x07e0, 0x07ff), {SR1, R2}, 0, PROCESSOR_V850E3V5_UP },
1764 { "sub", OP (0x0d), OP_MASK, IF1, 0, PROCESSOR_ALL },
1766 { "subr", OP (0x0c), OP_MASK, IF1, 0, PROCESSOR_ALL },
1768 { "switch", one (0x0040), one (0xffe0), {R1_NOTR0}, 0, PROCESSOR_NOT_V850 },
1770 { "sxb", one (0x00a0), one (0xffe0), {R1}, 0, PROCESSOR_NOT_V850 },
1772 { "sxh", one (0x00e0), one (0xffe0), {R1}, 0, PROCESSOR_NOT_V850 },
1774 { "tlbai", two (0x87e0, 0x8960), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E3V5_UP },
1775 { "tlbr", two (0x87e0, 0xe960), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E3V5_UP },
1776 { "tlbs", two (0x87e0, 0xc160), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E3V5_UP },
1777 { "tlbvi", two (0x87e0, 0x8160), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E3V5_UP },
1778 { "tlbw", two (0x87e0, 0xe160), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E3V5_UP },
1780 { "trap", two (0x07e0, 0x0100), two (0xffe0, 0xffff), {I5U}, 0, PROCESSOR_ALL },
1782 { "tst", OP (0x0b), OP_MASK, IF1, 0, PROCESSOR_ALL },
1784 { "tst1", two (0xc7c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 3, PROCESSOR_ALL },
1785 { "tst1", two (0x07e0, 0x00e6), two (0x07e0, 0xffff), {R2, R1}, 3, PROCESSOR_NOT_V850 },
1787 { "xor", OP (0x09), OP_MASK, IF1, 0, PROCESSOR_ALL },
1789 { "xori", OP (0x35), OP_MASK, IF6U, 0, PROCESSOR_ALL },
1791 { "zxb", one (0x0080), one (0xffe0), {R1}, 0, PROCESSOR_NOT_V850 },
1793 { "zxh", one (0x00c0), one (0xffe0), {R1}, 0, PROCESSOR_NOT_V850 },
1795 /* Floating point operation. */
1796 { "absf.d", two (0x07e0, 0x0458), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1797 { "absf.s", two (0x07e0, 0x0448), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP },
1798 { "addf.d", two (0x07e0, 0x0470), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1799 { "addf.s", two (0x07e0, 0x0460), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2V3_UP },
1800 { "ceilf.dl", two (0x07e2, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1801 { "ceilf.dul", two (0x07f2, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1802 { "ceilf.duw", two (0x07f2, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP },
1803 { "ceilf.dw", two (0x07e2, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP },
1804 { "ceilf.sl", two (0x07e2, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1805 { "ceilf.sul", two (0x07f2, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1806 { "ceilf.suw", two (0x07f2, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP },
1807 { "ceilf.sw", two (0x07e2, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP },
1808 { "cmovf.d", two (0x07e0, 0x0410), two (0x0fe1, 0x0ff1), {FFF, R1_EVEN, R2_EVEN, R3_EVEN_NOTR0}, 0, PROCESSOR_V850E2V3_UP },
1809 /* Default value for FFF is 0(not defined in spec). */
1810 { "cmovf.d", two (0x07e0, 0x0410), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN_NOTR0}, 0, PROCESSOR_V850E2V3_UP },
1811 { "cmovf.s", two (0x07e0, 0x0400), two (0x07e0, 0x07f1), {FFF, R1, R2, R3_NOTR0}, 0, PROCESSOR_V850E2V3_UP },
1812 /* Default value for FFF is 0(not defined in spec). */
1813 { "cmovf.s", two (0x07e0, 0x0400), two (0x07e0, 0x07ff), {R1, R2, R3_NOTR0}, 0, PROCESSOR_V850E2V3_UP },
1814 { "cmpf.d", two (0x07e0, 0x0430), two (0x0fe1, 0x87f1), {FLOAT_CCCC, R2_EVEN, R1_EVEN, FFF}, 0, PROCESSOR_V850E2V3_UP },
1815 { "cmpf.d", two (0x07e0, 0x0430), two (0x0fe1, 0x87ff), {FLOAT_CCCC, R2_EVEN, R1_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1816 { "cmpf.s", two (0x07e0, 0x0420), two (0x07e0, 0x87f1), {FLOAT_CCCC, R2, R1, FFF}, 0, PROCESSOR_V850E2V3_UP },
1817 { "cmpf.s", two (0x07e0, 0x0420), two (0x07e0, 0x87ff), {FLOAT_CCCC, R2, R1}, 0, PROCESSOR_V850E2V3_UP },
1818 { "cvtf.dl", two (0x07e4, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1819 { "cvtf.ds", two (0x07e3, 0x0452), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP },
1820 { "cvtf.dul", two (0x07f4, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1821 { "cvtf.duw", two (0x07f4, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP },
1822 { "cvtf.dw", two (0x07e4, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP },
1823 { "cvtf.hs", two (0x07e2, 0x0442), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E3V5_UP },
1824 { "cvtf.ld", two (0x07e1, 0x0452), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1825 { "cvtf.ls", two (0x07e1, 0x0442), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP },
1826 { "cvtf.sd", two (0x07e2, 0x0452), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1827 { "cvtf.sl", two (0x07e4, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1828 { "cvtf.sh", two (0x07e3, 0x0442), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E3V5_UP },
1829 { "cvtf.sul", two (0x07f4, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1830 { "cvtf.suw", two (0x07f4, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP },
1831 { "cvtf.sw", two (0x07e4, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP },
1832 { "cvtf.uld", two (0x07f1, 0x0452), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1833 { "cvtf.uls", two (0x07f1, 0x0442), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP },
1834 { "cvtf.uwd", two (0x07f0, 0x0452), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1835 { "cvtf.uws", two (0x07f0, 0x0442), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP },
1836 { "cvtf.wd", two (0x07e0, 0x0452), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1837 { "cvtf.ws", two (0x07e0, 0x0442), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP },
1838 { "divf.d", two (0x07e0, 0x047e), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1839 { "divf.s", two (0x07e0, 0x046e), two (0x07e0, 0x07ff), {R1_NOTR0, R2, R3}, 0, PROCESSOR_V850E2V3_UP },
1840 { "floorf.dl", two (0x07e3, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1841 { "floorf.dul", two (0x07f3, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1842 { "floorf.duw", two (0x07f3, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP },
1843 { "floorf.dw", two (0x07e3, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP },
1844 { "floorf.sl", two (0x07e3, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1845 { "floorf.sul", two (0x07f3, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1846 { "floorf.suw", two (0x07f3, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP },
1847 { "floorf.sw", two (0x07e3, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP },
1848 { "maddf.s", two (0x07e0, 0x0500), two (0x07e0, 0x0761), {R1, R2, R3, R4}, 0, PROCESSOR_V850E2V3 },
1849 { "fmaf.s", two (0x07e0, 0x04e0), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E3V5_UP },
1850 { "maxf.d", two (0x07e0, 0x0478), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1851 { "maxf.s", two (0x07e0, 0x0468), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2V3_UP },
1852 { "minf.d", two (0x07e0, 0x047a), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1853 { "minf.s", two (0x07e0, 0x046a), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2V3_UP },
1854 { "msubf.s", two (0x07e0, 0x0520), two (0x07e0, 0x0761), {R1, R2, R3, R4}, 0, PROCESSOR_V850E2V3 },
1855 { "fmsf.s", two (0x07e0, 0x04e2), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E3V5_UP },
1856 { "mulf.d", two (0x07e0, 0x0474), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1857 { "mulf.s", two (0x07e0, 0x0464), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2V3_UP },
1858 { "negf.d", two (0x07e1, 0x0458), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1859 { "negf.s", two (0x07e1, 0x0448), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP },
1860 { "nmaddf.s", two (0x07e0, 0x0540), two (0x07e0, 0x0761), {R1, R2, R3, R4}, 0, PROCESSOR_V850E2V3 },
1861 { "fnmaf.s", two (0x07e0, 0x04e4), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E3V5_UP },
1862 { "nmsubf.s", two (0x07e0, 0x0560), two (0x07e0, 0x0761), {R1, R2, R3, R4}, 0, PROCESSOR_V850E2V3 },
1863 { "fnmsf.s", two (0x07e0, 0x04e6), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E3V5_UP },
1864 { "recipf.d", two (0x07e1, 0x045e), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1865 { "recipf.s", two (0x07e1, 0x044e), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP },
1867 { "roundf.dl", two (0x07e0, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_EXTENSION },
1868 { "roundf.dul", two (0x07f0, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_EXTENSION },
1869 { "roundf.duw", two (0x07f0, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_EXTENSION },
1870 { "roundf.dw", two (0x07e0, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_EXTENSION },
1871 { "roundf.sl", two (0x07e0, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_EXTENSION },
1872 { "roundf.sul", two (0x07f0, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_EXTENSION },
1873 { "roundf.suw", two (0x07f0, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_EXTENSION },
1874 { "roundf.sw", two (0x07e0, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_EXTENSION },
1876 { "rsqrtf.d", two (0x07e2, 0x045e), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1877 { "rsqrtf.s", two (0x07e2, 0x044e), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP },
1878 { "sqrtf.d", two (0x07e0, 0x045e), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1879 { "sqrtf.s", two (0x07e0, 0x044e), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP },
1880 { "subf.d", two (0x07e0, 0x0472), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1881 { "subf.s", two (0x07e0, 0x0462), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2V3_UP },
1882 { "trfsr", two (0x07e0, 0x0400), two (0xffff, 0xfff1), {FFF}, 0, PROCESSOR_V850E2V3_UP },
1883 { "trfsr", two (0x07e0, 0x0400), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E2V3_UP },
1884 { "trncf.dl", two (0x07e1, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1885 { "trncf.dul", two (0x07f1, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1886 { "trncf.duw", two (0x07f1, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP },
1887 { "trncf.dw", two (0x07e1, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP },
1888 { "trncf.sl", two (0x07e1, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1889 { "trncf.sul", two (0x07f1, 0x0444), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP },
1890 { "trncf.suw", two (0x07f1, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP },
1891 { "trncf.sw", two (0x07e1, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP },
1893 /* Special instruction (from gdb) mov 1, r0. */
1894 { "breakpoint", one (0x0001), one (0xffff), {UNUSED}, 0, PROCESSOR_ALL },
1896 { "synci", one (0x001c), one (0xffff), {0}, 0, PROCESSOR_V850E3V5_UP },
1898 { "synce", one (0x001d), one (0xffff), {0}, 0, PROCESSOR_V850E2V3_UP },
1899 { "syncm", one (0x001e), one (0xffff), {0}, 0, PROCESSOR_V850E2V3_UP },
1900 { "syncp", one (0x001f), one (0xffff), {0}, 0, PROCESSOR_V850E2V3_UP },
1901 { "syscall", two (0xd7e0, 0x0160), two (0xffe0, 0xc7ff), {V8}, 0, PROCESSOR_V850E2V3_UP },
1902 /* Alias of syncp. */
1903 { "sync", one (0x001f), one (0xffff), {0}, 0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_ALIAS },
1904 { "rmtrap", one (0xf040), one (0xffff), {0}, 0, PROCESSOR_V850E2V3_UP },
1905 { "rie", one (0x0040), one (0xffff), {0}, 0, PROCESSOR_V850E2V3_UP },
1906 { "rie", two (0x07f0, 0x0000), two (0x07f0, 0xffff), {RIE_IMM5,RIE_IMM4}, 0, PROCESSOR_V850E2V3_UP },
1908 { 0, 0, 0, {0}, 0, 0 },
1911 const int v850_num_opcodes =
1912 sizeof (v850_opcodes) / sizeof (v850_opcodes[0]);