gdb/microblaze-tdep.c

   1 /* Target-dependent code for Xilinx MicroBlaze.
   2
   3    Copyright (C) 2009-2014 Free Software Foundation, Inc.
   4
   5    This file is part of GDB.
   6
   7    This program is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3 of the License, or
  10    (at your option) any later version.
  11
  12    This program is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  19
  20 #include "defs.h"
  21 #include "arch-utils.h"
  22 #include "dis-asm.h"
  23 #include "frame.h"
  24 #include "trad-frame.h"
  25 #include "symtab.h"
  26 #include "value.h"
  27 #include "gdbcmd.h"
  28 #include "breakpoint.h"
  29 #include "inferior.h"
  30 #include "regcache.h"
  31 #include "target.h"
  32 #include "frame-base.h"
  33 #include "frame-unwind.h"
  34 #include "dwarf2-frame.h"
  35 #include "osabi.h"
  36
  37 #include "gdb_assert.h"
  38 #include <string.h>
  39 #include "target-descriptions.h"
  40 #include "opcodes/microblaze-opcm.h"
  41 #include "opcodes/microblaze-dis.h"
  42 #include "microblaze-tdep.h"
  43 \f
  44 /* Instruction macros used for analyzing the prologue.  */
  45 /* This set of instruction macros need to be changed whenever the
  46    prologue generated by the compiler could have more instructions or
  47    different type of instructions.
  48    This set also needs to be verified if it is complete.  */
  49 #define IS_RETURN(op) (op == rtsd || op == rtid)
  50 #define IS_UPDATE_SP(op, rd, ra) \
  51   ((op == addik || op == addi) && rd == REG_SP && ra == REG_SP)
  52 #define IS_SPILL_SP(op, rd, ra) \
  53   ((op == swi || op == sw) && rd == REG_SP && ra == REG_SP)
  54 #define IS_SPILL_REG(op, rd, ra) \
  55   ((op == swi || op == sw) && rd != REG_SP && ra == REG_SP)
  56 #define IS_ALSO_SPILL_REG(op, rd, ra, rb) \
  57   ((op == swi || op == sw) && rd != REG_SP && ra == 0 && rb == REG_SP)
  58 #define IS_SETUP_FP(op, ra, rb) \
  59   ((op == add || op == addik || op == addk) && ra == REG_SP && rb == 0)
  60 #define IS_SPILL_REG_FP(op, rd, ra, fpregnum) \
  61   ((op == swi || op == sw) && rd != REG_SP && ra == fpregnum && ra != 0)
  62 #define IS_SAVE_HIDDEN_PTR(op, rd, ra, rb) \
  63   ((op == add || op == addik) && ra == MICROBLAZE_FIRST_ARGREG && rb == 0)
  64
  65 /* The registers of the Xilinx microblaze processor.  */
  66
  67 static const char *microblaze_register_names[] =
  68 {
  69   "r0",   "r1",  "r2",    "r3",   "r4",   "r5",   "r6",   "r7",
  70   "r8",   "r9",  "r10",   "r11",  "r12",  "r13",  "r14",  "r15",
  71   "r16",  "r17", "r18",   "r19",  "r20",  "r21",  "r22",  "r23",
  72   "r24",  "r25", "r26",   "r27",  "r28",  "r29",  "r30",  "r31",
  73   "rpc",  "rmsr", "rear", "resr", "rfsr", "rbtr",
  74   "rpvr0", "rpvr1", "rpvr2", "rpvr3", "rpvr4", "rpvr5", "rpvr6",
  75   "rpvr7", "rpvr8", "rpvr9", "rpvr10", "rpvr11",
  76   "redr", "rpid", "rzpr", "rtlbx", "rtlbsx", "rtlblo", "rtlbhi"
  77 };
  78
  79 #define MICROBLAZE_NUM_REGS ARRAY_SIZE (microblaze_register_names)
  80 \f
  81 static unsigned int microblaze_debug_flag = 0;
  82
  83 static void
  84 microblaze_debug (const char *fmt, ...)
  85 {
  86   if (microblaze_debug_flag)
  87     {
  88        va_list args;
  89
  90        va_start (args, fmt);
  91        printf_unfiltered ("MICROBLAZE: ");
  92        vprintf_unfiltered (fmt, args);
  93        va_end (args);
  94     }
  95 }
  96 \f
  97 /* Return the name of register REGNUM.  */
  98
  99 static const char *
 100 microblaze_register_name (struct gdbarch *gdbarch, int regnum)
 101 {
 102   if (regnum >= 0 && regnum < MICROBLAZE_NUM_REGS)
 103     return microblaze_register_names[regnum];
 104   return NULL;
 105 }
 106
 107 static struct type *
 108 microblaze_register_type (struct gdbarch *gdbarch, int regnum)
 109 {
 110   if (regnum == MICROBLAZE_SP_REGNUM)
 111     return builtin_type (gdbarch)->builtin_data_ptr;
 112
 113   if (regnum == MICROBLAZE_PC_REGNUM)
 114     return builtin_type (gdbarch)->builtin_func_ptr;
 115
 116   return builtin_type (gdbarch)->builtin_int;
 117 }
 118
 119 \f
 120 /* Fetch the instruction at PC.  */
 121
 122 static unsigned long
 123 microblaze_fetch_instruction (CORE_ADDR pc)
 124 {
 125   enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ());
 126   gdb_byte buf[4];
 127
 128   /* If we can't read the instruction at PC, return zero.  */
 129   if (target_read_memory (pc, buf, sizeof (buf)))
 130     return 0;
 131
 132   return extract_unsigned_integer (buf, 4, byte_order);
 133 }
 134 \f
 135
 136 static CORE_ADDR
 137 microblaze_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp,
 138                             CORE_ADDR funcaddr,
 139                             struct value **args, int nargs,
 140                             struct type *value_type,
 141                             CORE_ADDR *real_pc, CORE_ADDR *bp_addr,
 142                             struct regcache *regcache)
 143 {
 144   error (_("push_dummy_code not implemented"));
 145   return sp;
 146 }
 147
 148
 149 static CORE_ADDR
 150 microblaze_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
 151                             struct regcache *regcache, CORE_ADDR bp_addr,
 152                             int nargs, struct value **args, CORE_ADDR sp,
 153                             int struct_return, CORE_ADDR struct_addr)
 154 {
 155   error (_("store_arguments not implemented"));
 156   return sp;
 157 }
 158
 159 static const gdb_byte *
 160 microblaze_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc,
 161                                int *len)
 162 {
 163   static gdb_byte break_insn[] = MICROBLAZE_BREAKPOINT;
 164
 165   *len = sizeof (break_insn);
 166   return break_insn;
 167 }
 168 \f
 169 /* Allocate and initialize a frame cache.  */
 170
 171 static struct microblaze_frame_cache *
 172 microblaze_alloc_frame_cache (void)
 173 {
 174   struct microblaze_frame_cache *cache;
 175
 176   cache = FRAME_OBSTACK_ZALLOC (struct microblaze_frame_cache);
 177
 178   /* Base address.  */
 179   cache->base = 0;
 180   cache->pc = 0;
 181
 182   /* Frameless until proven otherwise.  */
 183   cache->frameless_p = 1;
 184
 185   return cache;
 186 }
 187
 188 /* The base of the current frame is actually in the stack pointer.
 189    This happens when there is no frame pointer (microblaze ABI does not
 190    require a frame pointer) or when we're stopped in the prologue or
 191    epilogue itself.  In these cases, microblaze_analyze_prologue will need
 192    to update fi->frame before returning or analyzing the register
 193    save instructions.  */
 194 #define MICROBLAZE_MY_FRAME_IN_SP 0x1
 195
 196 /* The base of the current frame is in a frame pointer register.
 197    This register is noted in frame_extra_info->fp_regnum.
 198
 199    Note that the existance of an FP might also indicate that the
 200    function has called alloca.  */
 201 #define MICROBLAZE_MY_FRAME_IN_FP 0x2
 202
 203 /* Function prologues on the Xilinx microblaze processors consist of:
 204
 205    - adjustments to the stack pointer (r1) (addi r1, r1, imm)
 206    - making a copy of r1 into another register (a "frame" pointer)
 207      (add r?, r1, r0)
 208    - store word/multiples that use r1 or the frame pointer as the
 209      base address (swi r?, r1, imm OR swi r?, fp, imm)
 210
 211    Note that microblaze really doesn't have a real frame pointer.
 212    Instead, the compiler may copy the SP into a register (usually
 213    r19) to act as an arg pointer.  For our target-dependent purposes,
 214    the frame info's "frame" member will be the beginning of the
 215    frame.  The SP could, in fact, point below this.
 216
 217    The prologue ends when an instruction fails to meet either of
 218    these criteria.  */
 219
 220 /* Analyze the prologue to determine where registers are saved,
 221    the end of the prologue, etc.  Return the address of the first line
 222    of "real" code (i.e., the end of the prologue).  */
 223
 224 static CORE_ADDR
 225 microblaze_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc,
 226                              CORE_ADDR current_pc,
 227                              struct microblaze_frame_cache *cache)
 228 {
 229   const char *name;
 230   CORE_ADDR func_addr, func_end, addr, stop, prologue_end_addr = 0;
 231   unsigned long insn;
 232   int rd, ra, rb, imm;
 233   enum microblaze_instr op;
 234   int flags = 0;
 235   int save_hidden_pointer_found = 0;
 236   int non_stack_instruction_found = 0;
 237
 238   /* Find the start of this function.  */
 239   find_pc_partial_function (pc, &name, &func_addr, &func_end);
 240   if (func_addr < pc)
 241     pc = func_addr;
 242
 243   if (current_pc < pc)
 244     return current_pc;
 245
 246    /* Initialize info about frame.  */
 247    cache->framesize = 0;
 248    cache->fp_regnum = MICROBLAZE_SP_REGNUM;
 249    cache->frameless_p = 1;
 250
 251   /* Start decoding the prologue.  We start by checking two special cases:
 252
 253      1. We're about to return
 254      2. We're at the first insn of the prologue.
 255
 256      If we're about to return, our frame has already been deallocated.
 257      If we are stopped at the first instruction of a prologue,
 258      then our frame has not yet been set up.  */
 259
 260   /* Get the first insn from memory.  */
 261
 262   insn = microblaze_fetch_instruction (pc);
 263   op = microblaze_decode_insn (insn, &rd, &ra, &rb, &imm);
 264
 265   if (IS_RETURN(op))
 266     return pc;
 267
 268   /* Start at beginning of function and analyze until we get to the
 269      current pc, or the end of the function, whichever is first.  */
 270   stop = (current_pc < func_end ? current_pc : func_end);
 271
 272   microblaze_debug ("Scanning prologue: name=%s, func_addr=%s, stop=%s\n",
 273                     name, paddress (gdbarch, func_addr),
 274                     paddress (gdbarch, stop));
 275
 276   for (addr = func_addr; addr < stop; addr += INST_WORD_SIZE)
 277     {
 278       insn = microblaze_fetch_instruction (addr);
 279       op = microblaze_decode_insn (insn, &rd, &ra, &rb, &imm);
 280       microblaze_debug ("%s %08lx\n", paddress (gdbarch, pc), insn);
 281
 282       /* This code is very sensitive to what functions are present in the
 283          prologue.  It assumes that the (addi, addik, swi, sw) can be the
 284          only instructions in the prologue.  */
 285       if (IS_UPDATE_SP(op, rd, ra))
 286         {
 287           microblaze_debug ("got addi r1,r1,%d; contnuing\n", imm);
 288           if (cache->framesize)
 289             break;      /* break if framesize already computed.  */
 290           cache->framesize = -imm; /* stack grows towards low memory.  */
 291           cache->frameless_p = 0; /* Frame found.  */
 292           save_hidden_pointer_found = 0;
 293           non_stack_instruction_found = 0;
 294           continue;
 295         }
 296       else if (IS_SPILL_SP(op, rd, ra))
 297         {
 298           /* Spill stack pointer.  */
 299           cache->register_offsets[rd] = imm; /* SP spilled before updating.  */
 300
 301           microblaze_debug ("swi r1 r1 %d, continuing\n", imm);
 302           save_hidden_pointer_found = 0;
 303           if (!cache->framesize)
 304             non_stack_instruction_found = 0;
 305           continue;
 306         }
 307       else if (IS_SPILL_REG(op, rd, ra))
 308         {
 309           /* Spill register.  */
 310           cache->register_offsets[rd] = imm - cache->framesize;
 311
 312           microblaze_debug ("swi %d r1 %d, continuing\n", rd, imm);
 313           save_hidden_pointer_found = 0;
 314           if (!cache->framesize)
 315             non_stack_instruction_found = 0;
 316           continue;
 317         }
 318       else if (IS_ALSO_SPILL_REG(op, rd, ra, rb))
 319         {
 320           /* Spill register.  */
 321           cache->register_offsets[rd] = 0 - cache->framesize;
 322
 323           microblaze_debug ("sw %d r0 r1, continuing\n", rd);
 324           save_hidden_pointer_found = 0;
 325           if (!cache->framesize)
 326             non_stack_instruction_found = 0;
 327           continue;
 328         }
 329       else if (IS_SETUP_FP(op, ra, rb))
 330         {
 331           /* We have a frame pointer.  Note the register which is
 332              acting as the frame pointer.  */
 333           flags |= MICROBLAZE_MY_FRAME_IN_FP;
 334           flags &= ~MICROBLAZE_MY_FRAME_IN_SP;
 335           cache->fp_regnum = rd;
 336           microblaze_debug ("Found a frame pointer: r%d\n", cache->fp_regnum);
 337           save_hidden_pointer_found = 0;
 338           if (!cache->framesize)
 339             non_stack_instruction_found = 0;
 340           continue;
 341         }
 342       else if (IS_SPILL_REG_FP(op, rd, ra, cache->fp_regnum))
 343         {
 344           /* reg spilled after updating.  */
 345           cache->register_offsets[rd] = imm - cache->framesize;
 346
 347           microblaze_debug ("swi %d %d %d, continuing\n", rd, ra, imm);
 348           save_hidden_pointer_found = 0;
 349           if (!cache->framesize)
 350             non_stack_instruction_found = 0;
 351           continue;
 352         }
 353       else if (IS_SAVE_HIDDEN_PTR(op, rd, ra, rb))
 354         {
 355           /* If the first argument is a hidden pointer to the area where the
 356              return structure is to be saved, then it is saved as part of the
 357              prologue.  */
 358
 359           microblaze_debug ("add %d %d %d, continuing\n", rd, ra, rb);
 360           save_hidden_pointer_found = 1;
 361           if (!cache->framesize)
 362             non_stack_instruction_found = 0;
 363           continue;
 364         }
 365
 366       /* As a result of the modification in the next step where we continue
 367          to analyze the prologue till we reach a control flow instruction,
 368          we need another variable to store when exactly a non-stack
 369          instruction was encountered, which is the current definition
 370          of a prologue.  */
 371       if (!non_stack_instruction_found)
 372         prologue_end_addr = addr;
 373       non_stack_instruction_found = 1;
 374
 375       /* When optimizations are enabled, it is not guaranteed that prologue
 376          instructions are not mixed in with other instructions from the
 377          program.  Some programs show this behavior at -O2.  This can be
 378          avoided by adding -fno-schedule-insns2 switch as of now (edk 8.1)
 379          In such cases, we scan the function until we see the first control
 380          instruction.  */
 381
 382       {
 383         unsigned op = (unsigned)insn >> 26;
 384
 385         /* continue if not control flow (branch, return).  */
 386         if (op != 0x26 && op != 0x27 && op != 0x2d && op != 0x2e && op != 0x2f)
 387           continue;
 388         else if (op == 0x2c)
 389           continue;    /* continue if imm.  */
 390       }
 391
 392       /* This is not a prologue insn, so stop here.  */
 393       microblaze_debug ("insn is not a prologue insn -- ending scan\n");
 394       break;
 395     }
 396
 397   microblaze_debug ("done analyzing prologue\n");
 398   microblaze_debug ("prologue end = 0x%x\n", (int) addr);
 399
 400   /* If the last instruction was an add rd, r5, r0 then don't count it as
 401      part of the prologue.  */
 402   if (save_hidden_pointer_found)
 403     prologue_end_addr -= INST_WORD_SIZE;
 404
 405   return prologue_end_addr;
 406 }
 407
 408 static CORE_ADDR
 409 microblaze_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
 410 {
 411   gdb_byte buf[4];
 412   CORE_ADDR pc;
 413
 414   frame_unwind_register (next_frame, MICROBLAZE_PC_REGNUM, buf);
 415   pc = extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
 416   /* For sentinel frame, return address is actual PC.  For other frames,
 417      return address is pc+8.  This is a workaround because gcc does not
 418      generate correct return address in CIE.  */
 419   if (frame_relative_level (next_frame) >= 0)
 420     pc += 8;
 421   return pc;
 422 }
 423
 424 /* Return PC of first real instruction of the function starting at
 425    START_PC.  */
 426
 427 static CORE_ADDR
 428 microblaze_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
 429 {
 430   struct symtab_and_line sal;
 431   CORE_ADDR func_start, func_end, ostart_pc;
 432   struct microblaze_frame_cache cache;
 433
 434   /* This is the preferred method, find the end of the prologue by
 435      using the debugging information.  Debugging info does not always
 436      give the right answer since parameters are stored on stack after this.
 437      Always analyze the prologue.  */
 438   if (find_pc_partial_function (start_pc, NULL, &func_start, &func_end))
 439     {
 440       sal = find_pc_line (func_start, 0);
 441
 442       if (sal.end < func_end
 443           && start_pc <= sal.end)
 444         start_pc = sal.end;
 445     }
 446
 447   ostart_pc = microblaze_analyze_prologue (gdbarch, func_start, 0xffffffffUL,
 448                                            &cache);
 449
 450   if (ostart_pc > start_pc)
 451     return ostart_pc;
 452   return start_pc;
 453 }
 454
 455 /* Normal frames.  */
 456
 457 static struct microblaze_frame_cache *
 458 microblaze_frame_cache (struct frame_info *next_frame, void **this_cache)
 459 {
 460   struct microblaze_frame_cache *cache;
 461   struct gdbarch *gdbarch = get_frame_arch (next_frame);
 462   CORE_ADDR func;
 463   int rn;
 464
 465   if (*this_cache)
 466     return *this_cache;
 467
 468   cache = microblaze_alloc_frame_cache ();
 469   *this_cache = cache;
 470   cache->saved_regs = trad_frame_alloc_saved_regs (next_frame);
 471
 472   /* Clear offsets to saved regs in frame.  */
 473   for (rn = 0; rn < gdbarch_num_regs (gdbarch); rn++)
 474     cache->register_offsets[rn] = -1;
 475
 476   func = get_frame_func (next_frame);
 477
 478   cache->pc = get_frame_address_in_block (next_frame);
 479
 480   return cache;
 481 }
 482
 483 static void
 484 microblaze_frame_this_id (struct frame_info *next_frame, void **this_cache,
 485                        struct frame_id *this_id)
 486 {
 487   struct microblaze_frame_cache *cache =
 488     microblaze_frame_cache (next_frame, this_cache);
 489
 490   /* This marks the outermost frame.  */
 491   if (cache->base == 0)
 492     return;
 493
 494   (*this_id) = frame_id_build (cache->base, cache->pc);
 495 }
 496
 497 static struct value *
 498 microblaze_frame_prev_register (struct frame_info *this_frame,
 499                                  void **this_cache, int regnum)
 500 {
 501   struct microblaze_frame_cache *cache =
 502     microblaze_frame_cache (this_frame, this_cache);
 503
 504   if (cache->frameless_p)
 505     {
 506       if (regnum == MICROBLAZE_PC_REGNUM)
 507         regnum = 15;
 508       if (regnum == MICROBLAZE_SP_REGNUM)
 509         regnum = 1;
 510       return trad_frame_get_prev_register (this_frame,
 511                                            cache->saved_regs, regnum);
 512     }
 513   else
 514     return trad_frame_get_prev_register (this_frame, cache->saved_regs,
 515                                          regnum);
 516
 517 }
 518
 519 static const struct frame_unwind microblaze_frame_unwind =
 520 {
 521   NORMAL_FRAME,
 522   default_frame_unwind_stop_reason,
 523   microblaze_frame_this_id,
 524   microblaze_frame_prev_register,
 525   NULL,
 526   default_frame_sniffer
 527 };
 528 \f
 529 static CORE_ADDR
 530 microblaze_frame_base_address (struct frame_info *next_frame,
 531                                void **this_cache)
 532 {
 533   struct microblaze_frame_cache *cache =
 534     microblaze_frame_cache (next_frame, this_cache);
 535
 536   return cache->base;
 537 }
 538
 539 static const struct frame_base microblaze_frame_base =
 540 {
 541   &microblaze_frame_unwind,
 542   microblaze_frame_base_address,
 543   microblaze_frame_base_address,
 544   microblaze_frame_base_address
 545 };
 546 \f
 547 /* Extract from an array REGBUF containing the (raw) register state, a
 548    function return value of TYPE, and copy that into VALBUF.  */
 549 static void
 550 microblaze_extract_return_value (struct type *type, struct regcache *regcache,
 551                                  gdb_byte *valbuf)
 552 {
 553   gdb_byte buf[8];
 554
 555   /* Copy the return value (starting) in RETVAL_REGNUM to VALBUF.  */
 556   switch (TYPE_LENGTH (type))
 557     {
 558       case 1:   /* return last byte in the register.  */
 559         regcache_cooked_read (regcache, MICROBLAZE_RETVAL_REGNUM, buf);
 560         memcpy(valbuf, buf + MICROBLAZE_REGISTER_SIZE - 1, 1);
 561         return;
 562       case 2:   /* return last 2 bytes in register.  */
 563         regcache_cooked_read (regcache, MICROBLAZE_RETVAL_REGNUM, buf);
 564         memcpy(valbuf, buf + MICROBLAZE_REGISTER_SIZE - 2, 2);
 565         return;
 566       case 4:   /* for sizes 4 or 8, copy the required length.  */
 567       case 8:
 568         regcache_cooked_read (regcache, MICROBLAZE_RETVAL_REGNUM, buf);
 569         regcache_cooked_read (regcache, MICROBLAZE_RETVAL_REGNUM+1, buf+4);
 570         memcpy (valbuf, buf, TYPE_LENGTH (type));
 571         return;
 572       default:
 573         internal_error (__FILE__, __LINE__,
 574                         _("Unsupported return value size requested"));
 575     }
 576 }
 577
 578 /* Store the return value in VALBUF (of type TYPE) where the caller
 579    expects to see it.
 580
 581    Integers up to four bytes are stored in r3.
 582
 583    Longs are stored in r3 (most significant word) and r4 (least
 584    significant word).
 585
 586    Small structures are always returned on stack.  */
 587
 588 static void
 589 microblaze_store_return_value (struct type *type, struct regcache *regcache,
 590                                const gdb_byte *valbuf)
 591 {
 592   int len = TYPE_LENGTH (type);
 593   gdb_byte buf[8];
 594
 595   memset (buf, 0, sizeof(buf));
 596
 597   /* Integral and pointer return values.  */
 598
 599   if (len > 4)
 600     {
 601        gdb_assert (len == 8);
 602        memcpy (buf, valbuf, 8);
 603        regcache_cooked_write (regcache, MICROBLAZE_RETVAL_REGNUM+1, buf + 4);
 604     }
 605   else
 606     /* ??? Do we need to do any sign-extension here?  */
 607     memcpy (buf + 4 - len, valbuf, len);
 608
 609   regcache_cooked_write (regcache, MICROBLAZE_RETVAL_REGNUM, buf);
 610 }
 611
 612 static enum return_value_convention
 613 microblaze_return_value (struct gdbarch *gdbarch, struct value *function,
 614                          struct type *type, struct regcache *regcache,
 615                          gdb_byte *readbuf, const gdb_byte *writebuf)
 616 {
 617   if (readbuf)
 618     microblaze_extract_return_value (type, regcache, readbuf);
 619   if (writebuf)
 620     microblaze_store_return_value (type, regcache, writebuf);
 621
 622   return RETURN_VALUE_REGISTER_CONVENTION;
 623 }
 624
 625 static int
 626 microblaze_stabs_argument_has_addr (struct gdbarch *gdbarch, struct type *type)
 627 {
 628   return (TYPE_LENGTH (type) == 16);
 629 }
 630
 631 static void
 632 microblaze_write_pc (struct regcache *regcache, CORE_ADDR pc)
 633 {
 634   regcache_cooked_write_unsigned (regcache, MICROBLAZE_PC_REGNUM, pc);
 635 }
 636 \f
 637 static int dwarf2_to_reg_map[78] =
 638 { 0  /* r0  */,   1  /* r1  */,   2  /* r2  */,   3  /* r3  */,  /*  0- 3 */
 639   4  /* r4  */,   5  /* r5  */,   6  /* r6  */,   7  /* r7  */,  /*  4- 7 */
 640   8  /* r8  */,   9  /* r9  */,  10  /* r10 */,  11  /* r11 */,  /*  8-11 */
 641   12 /* r12 */,  13  /* r13 */,  14  /* r14 */,  15  /* r15 */,  /* 12-15 */
 642   16 /* r16 */,  17  /* r17 */,  18  /* r18 */,  19  /* r19 */,  /* 16-19 */
 643   20 /* r20 */,  21  /* r21 */,  22  /* r22 */,  23  /* r23 */,  /* 20-23 */
 644   24 /* r24 */,  25  /* r25 */,  26  /* r26 */,  27  /* r27 */,  /* 24-25 */
 645   28 /* r28 */,  29  /* r29 */,  30  /* r30 */,  31  /* r31 */,  /* 28-31 */
 646   -1 /* $f0 */,  -1  /* $f1 */,  -1  /* $f2 */,  -1  /* $f3 */,  /* 32-35 */
 647   -1 /* $f4 */,  -1  /* $f5 */,  -1  /* $f6 */,  -1  /* $f7 */,  /* 36-39 */
 648   -1 /* $f8 */,  -1  /* $f9 */,  -1  /* $f10 */, -1  /* $f11 */, /* 40-43 */
 649   -1 /* $f12 */, -1  /* $f13 */, -1  /* $f14 */, -1  /* $f15 */, /* 44-47 */
 650   -1 /* $f16 */, -1  /* $f17 */, -1  /* $f18 */, -1  /* $f19 */, /* 48-51 */
 651   -1 /* $f20 */, -1  /* $f21 */, -1  /* $f22 */, -1  /* $f23 */, /* 52-55 */
 652   -1 /* $f24 */, -1  /* $f25 */, -1  /* $f26 */, -1  /* $f27 */, /* 56-59 */
 653   -1 /* $f28 */, -1  /* $f29 */, -1  /* $f30 */, -1  /* $f31 */, /* 60-63 */
 654   -1 /* hi   */, -1  /* lo   */, -1  /* accum*/, 33  /* rmsr */, /* 64-67 */
 655   -1 /* $fcc1*/, -1  /* $fcc2*/, -1  /* $fcc3*/, -1  /* $fcc4*/, /* 68-71 */
 656   -1 /* $fcc5*/, -1  /* $fcc6*/, -1  /* $fcc7*/, -1  /* $ap  */, /* 72-75 */
 657   -1 /* $rap */, -1  /* $frp */                                  /* 76-77 */
 658 };
 659
 660 static int
 661 microblaze_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int reg)
 662 {
 663   gdb_assert (reg < sizeof (dwarf2_to_reg_map));
 664   return dwarf2_to_reg_map[reg];
 665 }
 666
 667 static struct gdbarch *
 668 microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
 669 {
 670   struct gdbarch_tdep *tdep;
 671   struct gdbarch *gdbarch;
 672
 673   /* If there is already a candidate, use it.  */
 674   arches = gdbarch_list_lookup_by_info (arches, &info);
 675   if (arches != NULL)
 676     return arches->gdbarch;
 677
 678   /* Allocate space for the new architecture.  */
 679   tdep = XNEW (struct gdbarch_tdep);
 680   gdbarch = gdbarch_alloc (&info, tdep);
 681
 682   set_gdbarch_long_double_bit (gdbarch, 128);
 683
 684   set_gdbarch_num_regs (gdbarch, MICROBLAZE_NUM_REGS);
 685   set_gdbarch_register_name (gdbarch, microblaze_register_name);
 686   set_gdbarch_register_type (gdbarch, microblaze_register_type);
 687
 688   /* Register numbers of various important registers.  */
 689   set_gdbarch_sp_regnum (gdbarch, MICROBLAZE_SP_REGNUM);
 690   set_gdbarch_pc_regnum (gdbarch, MICROBLAZE_PC_REGNUM);
 691
 692   /* Map Dwarf2 registers to GDB registers.  */
 693   set_gdbarch_dwarf2_reg_to_regnum (gdbarch, microblaze_dwarf2_reg_to_regnum);
 694
 695   /* Call dummy code.  */
 696   set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
 697   set_gdbarch_push_dummy_code (gdbarch, microblaze_push_dummy_code);
 698   set_gdbarch_push_dummy_call (gdbarch, microblaze_push_dummy_call);
 699
 700   set_gdbarch_return_value (gdbarch, microblaze_return_value);
 701   set_gdbarch_stabs_argument_has_addr
 702     (gdbarch, microblaze_stabs_argument_has_addr);
 703
 704   set_gdbarch_skip_prologue (gdbarch, microblaze_skip_prologue);
 705
 706   /* Stack grows downward.  */
 707   set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
 708
 709   set_gdbarch_breakpoint_from_pc (gdbarch, microblaze_breakpoint_from_pc);
 710
 711   set_gdbarch_frame_args_skip (gdbarch, 8);
 712
 713   set_gdbarch_print_insn (gdbarch, print_insn_microblaze);
 714
 715   set_gdbarch_write_pc (gdbarch, microblaze_write_pc);
 716
 717   set_gdbarch_unwind_pc (gdbarch, microblaze_unwind_pc);
 718
 719   frame_base_set_default (gdbarch, &microblaze_frame_base);
 720
 721   /* Hook in ABI-specific overrides, if they have been registered.  */
 722   gdbarch_init_osabi (info, gdbarch);
 723
 724   /* Unwind the frame.  */
 725   dwarf2_append_unwinders (gdbarch);
 726   frame_unwind_append_unwinder (gdbarch, &microblaze_frame_unwind);
 727   frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer);
 728
 729   return gdbarch;
 730 }
 731
 732 /* Provide a prototype to silence -Wmissing-prototypes.  */
 733 void _initialize_microblaze_tdep (void);
 734
 735 void
 736 _initialize_microblaze_tdep (void)
 737 {
 738   register_gdbarch_init (bfd_arch_microblaze, microblaze_gdbarch_init);
 739
 740   /* Debug this files internals.  */
 741   add_setshow_zuinteger_cmd ("microblaze", class_maintenance,
 742                              &microblaze_debug_flag, _("\
 743 Set microblaze debugging."), _("\
 744 Show microblaze debugging."), _("\
 745 When non-zero, microblaze specific debugging is enabled."),
 746                              NULL,
 747                              NULL,
 748                              &setdebuglist, &showdebuglist);
 749
 750 }