From df0a2b6a11cf2ad9aec3b521189f918a13f1e48c Mon Sep 17 00:00:00 2001 From: blckmn Date: Sun, 9 Jul 2017 08:04:56 +1000 Subject: [PATCH] Minor code tidy --- src/main/target/stm32f7xx_hal_conf.h | 4 +- src/main/target/system_stm32f7xx.c | 173 +++++++++++++++-------------------- 2 files changed, 79 insertions(+), 98 deletions(-) diff --git a/src/main/target/stm32f7xx_hal_conf.h b/src/main/target/stm32f7xx_hal_conf.h index 26afa82fa..e8114a5a0 100644 --- a/src/main/target/stm32f7xx_hal_conf.h +++ b/src/main/target/stm32f7xx_hal_conf.h @@ -156,10 +156,12 @@ * @brief This is the HAL system configuration section */ #define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */ +#define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */ #define USE_RTOS 0U #define PREFETCH_ENABLE 0U #define ART_ACCLERATOR_ENABLE 0U /* To enable instruction cache and prefetch */ +#define INSTRUCTION_CACHE_ENABLE 1U +#define DATA_CACHE_ENABLE 0U /* ########################## Assert Selection ############################## */ /** diff --git a/src/main/target/system_stm32f7xx.c b/src/main/target/system_stm32f7xx.c index e0b094bd4..b928ecf60 100644 --- a/src/main/target/system_stm32f7xx.c +++ b/src/main/target/system_stm32f7xx.c @@ -167,16 +167,14 @@ RCC_OscInitStruct.PLL.PLLQ = PLL_Q; ret = HAL_RCC_OscConfig(&RCC_OscInitStruct); - if (ret != HAL_OK) - { - while (1) { ; } + if (ret != HAL_OK) { + while (1); } /* Activate the OverDrive to reach the 216 MHz Frequency */ ret = HAL_PWREx_EnableOverDrive(); - if (ret != HAL_OK) - { - while (1) { ; } + if (ret != HAL_OK) { + while (1); } /* Select PLLSAI output as USB clock source */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; @@ -184,9 +182,8 @@ PeriphClkInitStruct.PLLSAI.PLLSAIN = PLL_SAIN; PeriphClkInitStruct.PLLSAI.PLLSAIQ = PLL_SAIQ; PeriphClkInitStruct.PLLSAI.PLLSAIP = PLL_SAIP; - if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) - { - while (1) {}; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { + while (1); } /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ @@ -197,9 +194,8 @@ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; ret = HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7); - if (ret != HAL_OK) - { - while (1) { ; } + if (ret != HAL_OK) { + while (1); } PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART1|RCC_PERIPHCLK_USART2 @@ -221,9 +217,8 @@ PeriphClkInitStruct.I2c3ClockSelection = RCC_I2C3CLKSOURCE_PCLK1; PeriphClkInitStruct.I2c4ClockSelection = RCC_I2C4CLKSOURCE_PCLK1; ret = HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); - if (ret != HAL_OK) - { - while (1) { ; } + if (ret != HAL_OK) { + while (1); } // Activating the timerprescalers while the APBx prescalers are 1/2/4 will connect the TIMxCLK to HCLK which has been configured to 216MHz @@ -249,54 +244,53 @@ */ void SystemInit(void) { - /* FPU settings ------------------------------------------------------------*/ - #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + /* FPU settings ------------------------------------------------------------*/ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ - #endif - /* Reset the RCC clock configuration to the default reset state ------------*/ - /* Set HSION bit */ - RCC->CR |= (uint32_t)0x00000001; +#endif + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; - /* Reset CFGR register */ - RCC->CFGR = 0x00000000; + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; - /* Reset HSEON, CSSON and PLLON bits */ - RCC->CR &= (uint32_t)0xFEF6FFFF; + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; - /* Reset PLLCFGR register */ - RCC->PLLCFGR = 0x24003010; + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; - /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; - /* Disable all interrupts */ - RCC->CIR = 0x00000000; + /* Disable all interrupts */ + RCC->CIR = 0x00000000; /* Configure the Vector Table location add offset address ------------------*/ #ifdef VECT_TAB_SRAM - SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ + SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ #else - SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ #endif - /* Enable I-Cache */ - SCB_EnableICache(); - - /* Enable D-Cache */ - //SCB_EnableDCache(); - - /* Configure the system clock to 216 MHz */ - SystemClock_Config(); - - if (SystemCoreClock != 216000000) - { - while (1) - { - // There is a mismatch between the configured clock and the expected clock in portable.h - } - } - - + /* Enable I-Cache */ + if (INSTRUCTION_CACHE_ENABLE) { + SCB_EnableICache(); + } + + /* Enable D-Cache */ + if (DATA_CACHE_ENABLE) { + SCB_EnableDCache(); + } + + /* Configure the system clock to 216 MHz */ + SystemClock_Config(); + + if (SystemCoreClock != 216000000) { + // There is a mismatch between the configured clock and the expected clock in portable.h + while (1); + } } /** @@ -337,61 +331,46 @@ void SystemInit(void) */ void SystemCoreClockUpdate(void) { - uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; - /* Get SYSCLK source -------------------------------------------------------*/ - tmp = RCC->CFGR & RCC_CFGR_SWS; + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; - switch (tmp) - { + switch (tmp) { case 0x00: /* HSI used as system clock source */ - SystemCoreClock = HSI_VALUE; - break; + SystemCoreClock = HSI_VALUE; + break; case 0x04: /* HSE used as system clock source */ - SystemCoreClock = HSE_VALUE; - break; + SystemCoreClock = HSE_VALUE; + break; case 0x08: /* PLL used as system clock source */ - /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N SYSCLK = PLL_VCO / PLL_P */ - pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; - pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; - - if (pllsource != 0) - { - /* HSE used as PLL clock source */ - pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); - } - else - { - /* HSI used as PLL clock source */ - pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); - } - - pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; - SystemCoreClock = pllvco/pllp; - break; + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } else { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> 16) + 1) * 2; + SystemCoreClock = pllvco/pllp; + break; default: - SystemCoreClock = HSI_VALUE; - break; - } - /* Compute HCLK frequency --------------------------------------------------*/ - /* Get HCLK prescaler */ - tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; - /* HCLK frequency */ - SystemCoreClock >>= tmp; + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; } -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ -- 2.11.4.GIT