1 if(typeof exports === 'undefined') exports = {};
18 "muxRegOffset": "0x018",
36 "muxRegOffset": "0x01c",
54 "muxRegOffset": "0x008",
72 "muxRegOffset": "0x00c",
87 "mux": "gpmc_advn_ale",
90 "muxRegOffset": "0x090",
105 "mux": "gpmc_oen_ren",
108 "muxRegOffset": "0x094",
123 "mux": "gpmc_ben0_cle",
126 "muxRegOffset": "0x09c",
144 "muxRegOffset": "0x098",
162 "muxRegOffset": "0x034",
170 "pr1_pru0_pru_r30_15",
180 "muxRegOffset": "0x030",
188 "pr1_pru0_pru_r30_14",
199 "path": "ehrpwm.2:1",
203 "muxRegOffset": "0x024",
221 "muxRegOffset": "0x028",
227 "ehrpwm2_tripzone_input",
239 "muxRegOffset": "0x03c",
246 "pr1_ecap0_ecap_capin_apwm_o",
247 "pr1_pru0_pru_r31_15",
257 "muxRegOffset": "0x038",
265 "pr1_pru0_pru_r31_14",
275 "muxRegOffset": "0x02c",
293 "muxRegOffset": "0x08c",
296 "lcd_memory_clk_mux",
312 "path": "ehrpwm.2:0",
316 "muxRegOffset": "0x020",
334 "muxRegOffset": "0x084",
340 "pr1_edio_data_out7",
341 "pr1_pru1_pru_r30_13",
342 "pr1_pru1_pru_r31_13",
352 "muxRegOffset": "0x080",
358 "pr1_edio_data_out6",
359 "pr1_pru1_pru_r30_12",
360 "pr1_pru1_pru_r31_12",
370 "muxRegOffset": "0x014",
388 "muxRegOffset": "0x010",
406 "muxRegOffset": "0x004",
424 "muxRegOffset": "0x000",
442 "muxRegOffset": "0x07c",
460 "muxRegOffset": "0x0e0",
466 "pr1_edio_data_out2",
467 "pr1_pru1_pru_r30_8",
468 "pr1_pru1_pru_r31_8",
478 "muxRegOffset": "0x0e8",
484 "pr1_edio_data_out4",
485 "pr1_pru1_pru_r30_10",
486 "pr1_pru1_pru_r31_10",
496 "muxRegOffset": "0x0e4",
502 "pr1_edio_data_out3",
503 "pr1_pru1_pru_r30_9",
504 "pr1_pru1_pru_r31_9",
511 "mux": "lcd_ac_bias_en",
514 "muxRegOffset": "0x0ec",
520 "pr1_edio_data_out5",
521 "pr1_pru1_pru_r30_11",
522 "pr1_pru1_pru_r31_11",
527 "name": "UART5_CTSN",
532 "muxRegOffset": "0x0d8",
545 "name": "UART5_RTSN",
550 "muxRegOffset": "0x0dc",
563 "name": "UART4_RTSN",
568 "muxRegOffset": "0x0d4",
581 "name": "UART3_RTSN",
587 "path": "ehrpwm.1:1",
591 "muxRegOffset": "0x0cc",
604 "name": "UART4_CTSN",
609 "muxRegOffset": "0x0d0",
622 "name": "UART3_CTSN",
628 "path": "ehrpwm.1:0",
632 "muxRegOffset": "0x0c8",
650 "muxRegOffset": "0x0c0",
668 "muxRegOffset": "0x0c4",
686 "muxRegOffset": "0x0b8",
692 "pr1_edio_data_out6",
693 "pr1_pru1_pru_r30_6",
694 "pr1_pru1_pru_r31_6",
704 "muxRegOffset": "0x0bc",
710 "pr1_pru1_pru_r30_7",
711 "pr1_pru_pru1_r30_7",
712 "pr1_pru1_pru_r31_7",
722 "muxRegOffset": "0x0b0",
729 "pr1_pru1_pru_r30_4",
730 "pr1_pru1_pru_r31_4",
740 "muxRegOffset": "0x0b4",
747 "pr1_pru1_pru_r30_5",
748 "pr1_pru1_pru_r31_5",
758 "muxRegOffset": "0x0a8",
763 "ehrpwm2_tripzone_input",
765 "pr1_pru1_pru_r30_2",
766 "pr1_pru1_pru_r31_2",
776 "muxRegOffset": "0x0ac",
783 "pr1_pru1_pru_r30_3",
784 "pr1_pru1_pru_r31_3",
795 "path": "ehrpwm.2:0",
799 "muxRegOffset": "0x0a0",
806 "pr1_pru1_pru_r30_0",
807 "pr1_pru1_pru_r31_0",
818 "path": "ehrpwm.2:1",
822 "muxRegOffset": "0x0a4",
829 "pr1_pru1_pru_r30_1",
830 "pr1_pru1_pru_r31_1",
871 "name": "SYS_RESETn",
880 "muxRegOffset": "0x070",
898 "muxRegOffset": "0x078",
916 "muxRegOffset": "0x074",
935 "path": "ehrpwm.1:0",
939 "muxRegOffset": "0x048",
957 "muxRegOffset": "0x134",
976 "path": "ehrpwm.1:1",
980 "muxRegOffset": "0x04c",
998 "muxRegOffset": "0x15c",
1016 "muxRegOffset": "0x158",
1031 "mux": "uart1_rtsn",
1034 "muxRegOffset": "0x17c",
1049 "mux": "uart1_ctsn",
1052 "muxRegOffset": "0x178",
1065 "name": "UART2_TXD",
1071 "path": "ehrpwm.0:1",
1075 "muxRegOffset": "0x154",
1088 "name": "UART2_RXD",
1094 "path": "ehrpwm.0:0",
1098 "muxRegOffset": "0x150",
1116 "muxRegOffset": "0x044",
1129 "name": "UART1_TXD",
1134 "muxRegOffset": "0x184",
1141 "pr1_uart0_txd_mux1",
1149 "mux": "mcasp0_ahclkx",
1152 "muxRegOffset": "0x1ac",
1165 "name": "UART1_RXD",
1170 "muxRegOffset": "0x180",
1177 "pr1_uart0_rxd_mux1",
1185 "mux": "mcasp0_fsr",
1188 "muxRegOffset": "0x1a4",
1195 "pr1_pru0_pru_r30_5",
1203 "mux": "mcasp0_ahclkr",
1211 "muxRegOffset": "0x19c",
1226 "mux": "mcasp0_fsx",
1230 "path": "ehrpwm.0:1",
1234 "muxRegOffset": "0x194",
1249 "mux": "mcasp0_axr0",
1252 "muxRegOffset": "0x198",
1265 "name": "SPI1_SCLK",
1267 "mux": "mcasp0_aclkx",
1271 "path": "ehrpwm.0:0",
1275 "muxRegOffset": "0x190",
1347 "mux": "xdma_event_intr1",
1350 "muxRegOffset": "0x1b4",
1365 "mux": "ecap0_in_pwm0_out",
1373 "muxRegOffset": "0x164",
1375 "ecap0_in_pwm0_out",
1378 "pr1_ecap0_ecap_capin_apwm_o",
1407 "muxRegOffset": "0x054",
1425 "muxRegOffset": "0x058",
1443 "muxRegOffset": "0x05c",
1461 "muxRegOffset": "0x060",