linux-ac100/armdma.patch

   1 diff -urN linux-3.1-rc4-a/arch/arm/include/asm/dma-mapping.h linux-3.1-rc4-b/arch/arm/include/asm/dma-mapping.h
   2 --- linux-3.1-rc4-a/arch/arm/include/asm/dma-mapping.h  2011-08-29 05:16:01.000000000 +0100
   3 +++ linux-3.1-rc4-b/arch/arm/include/asm/dma-mapping.h  2011-09-02 12:09:00.000000000 +0100
   4 @@ -205,6 +205,15 @@
   5  int dma_mmap_writecombine(struct device *, struct vm_area_struct *,
   6                 void *, dma_addr_t, size_t);
   7
   8 +#ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
   9 +#define ARCH_HAS_DMA_COHERENT_WRITE_SYNC
  10 +
  11 +static inline void dma_coherent_write_sync(void)
  12 +{
  13 +       dsb();
  14 +       outer_sync();
  15 +}
  16 +#endif
  17
  18  #ifdef CONFIG_DMABOUNCE
  19  /*
  20 diff -urN linux-3.1-rc4-a/Documentation/DMA-API-HOWTO.txt linux-3.1-rc4-b/Documentation/DMA-API-HOWTO.txt
  21 --- linux-3.1-rc4-a/Documentation/DMA-API-HOWTO.txt     2011-08-29 05:16:01.000000000 +0100
  22 +++ linux-3.1-rc4-b/Documentation/DMA-API-HOWTO.txt     2011-09-02 12:01:09.000000000 +0100
  23 @@ -400,6 +400,22 @@
  24  from a pool before you destroy the pool. This function may not
  25  be called in interrupt context.
  26
  27 +Some architectures which supporting DMA coherent memory may still have write
  28 +buffering between the CPU and DMA memory. This buffering may delay CPU writes
  29 +from reaching coherent memory in a timely manner. These delays in turn can
  30 +lead lead to dramatic performance issues in certain cases. An architecture
  31 +may mitigate this problem to a large degree by having a write buffer flush
  32 +implicit in the MMIO functions used to write to device registers. This works
  33 +for the most common cases where a driver needs to write to a register to tell
  34 +a device that something was written to the shared coherent memory. There are
  35 +other cases where the device polls the dma-coherent memory for data written
  36 +by the driver. In such cases, the driver needs to explicity force write buffer
  37 +data to memory by calling:
  38 +
  39 +       dma_coherent_write_sync();
  40 +
  41 +
  42 +
  43                         DMA Direction
  44
  45  The interfaces described in subsequent portions of this document
  46 diff -urN linux-3.1-rc4-a/Documentation/DMA-API.txt linux-3.1-rc4-b/Documentation/DMA-API.txt
  47 --- linux-3.1-rc4-a/Documentation/DMA-API.txt   2011-08-29 05:16:01.000000000 +0100
  48 +++ linux-3.1-rc4-b/Documentation/DMA-API.txt   2011-09-02 12:03:06.000000000 +0100
  49 @@ -418,6 +418,18 @@
  50         ....
  51
  52
  53 +Part Ie - Write buffering to dma-coherent memory
  54 +------------------------------------------------
  55 +
  56 +Some architectures supporting DMA coherent memory may have write
  57 +buffering between the CPU and DMA memory. This buffering may delay
  58 +CPU writes from reaching coherent memory in a timely manner.
  59 +
  60 +    void
  61 +    dma_coherent_write_sync()
  62 +
  63 +Force any outstanding coherent writes to memory.
  64 +
  65  Part II - Advanced dma_ usage
  66  -----------------------------
  67
  68 diff -urN linux-3.1-rc4-a/drivers/usb/host/ehci-q.c linux-3.1-rc4-b/drivers/usb/host/ehci-q.c
  69 --- linux-3.1-rc4-a/drivers/usb/host/ehci-q.c   2011-08-29 05:16:01.000000000 +0100
  70 +++ linux-3.1-rc4-b/drivers/usb/host/ehci-q.c   2011-09-02 12:17:20.000000000 +0100
  71 @@ -114,6 +114,7 @@
  72         /* HC must see latest qtd and qh data before we clear ACTIVE+HALT */
  73         wmb ();
  74         hw->hw_token &= cpu_to_hc32(ehci, QTD_TOGGLE | QTD_STS_PING);
  75 +       dma_coherent_write_sync();
  76  }
  77
  78  /* if it weren't for a common silicon quirk (writing the dummy into the qh
  79 @@ -404,6 +405,7 @@
  80                                         wmb();
  81                                         hw->hw_token = cpu_to_hc32(ehci,
  82                                                         token);
  83 +                                       dma_coherent_write_sync();
  84                                         goto retry_xacterr;
  85                                 }
  86                                 stopped = 1;
  87 @@ -753,8 +755,10 @@
  88         }
  89
  90         /* by default, enable interrupt on urb completion */
  91 -       if (likely (!(urb->transfer_flags & URB_NO_INTERRUPT)))
  92 +       if (likely(!(urb->transfer_flags & URB_NO_INTERRUPT))) {
  93                 qtd->hw_token |= cpu_to_hc32(ehci, QTD_IOC);
  94 +               dma_coherent_write_sync();
  95 +       }
  96         return head;
  97
  98  cleanup:
  99 @@ -1081,6 +1085,7 @@
 100                         /* let the hc process these next qtds */
 101                         wmb ();
 102                         dummy->hw_token = token;
 103 +                       dma_coherent_write_sync();
 104
 105                         urb->hcpriv = qh_get (qh);
 106                 }
 107 diff -urN linux-3.1-rc4-a/include/linux/dma-mapping.h linux-3.1-rc4-b/include/linux/dma-mapping.h
 108 --- linux-3.1-rc4-a/include/linux/dma-mapping.h 2011-08-29 05:16:01.000000000 +0100
 109 +++ linux-3.1-rc4-b/include/linux/dma-mapping.h 2011-09-02 12:06:06.000000000 +0100
 110 @@ -154,6 +154,12 @@
 111  }
 112  #endif
 113
 114 +#ifndef ARCH_HAS_DMA_COHERENT_WRITE_SYNC
 115 +static inline void dma_coherent_write_sync(void)
 116 +{
 117 +}
 118 +#endif
 119 +
 120  /*
 121   * Managed DMA API
 122   */