From c7d1f5dff967bf063801d808da8d2bdc10cfe52e Mon Sep 17 00:00:00 2001 From: Nedko Arnaudov Date: Sun, 1 Jul 2018 18:18:03 +0300 Subject: [PATCH] esp-idf-bootloader-support: Disable some cpu frequency smart logic (and risk deadlock on esp-32 silicon rev0) bootloader_support fails to build --- components/bootloader_support/src/bootloader_clock.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/components/bootloader_support/src/bootloader_clock.c b/components/bootloader_support/src/bootloader_clock.c index 2937210..895e113 100644 --- a/components/bootloader_support/src/bootloader_clock.c +++ b/components/bootloader_support/src/bootloader_clock.c @@ -1,4 +1,5 @@ // Copyright 2017 Espressif Systems (Shanghai) PTE LTD +// Copyright 2018 apeos contributors // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -31,6 +32,7 @@ void bootloader_clock_configure() /* Set CPU to 80MHz. Keep other clocks unmodified. */ rtc_cpu_freq_t cpu_freq = RTC_CPU_FREQ_80M; +#if !defined(ESP_IDF_APEOS_BUILD) /* On ESP32 rev 0, switching to 80MHz if clock was previously set to * 240 MHz may cause the chip to lock up (see section 3.5 of the errata * document). For rev. 0, switch to 240 instead if it was chosen in @@ -41,6 +43,7 @@ void bootloader_clock_configure() CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ == 240) { cpu_freq = RTC_CPU_FREQ_240M; } +#endif rtc_clk_config_t clk_cfg = RTC_CLK_CONFIG_DEFAULT(); clk_cfg.xtal_freq = CONFIG_ESP32_XTAL_FREQ; -- 2.11.4.GIT