From f83341325dda968f3615152e190f00c9e7fe31c7 Mon Sep 17 00:00:00 2001 From: NicJA Date: Thu, 7 May 2015 00:25:55 +0000 Subject: [PATCH] add kernel_ipi to the build and call it from the bcm2708 support code if applicable. git-svn-id: https://svn.aros.org/svn/aros/trunk/AROS@50609 fb15a70f-31f2-0310-bbcc-cdcc74a49acc --- arch/arm-native/kernel/mmakefile.src | 1 + arch/arm-native/kernel/platform_bcm2708.c | 72 +++++++++++++------------------ 2 files changed, 31 insertions(+), 42 deletions(-) diff --git a/arch/arm-native/kernel/mmakefile.src b/arch/arm-native/kernel/mmakefile.src index 389235c725..a4bc23196c 100644 --- a/arch/arm-native/kernel/mmakefile.src +++ b/arch/arm-native/kernel/mmakefile.src @@ -5,6 +5,7 @@ CFILES := \ kernel_startup \ kernel_execsmp \ kernel_cpu \ + kernel_ipi \ kernel_scheduler \ spininit \ spinislocked \ diff --git a/arch/arm-native/kernel/platform_bcm2708.c b/arch/arm-native/kernel/platform_bcm2708.c index f8bff06705..94d31e43d4 100644 --- a/arch/arm-native/kernel/platform_bcm2708.c +++ b/arch/arm-native/kernel/platform_bcm2708.c @@ -47,7 +47,10 @@ extern uint32_t mpcore_pde; extern spinlock_t startup_lock; extern void cpu_Register(void); -extern void arm_flush_cache(uint32_t addr, uint32_t length); +extern void arm_flush_cache(uint32_t, uint32_t); +#if defined(__AROSEXEC_SMP__) +extern void handle_ipi(uint32_t); +#endif static void bcm2708_init(APTR _kernelBase, APTR _sysBase) { @@ -83,57 +86,39 @@ static void bcm2708_init(APTR _kernelBase, APTR _sysBase) for (core = 1; core < 4; core ++) { - core_stack = (uint32_t *)AllocMem(AROS_STACKSIZE*sizeof(uint32_t), MEMF_CLEAR); /* MEMF_PRIVATE */ - ((uint32_t *)(trampoline_dst + trampoline_data_offset))[2] = (uint32_t)&core_stack[AROS_STACKSIZE-sizeof(IPTR)]; + core_stack = (uint32_t *)AllocMem(AROS_STACKSIZE*sizeof(uint32_t), MEMF_CLEAR); /* MEMF_PRIVATE */ + ((uint32_t *)(trampoline_dst + trampoline_data_offset))[2] = (uint32_t)&core_stack[AROS_STACKSIZE-sizeof(IPTR)]; - core_fiq_stack = (uint32_t *)AllocMem(1024*sizeof(uint32_t), MEMF_CLEAR); /* MEMF_PRIVATE */ - ((uint32_t *)(trampoline_dst + trampoline_data_offset))[4] = (uint32_t)&core_fiq_stack[1024-sizeof(IPTR)]; + core_fiq_stack = (uint32_t *)AllocMem(1024*sizeof(uint32_t), MEMF_CLEAR); /* MEMF_PRIVATE */ + ((uint32_t *)(trampoline_dst + trampoline_data_offset))[4] = (uint32_t)&core_fiq_stack[1024-sizeof(IPTR)]; - __tls = AllocMem(sizeof(tls_t), MEMF_CLEAR); /* MEMF_PRIVATE */ - __tls->SysBase = _sysBase; - __tls->KernelBase = _kernelBase; - __tls->ThisTask = NULL; - arm_flush_cache(((uint32_t)__tls) & ~63, 512); - ((uint32_t *)(trampoline_dst + trampoline_data_offset))[3] = __tls; + __tls = AllocMem(sizeof(tls_t), MEMF_CLEAR); /* MEMF_PRIVATE */ + __tls->SysBase = _sysBase; + __tls->KernelBase = _kernelBase; + __tls->ThisTask = NULL; + arm_flush_cache(((uint32_t)__tls) & ~63, 512); + ((uint32_t *)(trampoline_dst + trampoline_data_offset))[3] = __tls; - D(bug("[KRN:BCM2708] %s: Attempting to wake core #%d\n", __PRETTY_FUNCTION__, core)); - D(bug("[KRN:BCM2708] %s: core #%d stack @ 0x%p (sp=0x%p)\n", __PRETTY_FUNCTION__, core, core_stack, ((uint32_t *)(trampoline_dst + trampoline_data_offset))[2])); - D(bug("[KRN:BCM2708] %s: core #%d fiq stack @ 0x%p (sp=0x%p)\n", __PRETTY_FUNCTION__, core, core_fiq_stack, ((uint32_t *)(trampoline_dst + trampoline_data_offset))[4])); - D(bug("[KRN:BCM2708] %s: core #%d tls @ 0x%p\n", __PRETTY_FUNCTION__, core, ((uint32_t *)(trampoline_dst + trampoline_data_offset))[3])); + D(bug("[KRN:BCM2708] %s: Attempting to wake core #%d\n", __PRETTY_FUNCTION__, core)); + D(bug("[KRN:BCM2708] %s: core #%d stack @ 0x%p (sp=0x%p)\n", __PRETTY_FUNCTION__, core, core_stack, ((uint32_t *)(trampoline_dst + trampoline_data_offset))[2])); + D(bug("[KRN:BCM2708] %s: core #%d fiq stack @ 0x%p (sp=0x%p)\n", __PRETTY_FUNCTION__, core, core_fiq_stack, ((uint32_t *)(trampoline_dst + trampoline_data_offset))[4])); + D(bug("[KRN:BCM2708] %s: core #%d tls @ 0x%p\n", __PRETTY_FUNCTION__, core, ((uint32_t *)(trampoline_dst + trampoline_data_offset))[3])); - arm_flush_cache((uint32_t)trampoline_dst, 512); + arm_flush_cache((uint32_t)trampoline_dst, 512); - /* Lock the startup spinlock */ - KrnSpinLock(&startup_lock, SPINLOCK_MODE_WRITE); + /* Lock the startup spinlock */ + KrnSpinLock(&startup_lock, SPINLOCK_MODE_WRITE); - /* Wake up the core */ - *((uint32_t *)(BCM2836_MAILBOX3_SET0 + (0x10 * core))) = (uint32_t)trampoline_dst; + /* Wake up the core */ + *((uint32_t *)(BCM2836_MAILBOX3_SET0 + (0x10 * core))) = (uint32_t)trampoline_dst; - /* + /* * Try to obtain spinlock again. * This should put this core to sleep since the locked was already obtained. Once the core startup * is ready, it will call KrnSpinUnLock too */ KrnSpinLock(&startup_lock, SPINLOCK_MODE_WRITE); KrnSpinUnLock(&startup_lock); - -#if 0 - if (__arm_arosintern.ARMI_Delay) - __arm_arosintern.ARMI_Delay(30000000); - - /* - * Just for fun try to fire FIQ interrupts on new cores - */ - int iii; - - for (iii = 0; iii < 4; iii++) - { - *((uint32_t *)(BCM2836_MAILBOX0_SET0 + iii*4 + (0x10 * core))) = 0xdead0000 + (core << 8) + iii; - - if (__arm_arosintern.ARMI_Delay) - __arm_arosintern.ARMI_Delay(30000000); - } -#endif } } } @@ -270,7 +255,7 @@ static void bcm2807_irq_process() static void bcm2807_fiq_process() { - uint32_t tmp, fiq, reason; + uint32_t tmp, fiq, fiq_data; int i; asm volatile (" mrc p15, 0, %0, c0, c0, 5 " : "=r" (tmp)); @@ -287,8 +272,11 @@ static void bcm2807_fiq_process() { if (fiq & (0x10 << i)) { - reason = *((uint32_t *)(BCM2836_MAILBOX0_CLR0 + 4*i + (16 * (tmp & 0x3)))); - DFIQ(bug("[KRN:BCM2708] %s: Mailbox%d: %08x\n", __PRETTY_FUNCTION__, i, reason)); + fiq_data = *((uint32_t *)(BCM2836_MAILBOX0_CLR0 + 4*i + (16 * (tmp & 0x3)))); + DFIQ(bug("[KRN:BCM2708] %s: Mailbox%d: FIQ Data %08x\n", __PRETTY_FUNCTION__, i, fiq_data)); +#if defined(__AROSEXEC_SMP__) + handle_ipi(fiq_data); +#endif *((uint32_t *)(BCM2836_MAILBOX0_CLR0 + 4*i + (16 * (tmp & 0x3)))) = 0xffffffff; } } -- 2.11.4.GIT