From bbb84faad29399e23ef235b33c4cc4081decc7ab Mon Sep 17 00:00:00 2001
From: NicJA <NicJA@fb15a70f-31f2-0310-bbcc-cdcc74a49acc>
Date: Thu, 31 Mar 2016 01:45:13 +0000
Subject: [PATCH] add the first parts of aarch64's cpucontext.h

git-svn-id: https://svn.aros.org/svn/aros/trunk/AROS@52461 fb15a70f-31f2-0310-bbcc-cdcc74a49acc
---
 arch/aarch64-all/include/aros/cpucontext.h | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)
 create mode 100644 arch/aarch64-all/include/aros/cpucontext.h

diff --git a/arch/aarch64-all/include/aros/cpucontext.h b/arch/aarch64-all/include/aros/cpucontext.h
new file mode 100644
index 0000000000..1dc6325ed3
--- /dev/null
+++ b/arch/aarch64-all/include/aros/cpucontext.h
@@ -0,0 +1,26 @@
+#ifndef AROS_AARCH64_CPUCONTEXT_H
+#define AROS_AARCH64_CPUCONTEXT_H
+
+/*
+    Copyright © 2016, The AROS Development Team. All rights reserved.
+    $Id$
+
+    Desc: CPU context definition for ARM AArch64 processors
+    Lang: english
+*/
+
+struct ExceptionContext
+{
+    IPTR r[29]; /* General purpose registers	*/
+    IPTR fp;	/*  x30    			*/
+    IPTR sp;	/*      			*/
+    IPTR pc;	/*      			*/
+};
+
+/* VFP context */
+struct VFPContext
+{
+    IPTR fpr[64];
+};
+
+#endif
-- 
2.11.4.GIT