From ae9212f87c1c0df642a11edf4d1d8817bf35af20 Mon Sep 17 00:00:00 2001 From: NicJA Date: Mon, 13 Apr 2015 21:01:05 +0000 Subject: [PATCH] re-order exceptioncontext so registers match order in exception handlers git-svn-id: https://svn.aros.org/svn/aros/trunk/AROS@50365 fb15a70f-31f2-0310-bbcc-cdcc74a49acc --- arch/arm-all/include/aros/cpucontext.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm-all/include/aros/cpucontext.h b/arch/arm-all/include/aros/cpucontext.h index ec01952d79..db140bfe60 100644 --- a/arch/arm-all/include/aros/cpucontext.h +++ b/arch/arm-all/include/aros/cpucontext.h @@ -11,15 +11,15 @@ struct ExceptionContext { - UWORD Flags; /* Currently reserved */ - UBYTE FPUType; /* FPU type (see below) */ - UBYTE Reserved; /* Unused */ ULONG r[12]; /* General purpose registers */ ULONG ip; /* r12 */ ULONG sp; /* r13 */ ULONG lr; /* r14 */ ULONG pc; /* r15 */ ULONG cpsr; + UWORD Flags; /* Currently reserved */ + UBYTE FPUType; /* FPU type (see below) */ + UBYTE Reserved; /* Unused */ APTR fpuContext; /* Pointer to FPU context area */ }; -- 2.11.4.GIT