From a8d0cdecc976342e02c140bea598e3351ef12e42 Mon Sep 17 00:00:00 2001 From: DizzyOfCRN Date: Mon, 18 Aug 2014 13:37:02 +0000 Subject: [PATCH] We dont seem to be able to trigger our own interrupt yeat, but SATA controller triggers same int as is for one of the USB3.0 controllers. Port register shows a change and that is nice... git-svn-id: https://svn.aros.org/svn/aros/trunk/AROS@49477 fb15a70f-31f2-0310-bbcc-cdcc74a49acc --- rom/usb/pciusbhc/xhci/pcixhci_controller.c | 27 +++++++++++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) diff --git a/rom/usb/pciusbhc/xhci/pcixhci_controller.c b/rom/usb/pciusbhc/xhci/pcixhci_controller.c index da75402717..e72740b3b0 100644 --- a/rom/usb/pciusbhc/xhci/pcixhci_controller.c +++ b/rom/usb/pciusbhc/xhci/pcixhci_controller.c @@ -44,8 +44,29 @@ static AROS_INTH1(PCIXHCI_IntCode, struct PCIXHCIUnit *, unit) { AROS_INTFUNC_INIT - mybug_unit(-1, ("Excuse me...\n")); + struct PCIXHCIPort *port = NULL; + + ULONG usbsts; + + if((opreg_readl(XHCI_USBCMD) & XHCF_CMD_INTE)) { + + usbsts = opreg_readl(XHCI_USBSTS); + if((usbsts & XHCF_STS_PCD)) { + mybug_unit(-1, ("Excuse me... Port status change has occured\n")); + opreg_writel(XHCI_USBSTS, XHCF_STS_PCD); + + if(unit->state == UHSF_OPERATIONAL) { + mybug_unit(-1,("Interrupt occured while controller is operational\n")); + } else { + mybug_unit(-1,("Interrupt occured while controller is not operational\n")); + } + + ForeachNode(&unit->roothub.port_list, port) { + mybug_unit(-1,("port %d XHCI_PORTSC(%08x)\n", port->number, opreg_readl(XHCI_PORTSC(port->number)))); + } + } + } return 0; AROS_INTFUNC_EXIT } @@ -137,7 +158,6 @@ BOOL PCIXHCI_HCInit(struct PCIXHCIUnit *unit) { unit->hc.inthandler.is_Node.ln_Type = NT_INTERRUPT; unit->hc.inthandler.is_Code = (VOID_FUNC)PCIXHCI_IntCode; unit->hc.inthandler.is_Data = unit; - HIDD_PCIDevice_AddInterrupt(unit->hc.pcidevice, &unit->hc.inthandler); return TRUE; @@ -198,6 +218,9 @@ BOOL PCIXHCI_HCReset(struct PCIXHCIUnit *unit) { } mybug(-1,("\n")); + /* Enable host controller to issue interrupts */ + opreg_writel(XHCI_USBCMD, (opreg_readl(XHCI_USBCMD) | XHCF_CMD_INTE)); + return TRUE; } -- 2.11.4.GIT