From 824060990fedb93426313e0b958842271ba0b33b Mon Sep 17 00:00:00 2001
From: NicJA <NicJA@fb15a70f-31f2-0310-bbcc-cdcc74a49acc>
Date: Tue, 12 Mar 2013 19:00:46 +0000
Subject: [PATCH] add a few more feature flags, and try to probe the arm cpu
 version

git-svn-id: https://svn.aros.org/svn/aros/trunk/AROS@46904 fb15a70f-31f2-0310-bbcc-cdcc74a49acc
---
 arch/arm-raspi/processor/processor_arch_intern.h | 11 ++++++--
 arch/arm-raspi/processor/processor_util.c        | 36 ++++++++++++++++++++++--
 2 files changed, 42 insertions(+), 5 deletions(-)

diff --git a/arch/arm-raspi/processor/processor_arch_intern.h b/arch/arm-raspi/processor/processor_arch_intern.h
index 1c58b70a64..8ca6b9c16b 100644
--- a/arch/arm-raspi/processor/processor_arch_intern.h
+++ b/arch/arm-raspi/processor/processor_arch_intern.h
@@ -35,9 +35,14 @@ VOID ReadMaxFrequencyInformation(struct ARMProcessorInformation * info);
 UQUAD GetCurrentProcessorFrequency(struct ARMProcessorInformation * info);
 
 /* Flags */
-#define FEATB_FPU   0
-
-#define FEATF_FPU   (1 << FEATB_FPU)
 
+#define FEATB_FPU       0
+#define FEATF_FPU       (1 << FEATB_FPU)
+#define FEATB_FPU_VFP   FEATB_FPU
+#define FEATF_FPU_VFP   (1 << FEATB_FPU_VFP)
+#define FEATB_FPU_VFP3  1
+#define FEATF_FPU_VFP3  (1 << FEATB_FPU_VFP3)
+#define FEATB_NEON      2
+#define FEATF_NEON      (1 << FEATB_NEON)
 
 #endif /* PROCESSOR_ARCH_INTERN_H */
diff --git a/arch/arm-raspi/processor/processor_util.c b/arch/arm-raspi/processor/processor_util.c
index da0265b5bc..108a3ebc7e 100644
--- a/arch/arm-raspi/processor/processor_util.c
+++ b/arch/arm-raspi/processor/processor_util.c
@@ -36,13 +36,45 @@ VOID ReadProcessorInformation(struct ARMProcessorInformation * info)
 
     D(bug("[processor.ARM] %s: Probing CPU ..\n", __PRETTY_FUNCTION__));
 
+    /* Read Processor MainID Register */
     asm volatile("mrc p15, 0, %[scp_reg], c0, c0, 0" : [scp_reg] "=r" (scp_reg) );
 
     info->Vendor = (scp_reg >> 24) & 0x7F;
-    info->Family = (scp_reg >> 16) & 0xF;
 
+    if ((scp_reg & 0x8F000) == 0)
+        info->Family = CPUFAMILY_UNKNOWN;
+    else if ((scp_reg & 0x8F000) == 0x7000)
+        info->Family = (scp_reg & (1 << 23)) ? CPUFAMILY_ARM_4T : CPUFAMILY_ARM_3;
+    else if ((scp_reg & 0x80000) == 0)
+    {
+        info->Family = CPUFAMILY_ARM_3;
+        if ((scp_reg >> 16) & 7)
+            info->Family += ((scp_reg >> 16) & 7);
+    }
+    else if ((scp_reg & 0xF0000) == 0xF0000)
+    {
+        /* /* Read Processor Memory Model Feature Register */
+        asm volatile("mrc p15, 0, %[scp_reg], c0, c1, 4" : [scp_reg] "=r" (scp_reg) );
+        if ((scp_reg & 0xF) >= 3 || ((scp_reg >> 8) & 0xF) >= 3)
+            info->Family = CPUFAMILY_ARM_7;
+        else if ((scp_reg & 0xF) == 2 || ((scp_reg >> 8) & 0xF) == 2)
+            info->Family = CPUFAMILY_ARM_6;
+        else
+            info->Family = CPUFAMILY_UNKNOWN;
+    } else
+        info->Family = CPUFAMILY_UNKNOWN;
+
+#if (0)
+    /* Read Processor Feature Register 1 */
+    asm volatile("mrc p15, 0, %[scp_reg], c0, c1, 1" : [scp_reg] "=r" (scp_reg) );
+
+    /* Read Processor Feature Register 0 */
+    asm volatile("mrc p15, 0, %[scp_reg], c0, c1, 1" : [scp_reg] "=r" (scp_reg) );
+#endif
+
+    /* Read Processor Cache Type Register */
     asm volatile("mrc p15, 0, %[scp_reg], c0, c0, 1" : [scp_reg] "=r" (scp_reg) );
-
+    
     switch((scp_reg >> 18) & 0xF) {
         case 3:
             info->L1DataCacheSize = 4096;
-- 
2.11.4.GIT