| commit | 504295e19dfe1e0ae03ab977008626e8e3f48ee6 | |
| author | DizzyOfCRN <DizzyOfCRN@fb15a70f-31f2-0310-bbcc-cdcc74a49acc> | |
| Mon, 10 Nov 2014 09:08:51 +0000 (10 09:08 +0000) | ||
| committer | DizzyOfCRN <DizzyOfCRN@fb15a70f-31f2-0310-bbcc-cdcc74a49acc> | |
| Mon, 10 Nov 2014 09:08:51 +0000 (10 09:08 +0000) | ||
| tree | 33038b07ba5daf83683e24801540e4ed6dc1b537 | treesnapshot (tar.gz zip) |
| parent | 9859e8daa1e09b435da9c401cacd9fa5847f98cf | commitdiff |
Fix PLL5_CFG setup. (hardcoded)
Arm NEON (Testing DRAM with some NEON code, not committed)
Compute refresh timings from DRAM_CLK, no more hardcoded define.
Now DDR3 seems to actually retain content and work. (for 408MHz at least), needs CAS/CL automatic setup for different timing values.
git-svn-id: https://svn.aros.org/svn/aros/trunk/AROS@49781 fb15a70f-31f2-0310-bbcc-cdcc74a49acc
Arm NEON (Testing DRAM with some NEON code, not committed)
Compute refresh timings from DRAM_CLK, no more hardcoded define.
Now DDR3 seems to actually retain content and work. (for 408MHz at least), needs CAS/CL automatic setup for different timing values.
git-svn-id: https://svn.aros.org/svn/aros/trunk/AROS@49781 fb15a70f-31f2-0310-bbcc-cdcc74a49acc
| arch/arm-sun4i/bootstrap/bootstrap.c | diffblobblamehistory |