| commit | 18b6df7c5fe6fa5c4a2c878180a05a3f117734c7 | |
| author | DizzyOfCRN <DizzyOfCRN@fb15a70f-31f2-0310-bbcc-cdcc74a49acc> | |
| Thu, 11 Sep 2014 06:19:04 +0000 (11 06:19 +0000) | ||
| committer | DizzyOfCRN <DizzyOfCRN@fb15a70f-31f2-0310-bbcc-cdcc74a49acc> | |
| Thu, 11 Sep 2014 06:19:04 +0000 (11 06:19 +0000) | ||
| tree | efbbd332afd132f7b5d0d22732209e2d51cd0ff7 | treesnapshot (tar.gz zip) |
| parent | 0124e3a02c1cf218b92c8aebcd6bc73ccf0aec75 | commitdiff |
Lessen debug
Delete pcixhci_pcie.c
Move auxiliary functions to pcixhci_misc.c, will house memory allocation functions also.
- Maybe steal them from Jason's AHCI (slab allocator).
Port change interrupts are expected when DCBAA gets setup correctly.
Quad address write of DCBAA seems to work ok on 32-bit Aros (operational_writeq())
Show full port name when debugging port interrupt change,
- eg. PCIXHCI[03:00.0] USB 3.0 port 1 or PCIXHCI[03:00.0] USB 2.0 port 3, which is nice.
git-svn-id: https://svn.aros.org/svn/aros/trunk/AROS@49610 fb15a70f-31f2-0310-bbcc-cdcc74a49acc
Delete pcixhci_pcie.c
Move auxiliary functions to pcixhci_misc.c, will house memory allocation functions also.
- Maybe steal them from Jason's AHCI (slab allocator).
Port change interrupts are expected when DCBAA gets setup correctly.
Quad address write of DCBAA seems to work ok on 32-bit Aros (operational_writeq())
Show full port name when debugging port interrupt change,
- eg. PCIXHCI[03:00.0] USB 3.0 port 1 or PCIXHCI[03:00.0] USB 2.0 port 3, which is nice.
git-svn-id: https://svn.aros.org/svn/aros/trunk/AROS@49610 fb15a70f-31f2-0310-bbcc-cdcc74a49acc