re-order exceptioncontext so registers match order in exception handlers
[AROS.git] / arch / arm-all / include / aros / cpucontext.h
blobdb140bfe60aa5ee439538c6ed3d23b0893477ad5
1 #ifndef AROS_ARM_CPUCONTEXT_H
2 #define AROS_ARM_CPUCONTEXT_H
4 /*
5 Copyright © 1995-2010, The AROS Development Team. All rights reserved.
6 $Id$
8 Desc: CPU context definition for ARM processors
9 Lang: english
12 struct ExceptionContext
14 ULONG r[12]; /* General purpose registers */
15 ULONG ip; /* r12 */
16 ULONG sp; /* r13 */
17 ULONG lr; /* r14 */
18 ULONG pc; /* r15 */
19 ULONG cpsr;
20 UWORD Flags; /* Currently reserved */
21 UBYTE FPUType; /* FPU type (see below) */
22 UBYTE Reserved; /* Unused */
23 APTR fpuContext; /* Pointer to FPU context area */
26 /* CPU modes */
27 #define CPUMODE_USER 0x10
28 #define CPUMODE_FIQ 0x11
29 #define CPUMODE_IRQ 0x12
30 #define CPUMODE_SUPERVISOR 0x13
31 #define CPUMODE_ABORT 0x17
32 #define CPUMODE_UNDEF 0x1B
33 #define CPUMODE_SYSTEM 0x1F
35 #define CPUMODE_MASK 0x1F
37 #define CPUMODE_IRQENABLED (1 << 7)
39 /* Flags */
40 enum enECFlags
42 ECF_FPU = 1<<0 /* FPU data is present */
45 /* FPU types */
46 #define FPU_NONE 0
47 #define FPU_AFP 1
48 #define FPU_VFP 2
50 /* VFP context */
51 struct VFPContext
53 ULONG fpr[64];
54 ULONG fpscr;
57 #endif