| commit | e61df589a843d28483c6d94a9d7c0b3517e6e832 | |
| author | Ranjani Vaidyanathan <ra5478@freescale.com> | |
| Fri, 24 Aug 2012 03:57:50 +0000 (23 22:57 -0500) | ||
| committer | Xinyu Chen <xinyu.chen@freescale.com> | |
| Fri, 24 Aug 2012 05:37:17 +0000 (24 13:37 +0800) | ||
| tree | bcf70d3916244e090dbca003b4f43db3c2403a24 | treesnapshot (tar.gz zip) |
| parent | ac8f43ae39627e6ddb2072521fc8b6014c48e7cd | commitdiff |
ENGR00221277 MX6DL/S - Set AXI clock to 270MHz
Change AXI_CLK to be sourced from PLL3_PFD1_540MHz, so that it
can run at 270MHz on MX6DL/S. This is required for improving
VPU performance.
Change AXI_CLK to be sourced from periph_clk just before the DDR
freq is going to be dropped to 24MHz/50MHz. Change it back
to PLL3_PFD1_540 when the DDR freq is back at 400MHz.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
Change AXI_CLK to be sourced from PLL3_PFD1_540MHz, so that it
can run at 270MHz on MX6DL/S. This is required for improving
VPU performance.
Change AXI_CLK to be sourced from periph_clk just before the DDR
freq is going to be dropped to 24MHz/50MHz. Change it back
to PLL3_PFD1_540 when the DDR freq is back at 400MHz.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
| arch/arm/mach-mx6/bus_freq.c | diffblobblamehistory | |
| arch/arm/mach-mx6/clock.c | diffblobblamehistory |