zpu/hdl/zpuino/sram_ctrl.vhd

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4 use ieee.std_logic_unsigned.all;
   5
   6 library work;
   7 use work.zpu_config.all;
   8 use work.zpuino_config.all;
   9 use work.zpuinopkg.all;
  10 use work.zpupkg.all;
  11 use work.wishbonepkg.all;
  12
  13 entity sram_ctrl is
  14   port (
  15     wb_clk_i: in std_logic;
  16                 wb_rst_i: in std_logic;
  17
  18     wb_dat_o: out std_logic_vector(31 downto 0);
  19     wb_dat_i: in std_logic_vector(31 downto 0);
  20     wb_adr_i: in std_logic_vector(maxIOBit downto minIOBit);
  21 --    wb_sel_i: in std_logic_vector(3 downto 0);
  22     wb_cti_i: in std_logic_vector(2 downto 0);
  23     wb_we_i:  in std_logic;
  24     wb_cyc_i: in std_logic;
  25     wb_stb_i: in std_logic;
  26     wb_ack_o: out std_logic;
  27
  28     -- SRAM signals
  29     sram_addr:  out std_logic_vector(18 downto 0);
  30     sram_data:  inout std_logic_vector(15 downto 0);
  31     sram_ce:    out std_logic;
  32     sram_we:    out std_logic;
  33     sram_oe:    out std_logic;
  34     sram_be:    out std_logic
  35   );
  36 end entity sram_ctrl;
  37
  38
  39 architecture behave of sram_ctrl is
  40
  41 signal sram_data_write: std_logic_vector(15 downto 0);
  42
  43 type state_type is (
  44   idle,
  45   waitburst,
  46   operation,
  47   finish
  48 );
  49
  50 signal state: state_type;
  51 signal sram_addr_q: unsigned(18 downto 0);
  52
  53 begin
  54
  55 sram_be <= '0';
  56
  57 sram_data <= sram_data_write when wb_we_i='1' and wb_cyc_i='1' else (others => 'Z');
  58
  59 wb_dat_o(31 downto 16) <= (others => '0');
  60
  61 sram_addr <= std_logic_vector(sram_addr_q);
  62
  63 process(wb_clk_i)
  64 begin
  65   if rising_edge(wb_clk_i) then
  66     if wb_rst_i='1' then
  67       wb_ack_o <= '0';
  68       state <= idle;
  69       sram_we <= '1';
  70       sram_ce <= '1';
  71       sram_oe <= '1';
  72     else
  73
  74       wb_ack_o <= '0';
  75       case state is
  76         when idle =>
  77           if wb_cyc_i='1' and wb_stb_i='1' then
  78
  79             sram_addr_q <= unsigned(wb_adr_i(20 downto 2));
  80             sram_data_write <= wb_dat_i(15 downto 0);
  81             sram_we <= not wb_we_i;
  82             sram_oe <= wb_we_i;
  83             sram_ce <= '0';
  84
  85             if wb_we_i='1' then
  86               state <= operation;
  87             else
  88               state <= waitburst;
  89             end if;
  90           end if;
  91         when waitburst =>
  92
  93           state <= operation;
  94         when operation =>
  95           wb_ack_o<='1';
  96           wb_dat_o(15 downto 0) <= sram_data;
  97           sram_we <= '1';
  98           if wb_cti_i = CTI_CYCLE_INCRADDR then
  99             sram_addr_q <= sram_addr_q + 1;
 100             state <= waitburst;
 101           else
 102             state <= finish;
 103           end if;
 104         when finish =>
 105           state <= idle;
 106           sram_we <= '1';
 107           sram_oe <= '1';
 108           sram_ce <= '1';
 109         when others =>
 110       end case;
 111     end if;
 112   end if;
 113 end process;
 114
 115
 116 end behave;