board/mini2440/mini2440.c

   1 /*
   2  * (C) Copyright 2002
   3  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   4  * Marius Groeger <mgroeger@sysgo.de>
   5  *
   6  * (C) Copyright 2002
   7  * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
   8  *
   9  * (C) Copyright 2009
  10  * Michel Pollet <buserror@gmail.com>
  11  *
  12  * See file CREDITS for list of people who contributed to this
  13  * project.
  14  *
  15  * This program is free software; you can redistribute it and/or
  16  * modify it under the terms of the GNU General Public License as
  17  * published by the Free Software Foundation; either version 2 of
  18  * the License, or (at your option) any later version.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  *
  25  * You should have received a copy of the GNU General Public License
  26  * along with this program; if not, write to the Free Software
  27  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  28  * MA 02111-1307 USA
  29  */
  30
  31 #include <common.h>
  32 #include <s3c2440.h>
  33 #include <video_fb.h>
  34
  35 DECLARE_GLOBAL_DATA_PTR;
  36
  37 /* FCLK = 405 MHz, HCLK = 101 MHz, PCLK = 50 MHz, UCLK = 48 MHz */
  38 #define CLKDIVN_VAL     5
  39 #define M_MDIV          0x7f
  40 #define M_PDIV          0x2
  41 #define M_SDIV          0x1
  42
  43 #define U_M_MDIV        0x38
  44 #define U_M_PDIV        0x2
  45 #define U_M_SDIV        0x2
  46
  47 static inline void delay (unsigned long loops)
  48 {
  49         __asm__ volatile ("1:\n"
  50           "subs %0, %1, #1\n"
  51           "bne 1b":"=r" (loops):"0" (loops));
  52 }
  53
  54 /*
  55  * Miscellaneous platform dependent initialisations
  56  */
  57
  58 int board_init (void)
  59 {
  60         S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
  61         S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
  62
  63         /* to reduce PLL lock time, adjust the LOCKTIME register */
  64         clk_power->LOCKTIME = 0xFFFFFF;
  65         clk_power->CLKDIVN = CLKDIVN_VAL;
  66
  67         /* configure UPLL */
  68         clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
  69         /* some delay between MPLL and UPLL */
  70         delay (10);
  71         /* configure MPLL */
  72         clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
  73
  74         /* some delay between MPLL and UPLL */
  75         delay (8000);
  76
  77         gpio->GPACON = 0x007FFFFF;      /* Port A is all "special" */
  78         // port B outputs reconfigured
  79         gpio->GPBCON =
  80                 (0x1 <<  0) | // GPB0   OUT     TOUT0           PWM Buzzer
  81                 (0x2 <<  2) | // GPB1   OUT     TOUT1           LCD Backlight ?
  82                 (0x1 <<  4) | // GPB2   OUT     L3MODE
  83                 (0x1 <<  6) | // GBP3   OUT     L3DATA
  84                 (0x1 <<  8) | // GBP4   OUT     L3CLOCK
  85                 (0x1 << 10) | // GBP5   OUT     LED1
  86                 (0x1 << 12) | // GBP6   OUT     LED2
  87                 (0x1 << 14) | // GBP7   OUT     LED3
  88                 (0x1 << 16) | // GBP8   OUT     LED4
  89                 (0x2 << 18) | // GBP9   ---     nXDACK0         CON5 EBI
  90                 (0x2 << 20) | // GBP10  ---     nXDREQ0         CON5 EBI
  91                 0;
  92         gpio->GPBUP     = (1 << 10) - 1; // disable pullup on all 10 pins
  93         gpio->GPBDAT    =
  94                 (0 << 5) | /* turn LED 1 on */
  95                 (1 << 6) | /* turn LED 1 off */
  96                 (1 << 7) | /* turn LED 1 off */
  97                 (1 << 8) | /* turn LED 1 off */
  98                 0;
  99
 100         // lcd signals on C and D
 101         gpio->GPCCON    = (0xAAAAAAAA & /* all default IN but ... */
 102                                 ~(0x3 << 10)) | /* not pin 5 ... */
 103                                 (0x1 << 10);    /* that is output (USBD) */
 104         gpio->GPCUP     = 0xFFFFFFFF;
 105         gpio->GPCDAT    = 0;
 106
 107         gpio->GPDCON    = 0xAAAAAAAA;
 108         gpio->GPDUP     = 0xFFFFFFFF;
 109         // port E is set for all it's special functions (i2c, spi etc)
 110         gpio->GPECON    = 0xAAAAAAAA;
 111         gpio->GPEUP     = 0x0000FFFF;
 112
 113         gpio->GPFCON    =
 114                 (0x1 <<  0) | // GPG0   EINT0   OUT
 115                 (0x1 <<  2) | // GPG1   EINT1   OUT
 116                 (0x1 <<  4) | // GPG2   EINT2   OUT
 117                 (0x1 <<  6) | // GPG3   EINT3   OUT
 118                 (0x1 <<  8) | // GPG4   EINT4   OUT
 119                 (0x1 << 10) | // GPG5   EINT5   OUT
 120                 (0x1 << 12) | // GPG6   EINT6   OUT
 121                 (0x0 << 14) | // GPG7   EINT7   IN      DM9000
 122                 0;
 123         gpio->GPFDAT    = 0;
 124         gpio->GPFUP     =
 125                 ((1 << 7) - 1) // all disabled
 126                 & ~( 1 << 7 ) // but for the ethernet one, we need it.
 127                 ;
 128
 129         gpio->GPGCON    =
 130                 (0x0 <<  0) | // GPG0   EINT8   IN      Key1
 131                 (0x1 <<  2) | // GPG1   EINT9   OUT             Con5
 132                 (0x1 <<  4) | // GPG2   EINT10  OUT
 133                 (0x0 <<  6) | // GPG3   EINT11  IN      Key2
 134                 (0x1 <<  8) | // GPG4   EINT12  OUT
 135                 (0x0 << 10) | // GPG5   EINT13  IN      Key3
 136                 (0x0 << 12) | // GPG6   EINT14  IN      Key4
 137                 (0x0 << 14) | // GPG7   EINT15  IN      Key5
 138                 (0x1 << 16) | // GPG8   EINT16  OUT     nCD_SD
 139                 (0x1 << 18) | // GPG9   EINT17  OUT
 140                 (0x1 << 20) | // GPG10  EINT18  OUT
 141                 (0x0 << 22) | // GPG11  EINT19  IN      Key6
 142                 (0x0 << 24) | // GPG12  EINT18  IN      // GPG[12..15] need to be inputs
 143                 (0x0 << 26) | // GPG13  EINT18  IN      // hard pullups
 144                 (0x0 << 28) | // GPG14  EINT18  IN
 145                 (0x0 << 30) | // GPG15  EINT18  IN
 146                 0;
 147         gpio->GPGUP = (1 << 15) -1;     // disable pullups for all pins
 148
 149         gpio->GPHCON =
 150                 (0x2 <<  0) | // GPH0   nCTS0                   ---
 151                 (0x2 <<  2) | // GPH1   nRTS0                   ---
 152                 (0x2 <<  4) | // GPH2   TXD0                    ---
 153                 (0x2 <<  6) | // GPH3   RXD0                    ---
 154                 (0x2 <<  8) | // GPH4   TXD1                    ---
 155                 (0x2 << 10) | // GPH5   RXD1                    ---
 156                 (0x2 << 12) | // GPH6   [TXD2]  nRTS1
 157                 (0x2 << 14) | // GPH7   [RXD2]  nCTS1
 158                 (0x1 << 16) | // GPH8   UEXTCLK                 OUT
 159                 (0x1 << 18) | // GPH9   CLKOUT0                 OUT
 160                 (0x1 << 20) | // GPH10  CLKOUT1                 OUT
 161                 0;
 162         gpio->GPHUP = (1 << 10) - 1; // disable pullups for all pins
 163
 164         gpio->EXTINT0=0x22222222;
 165         gpio->EXTINT1=0x22222222;
 166         gpio->EXTINT2=0x22222222;
 167
 168         /* USB Device Part */
 169         /* GPC5 is reset for USB Device */
 170
 171         gpio->GPCDAT |= ( 1 << 5) ;
 172         udelay(20000);
 173         gpio->GPCDAT &= ~( 1 << 5) ;
 174         udelay(20000);
 175         gpio->GPCDAT |= ( 1 << 5) ;
 176
 177         /* arch number from kernel post 2.6.28 */
 178 #ifndef MACH_TYPE_MINI2440
 179 #define MACH_TYPE_MINI2440 1999
 180 #endif
 181         gd->bd->bi_arch_number = MACH_TYPE_MINI2440;
 182
 183         /* adress of boot parameters */
 184         gd->bd->bi_boot_params = 0x30000100;
 185
 186         icache_enable();
 187         dcache_enable();
 188
 189         return 0;
 190 }
 191
 192
 193
 194 #define MVAL            (0)
 195 #define MVAL_USED       (0)             //0=each frame   1=rate by MVAL
 196 #define INVVDEN         (1)             //0=normal       1=inverted
 197 #define BSWP            (0)             //Byte swap control
 198 #define HWSWP           (1)             //Half word swap control
 199
 200
 201 //TFT 240320
 202 #define LCD_XSIZE_TFT_240320    (240)
 203 #define LCD_YSIZE_TFT_240320    (320)
 204
 205 //TFT240320
 206 #define HOZVAL_TFT_240320       (LCD_XSIZE_TFT_240320-1)
 207 #define LINEVAL_TFT_240320      (LCD_YSIZE_TFT_240320-1)
 208
 209 //Timing parameter for NEC3.5"
 210 #define VBPD_240320             (3)
 211 #define VFPD_240320             (10)
 212 #define VSPW_240320             (1)
 213
 214 #define HBPD_240320             (5)
 215 #define HFPD_240320             (2)
 216 #define HSPW_240320             (36)
 217
 218 #define CLKVAL_TFT_240320       (3)
 219 //FCLK=101.25MHz,HCLK=50.625MHz,VCLK=6.33MHz
 220
 221
 222 void board_video_init(GraphicDevice *pGD)
 223 {
 224     S3C24X0_LCD * const lcd = S3C24X0_GetBase_LCD();
 225
 226     /* FIXME: select LCM type by env variable */
 227
 228         /* Configuration for GTA01 LCM on QT2410 */
 229         lcd->LCDCON1 = 0x00000378; /* CLKVAL=4, BPPMODE=16bpp, TFT, ENVID=0 */
 230
 231 //    lcd->LCDCON2 = 0x014fc141;
 232 //      lcd->LCDCON3 = 0x0098ef13;
 233 //      lcd->LCDCON4 = 0x00000d05;
 234         lcd->LCDCON5 = 0x00000f09;
 235
 236         lcd->LCDCON2 = (VBPD_240320<<24)|(LINEVAL_TFT_240320<<14)|(VFPD_240320<<6)|(VSPW_240320);
 237         lcd->LCDCON3 = (HBPD_240320<<19)|(HOZVAL_TFT_240320<<8)|(HFPD_240320);
 238         lcd->LCDCON4 = (MVAL<<8)|(HSPW_240320);
 239
 240
 241     lcd->LPCSEL  = 0x00000000;
 242 }
 243
 244 int dram_init (void)
 245 {
 246         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 247         gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 248
 249         return 0;
 250 }
 251
 252 /* The sum of all part_size[]s must equal to the NAND size, i.e., 0x4000000 */
 253
 254 unsigned int dynpart_size[] = {
 255     CFG_UBOOT_SIZE, 0x20000, 0x500000, 0xffffffff, 0 };
 256 char *dynpart_names[] = {
 257     "u-boot", "u-boot_env", "kernel", "rootfs", NULL };
 258
 259