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Comply to c89 compilers other than gcc (Hanzac Chen)
[tinycc.git] / i386-asm.c
blob899e9d804f91fed1a8c09365db69d70222d720b2
1 /*
2 * i386 specific functions for TCC assembler
3 *
4 * Copyright (c) 2001, 2002 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21 #define MAX_OPERANDS 3
22
23 typedef struct ASMInstr {
24 uint16_t sym;
25 uint16_t opcode;
26 uint16_t instr_type;
27 #define OPC_JMP 0x01 /* jmp operand */
28 #define OPC_B 0x02 /* only used zith OPC_WL */
29 #define OPC_WL 0x04 /* accepts w, l or no suffix */
30 #define OPC_BWL (OPC_B | OPC_WL) /* accepts b, w, l or no suffix */
31 #define OPC_REG 0x08 /* register is added to opcode */
32 #define OPC_MODRM 0x10 /* modrm encoding */
33 #define OPC_FWAIT 0x20 /* add fwait opcode */
34 #define OPC_TEST 0x40 /* test opcodes */
35 #define OPC_SHIFT 0x80 /* shift opcodes */
36 #define OPC_D16 0x0100 /* generate data16 prefix */
37 #define OPC_ARITH 0x0200 /* arithmetic opcodes */
38 #define OPC_SHORTJMP 0x0400 /* short jmp operand */
39 #define OPC_FARITH 0x0800 /* FPU arithmetic opcodes */
40 #define OPC_GROUP_SHIFT 13
41
42 /* in order to compress the operand type, we use specific operands and
43 we or only with EA */
44 #define OPT_REG8 0 /* warning: value is hardcoded from TOK_ASM_xxx */
45 #define OPT_REG16 1 /* warning: value is hardcoded from TOK_ASM_xxx */
46 #define OPT_REG32 2 /* warning: value is hardcoded from TOK_ASM_xxx */
47 #define OPT_MMX 3 /* warning: value is hardcoded from TOK_ASM_xxx */
48 #define OPT_SSE 4 /* warning: value is hardcoded from TOK_ASM_xxx */
49 #define OPT_CR 5 /* warning: value is hardcoded from TOK_ASM_xxx */
50 #define OPT_TR 6 /* warning: value is hardcoded from TOK_ASM_xxx */
51 #define OPT_DB 7 /* warning: value is hardcoded from TOK_ASM_xxx */
52 #define OPT_SEG 8
53 #define OPT_ST 9
54 #define OPT_IM8 10
55 #define OPT_IM8S 11
56 #define OPT_IM16 12
57 #define OPT_IM32 13
58 #define OPT_EAX 14 /* %al, %ax or %eax register */
59 #define OPT_ST0 15 /* %st(0) register */
60 #define OPT_CL 16 /* %cl register */
61 #define OPT_DX 17 /* %dx register */
62 #define OPT_ADDR 18 /* OP_EA with only offset */
63 #define OPT_INDIR 19 /* *(expr) */
64
65 /* composite types */
66 #define OPT_COMPOSITE_FIRST 20
67 #define OPT_IM 20 /* IM8 | IM16 | IM32 */
68 #define OPT_REG 21 /* REG8 | REG16 | REG32 */
69 #define OPT_REGW 22 /* REG16 | REG32 */
70 #define OPT_IMW 23 /* IM16 | IM32 */
71
72 /* can be ored with any OPT_xxx */
73 #define OPT_EA 0x80
74
75 uint8_t nb_ops;
76 uint8_t op_type[MAX_OPERANDS]; /* see OP_xxx */
77 } ASMInstr;
78
79 typedef struct Operand {
80 uint32_t type;
81 #define OP_REG8 (1 << OPT_REG8)
82 #define OP_REG16 (1 << OPT_REG16)
83 #define OP_REG32 (1 << OPT_REG32)
84 #define OP_MMX (1 << OPT_MMX)
85 #define OP_SSE (1 << OPT_SSE)
86 #define OP_CR (1 << OPT_CR)
87 #define OP_TR (1 << OPT_TR)
88 #define OP_DB (1 << OPT_DB)
89 #define OP_SEG (1 << OPT_SEG)
90 #define OP_ST (1 << OPT_ST)
91 #define OP_IM8 (1 << OPT_IM8)
92 #define OP_IM8S (1 << OPT_IM8S)
93 #define OP_IM16 (1 << OPT_IM16)
94 #define OP_IM32 (1 << OPT_IM32)
95 #define OP_EAX (1 << OPT_EAX)
96 #define OP_ST0 (1 << OPT_ST0)
97 #define OP_CL (1 << OPT_CL)
98 #define OP_DX (1 << OPT_DX)
99 #define OP_ADDR (1 << OPT_ADDR)
100 #define OP_INDIR (1 << OPT_INDIR)
101
102 #define OP_EA 0x40000000
103 #define OP_REG (OP_REG8 | OP_REG16 | OP_REG32)
104 #define OP_IM OP_IM32
105 int8_t reg; /* register, -1 if none */
106 int8_t reg2; /* second register, -1 if none */
107 uint8_t shift;
108 ExprValue e;
109 } Operand;
110
111 static const uint8_t reg_to_size[5] = {
112 /*
113 [OP_REG8] = 0,
114 [OP_REG16] = 1,
115 [OP_REG32] = 2,
116 */
117 0, 0, 1, 0, 2
118 };
119
120 #define WORD_PREFIX_OPCODE 0x66
121
122 #define NB_TEST_OPCODES 30
123
124 static const uint8_t test_bits[NB_TEST_OPCODES] = {
125 0x00, /* o */
126 0x01, /* no */
127 0x02, /* b */
128 0x02, /* c */
129 0x02, /* nae */
130 0x03, /* nb */
131 0x03, /* nc */
132 0x03, /* ae */
133 0x04, /* e */
134 0x04, /* z */
135 0x05, /* ne */
136 0x05, /* nz */
137 0x06, /* be */
138 0x06, /* na */
139 0x07, /* nbe */
140 0x07, /* a */
141 0x08, /* s */
142 0x09, /* ns */
143 0x0a, /* p */
144 0x0a, /* pe */
145 0x0b, /* np */
146 0x0b, /* po */
147 0x0c, /* l */
148 0x0c, /* nge */
149 0x0d, /* nl */
150 0x0d, /* ge */
151 0x0e, /* le */
152 0x0e, /* ng */
153 0x0f, /* nle */
154 0x0f, /* g */
155 };
156
157 static const uint8_t segment_prefixes[] = {
158 0x26, /* es */
159 0x2e, /* cs */
160 0x36, /* ss */
161 0x3e, /* ds */
162 0x64, /* fs */
163 0x65 /* gs */
164 };
165
166 static const ASMInstr asm_instrs[] = {
167 #define ALT(x) x
168 #define DEF_ASM_OP0(name, opcode)
169 #define DEF_ASM_OP0L(name, opcode, group, instr_type) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 0 },
170 #define DEF_ASM_OP1(name, opcode, group, instr_type, op0) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 1, { op0 }},
171 #define DEF_ASM_OP2(name, opcode, group, instr_type, op0, op1) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 2, { op0, op1 }},
172 #define DEF_ASM_OP3(name, opcode, group, instr_type, op0, op1, op2) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 3, { op0, op1, op2 }},
173 #include "i386-asm.h"
174
175 /* last operation */
176 { 0, },
177 };
178
179 static const uint16_t op0_codes[] = {
180 #define ALT(x)
181 #define DEF_ASM_OP0(x, opcode) opcode,
182 #define DEF_ASM_OP0L(name, opcode, group, instr_type)
183 #define DEF_ASM_OP1(name, opcode, group, instr_type, op0)
184 #define DEF_ASM_OP2(name, opcode, group, instr_type, op0, op1)
185 #define DEF_ASM_OP3(name, opcode, group, instr_type, op0, op1, op2)
186 #include "i386-asm.h"
187 };
188
189 static inline int get_reg_shift(TCCState *s1)
190 {
191 int shift, v;
192
193 v = asm_int_expr(s1);
194 switch(v) {
195 case 1:
196 shift = 0;
197 break;
198 case 2:
199 shift = 1;
200 break;
201 case 4:
202 shift = 2;
203 break;
204 case 8:
205 shift = 3;
206 break;
207 default:
208 expect("1, 2, 4 or 8 constant");
209 shift = 0;
210 break;
211 }
212 return shift;
213 }
214
215 static int asm_parse_reg(void)
216 {
217 int reg;
218 if (tok != '%')
219 goto error_32;
220 next();
221 if (tok >= TOK_ASM_eax && tok <= TOK_ASM_edi) {
222 reg = tok - TOK_ASM_eax;
223 next();
224 return reg;
225 } else {
226 error_32:
227 expect("32 bit register");
228 return 0;
229 }
230 }
231
232 static void parse_operand(TCCState *s1, Operand *op)
233 {
234 ExprValue e;
235 int reg, indir;
236 const char *p;
237
238 indir = 0;
239 if (tok == '*') {
240 next();
241 indir = OP_INDIR;
242 }
243
244 if (tok == '%') {
245 next();
246 if (tok >= TOK_ASM_al && tok <= TOK_ASM_db7) {
247 reg = tok - TOK_ASM_al;
248 op->type = 1 << (reg >> 3); /* WARNING: do not change constant order */
249 op->reg = reg & 7;
250 if ((op->type & OP_REG) && op->reg == TREG_EAX)
251 op->type |= OP_EAX;
252 else if (op->type == OP_REG8 && op->reg == TREG_ECX)
253 op->type |= OP_CL;
254 else if (op->type == OP_REG16 && op->reg == TREG_EDX)
255 op->type |= OP_DX;
256 } else if (tok >= TOK_ASM_dr0 && tok <= TOK_ASM_dr7) {
257 op->type = OP_DB;
258 op->reg = tok - TOK_ASM_dr0;
259 } else if (tok >= TOK_ASM_es && tok <= TOK_ASM_gs) {
260 op->type = OP_SEG;
261 op->reg = tok - TOK_ASM_es;
262 } else if (tok == TOK_ASM_st) {
263 op->type = OP_ST;
264 op->reg = 0;
265 next();
266 if (tok == '(') {
267 next();
268 if (tok != TOK_PPNUM)
269 goto reg_error;
270 p = tokc.cstr->data;
271 reg = p[0] - '0';
272 if ((unsigned)reg >= 8 || p[1] != '\0')
273 goto reg_error;
274 op->reg = reg;
275 next();
276 skip(')');
277 }
278 if (op->reg == 0)
279 op->type |= OP_ST0;
280 goto no_skip;
281 } else {
282 reg_error:
283 error("unknown register");
284 }
285 next();
286 no_skip: ;
287 } else if (tok == '$') {
288 /* constant value */
289 next();
290 asm_expr(s1, &e);
291 op->type = OP_IM32;
292 op->e.v = e.v;
293 op->e.sym = e.sym;
294 if (!op->e.sym) {
295 if (op->e.v == (uint8_t)op->e.v)
296 op->type |= OP_IM8;
297 if (op->e.v == (int8_t)op->e.v)
298 op->type |= OP_IM8S;
299 if (op->e.v == (uint16_t)op->e.v)
300 op->type |= OP_IM16;
301 }
302 } else {
303 /* address(reg,reg2,shift) with all variants */
304 op->type = OP_EA;
305 op->reg = -1;
306 op->reg2 = -1;
307 op->shift = 0;
308 if (tok != '(') {
309 asm_expr(s1, &e);
310 op->e.v = e.v;
311 op->e.sym = e.sym;
312 } else {
313 op->e.v = 0;
314 op->e.sym = NULL;
315 }
316 if (tok == '(') {
317 next();
318 if (tok != ',') {
319 op->reg = asm_parse_reg();
320 }
321 if (tok == ',') {
322 next();
323 if (tok != ',') {
324 op->reg2 = asm_parse_reg();
325 }
326 if (tok == ',') {
327 next();
328 op->shift = get_reg_shift(s1);
329 }
330 }
331 skip(')');
332 }
333 if (op->reg == -1 && op->reg2 == -1)
334 op->type |= OP_ADDR;
335 }
336 op->type |= indir;
337 }
338
339 /* XXX: unify with C code output ? */
340 static void gen_expr32(ExprValue *pe)
341 {
342 if (pe->sym)
343 greloc(cur_text_section, pe->sym, ind, R_386_32);
344 gen_le32(pe->v);
345 }
346
347 /* XXX: unify with C code output ? */
348 static void gen_disp32(ExprValue *pe)
349 {
350 Sym *sym;
351 sym = pe->sym;
352 if (sym) {
353 if (sym->r == cur_text_section->sh_num) {
354 /* same section: we can output an absolute value. Note
355 that the TCC compiler behaves differently here because
356 it always outputs a relocation to ease (future) code
357 elimination in the linker */
358 gen_le32(pe->v + (long)sym->next - ind - 4);
359 } else {
360 greloc(cur_text_section, sym, ind, R_386_PC32);
361 gen_le32(pe->v - 4);
362 }
363 } else {
364 /* put an empty PC32 relocation */
365 put_elf_reloc(symtab_section, cur_text_section,
366 ind, R_386_PC32, 0);
367 gen_le32(pe->v - 4);
368 }
369 }
370
371
372 static void gen_le16(int v)
373 {
374 g(v);
375 g(v >> 8);
376 }
377
378 /* generate the modrm operand */
379 static inline void asm_modrm(int reg, Operand *op)
380 {
381 int mod, reg1, reg2, sib_reg1;
382
383 if (op->type & (OP_REG | OP_MMX | OP_SSE)) {
384 g(0xc0 + (reg << 3) + op->reg);
385 } else if (op->reg == -1 && op->reg2 == -1) {
386 /* displacement only */
387 g(0x05 + (reg << 3));
388 gen_expr32(&op->e);
389 } else {
390 sib_reg1 = op->reg;
391 /* fist compute displacement encoding */
392 if (sib_reg1 == -1) {
393 sib_reg1 = 5;
394 mod = 0x00;
395 } else if (op->e.v == 0 && !op->e.sym && op->reg != 5) {
396 mod = 0x00;
397 } else if (op->e.v == (int8_t)op->e.v && !op->e.sym) {
398 mod = 0x40;
399 } else {
400 mod = 0x80;
401 }
402 /* compute if sib byte needed */
403 reg1 = op->reg;
404 if (op->reg2 != -1)
405 reg1 = 4;
406 g(mod + (reg << 3) + reg1);
407 if (reg1 == 4) {
408 /* add sib byte */
409 reg2 = op->reg2;
410 if (reg2 == -1)
411 reg2 = 4; /* indicate no index */
412 g((op->shift << 6) + (reg2 << 3) + sib_reg1);
413 }
414
415 /* add offset */
416 if (mod == 0x40) {
417 g(op->e.v);
418 } else if (mod == 0x80 || op->reg == -1) {
419 gen_expr32(&op->e);
420 }
421 }
422 }
423
424 static void asm_opcode(TCCState *s1, int opcode)
425 {
426 const ASMInstr *pa;
427 int i, modrm_index, reg, v, op1, is_short_jmp, has_seg_prefix;
428 int nb_ops, s, ss;
429 Operand ops[MAX_OPERANDS], *pop, seg_prefix;
430 int op_type[3]; /* decoded op type */
431
432 /* get operands */
433 pop = ops;
434 nb_ops = 0;
435 has_seg_prefix = 0;
436 for(;;) {
437 if (tok == ';' || tok == TOK_LINEFEED)
438 break;
439 if (nb_ops >= MAX_OPERANDS) {
440 error("incorrect number of operands");
441 }
442 parse_operand(s1, pop);
443 if (tok == ':') {
444 if (pop->type != OP_SEG || has_seg_prefix) {
445 error("incorrect prefix");
446 }
447 seg_prefix = *pop;
448 has_seg_prefix = 1;
449 next();
450 parse_operand(s1, pop);
451 if (!(pop->type & OP_EA)) {
452 error("segment prefix must be followed by memory reference");
453 }
454 }
455 pop++;
456 nb_ops++;
457 if (tok != ',')
458 break;
459 next();
460 }
461
462 is_short_jmp = 0;
463 s = 0; /* avoid warning */
464
465 /* optimize matching by using a lookup table (no hashing is needed
466 !) */
467 for(pa = asm_instrs; pa->sym != 0; pa++) {
468 s = 0;
469 if (pa->instr_type & OPC_FARITH) {
470 v = opcode - pa->sym;
471 if (!((unsigned)v < 8 * 6 && (v % 6) == 0))
472 continue;
473 } else if (pa->instr_type & OPC_ARITH) {
474 if (!(opcode >= pa->sym && opcode < pa->sym + 8 * 4))
475 continue;
476 goto compute_size;
477 } else if (pa->instr_type & OPC_SHIFT) {
478 if (!(opcode >= pa->sym && opcode < pa->sym + 7 * 4))
479 continue;
480 goto compute_size;
481 } else if (pa->instr_type & OPC_TEST) {
482 if (!(opcode >= pa->sym && opcode < pa->sym + NB_TEST_OPCODES))
483 continue;
484 } else if (pa->instr_type & OPC_B) {
485 if (!(opcode >= pa->sym && opcode <= pa->sym + 3))
486 continue;
487 compute_size:
488 s = (opcode - pa->sym) & 3;
489 } else if (pa->instr_type & OPC_WL) {
490 if (!(opcode >= pa->sym && opcode <= pa->sym + 2))
491 continue;
492 s = opcode - pa->sym + 1;
493 } else {
494 if (pa->sym != opcode)
495 continue;
496 }
497 if (pa->nb_ops != nb_ops)
498 continue;
499 /* now decode and check each operand */
500 for(i = 0; i < nb_ops; i++) {
501 int op1, op2;
502 op1 = pa->op_type[i];
503 op2 = op1 & 0x1f;
504 switch(op2) {
505 case OPT_IM:
506 v = OP_IM8 | OP_IM16 | OP_IM32;
507 break;
508 case OPT_REG:
509 v = OP_REG8 | OP_REG16 | OP_REG32;
510 break;
511 case OPT_REGW:
512 v = OP_REG16 | OP_REG32;
513 break;
514 case OPT_IMW:
515 v = OP_IM16 | OP_IM32;
516 break;
517 default:
518 v = 1 << op2;
519 break;
520 }
521 if (op1 & OPT_EA)
522 v |= OP_EA;
523 op_type[i] = v;
524 if ((ops[i].type & v) == 0)
525 goto next;
526 }
527 /* all is matching ! */
528 break;
529 next: ;
530 }
531 if (pa->sym == 0) {
532 if (opcode >= TOK_ASM_pusha && opcode <= TOK_ASM_emms) {
533 int b;
534 b = op0_codes[opcode - TOK_ASM_pusha];
535 if (b & 0xff00)
536 g(b >> 8);
537 g(b);
538 return;
539 } else {
540 error("unknown opcode '%s'",
541 get_tok_str(opcode, NULL));
542 }
543 }
544 /* if the size is unknown, then evaluate it (OPC_B or OPC_WL case) */
545 if (s == 3) {
546 for(i = 0; s == 3 && i < nb_ops; i++) {
547 if ((ops[i].type & OP_REG) && !(op_type[i] & (OP_CL | OP_DX)))
548 s = reg_to_size[ops[i].type & OP_REG];
549 }
550 if (s == 3) {
551 if ((opcode == TOK_ASM_push || opcode == TOK_ASM_pop) &&
552 (ops[0].type & (OP_SEG | OP_IM8S | OP_IM32)))
553 s = 2;
554 else
555 error("cannot infer opcode suffix");
556 }
557 }
558
559 /* generate data16 prefix if needed */
560 ss = s;
561 if (s == 1 || (pa->instr_type & OPC_D16))
562 g(WORD_PREFIX_OPCODE);
563 else if (s == 2)
564 s = 1;
565 /* now generates the operation */
566 if (pa->instr_type & OPC_FWAIT)
567 g(0x9b);
568 if (has_seg_prefix)
569 g(segment_prefixes[seg_prefix.reg]);
570
571 v = pa->opcode;
572 if (v == 0x69 || v == 0x69) {
573 /* kludge for imul $im, %reg */
574 nb_ops = 3;
575 ops[2] = ops[1];
576 } else if (v == 0xcd && ops[0].e.v == 3 && !ops[0].e.sym) {
577 v--; /* int $3 case */
578 nb_ops = 0;
579 } else if ((v == 0x06 || v == 0x07)) {
580 if (ops[0].reg >= 4) {
581 /* push/pop %fs or %gs */
582 v = 0x0fa0 + (v - 0x06) + ((ops[0].reg - 4) << 3);
583 } else {
584 v += ops[0].reg << 3;
585 }
586 nb_ops = 0;
587 } else if (v <= 0x05) {
588 /* arith case */
589 v += ((opcode - TOK_ASM_addb) >> 2) << 3;
590 } else if ((pa->instr_type & (OPC_FARITH | OPC_MODRM)) == OPC_FARITH) {
591 /* fpu arith case */
592 v += ((opcode - pa->sym) / 6) << 3;
593 }
594 if (pa->instr_type & OPC_REG) {
595 for(i = 0; i < nb_ops; i++) {
596 if (op_type[i] & (OP_REG | OP_ST)) {
597 v += ops[i].reg;
598 break;
599 }
600 }
601 /* mov $im, %reg case */
602 if (pa->opcode == 0xb0 && s >= 1)
603 v += 7;
604 }
605 if (pa->instr_type & OPC_B)
606 v += s;
607 if (pa->instr_type & OPC_TEST)
608 v += test_bits[opcode - pa->sym];
609 if (pa->instr_type & OPC_SHORTJMP) {
610 Sym *sym;
611 int jmp_disp;
612
613 /* see if we can really generate the jump with a byte offset */
614 sym = ops[0].e.sym;
615 if (!sym)
616 goto no_short_jump;
617 if (sym->r != cur_text_section->sh_num)
618 goto no_short_jump;
619 jmp_disp = ops[0].e.v + (long)sym->next - ind - 2;
620 if (jmp_disp == (int8_t)jmp_disp) {
621 /* OK to generate jump */
622 is_short_jmp = 1;
623 ops[0].e.v = jmp_disp;
624 } else {
625 no_short_jump:
626 if (pa->instr_type & OPC_JMP) {
627 /* long jump will be allowed. need to modify the
628 opcode slightly */
629 if (v == 0xeb)
630 v = 0xe9;
631 else
632 v += 0x0f10;
633 } else {
634 error("invalid displacement");
635 }
636 }
637 }
638 op1 = v >> 8;
639 if (op1)
640 g(op1);
641 g(v);
642
643 /* search which operand will used for modrm */
644 modrm_index = 0;
645 if (pa->instr_type & OPC_SHIFT) {
646 reg = (opcode - pa->sym) >> 2;
647 if (reg == 6)
648 reg = 7;
649 } else if (pa->instr_type & OPC_ARITH) {
650 reg = (opcode - pa->sym) >> 2;
651 } else if (pa->instr_type & OPC_FARITH) {
652 reg = (opcode - pa->sym) / 6;
653 } else {
654 reg = (pa->instr_type >> OPC_GROUP_SHIFT) & 7;
655 }
656 if (pa->instr_type & OPC_MODRM) {
657 /* first look for an ea operand */
658 for(i = 0;i < nb_ops; i++) {
659 if (op_type[i] & OP_EA)
660 goto modrm_found;
661 }
662 /* then if not found, a register or indirection (shift instructions) */
663 for(i = 0;i < nb_ops; i++) {
664 if (op_type[i] & (OP_REG | OP_MMX | OP_SSE | OP_INDIR))
665 goto modrm_found;
666 }
667 #ifdef ASM_DEBUG
668 error("bad op table");
669 #endif
670 modrm_found:
671 modrm_index = i;
672 /* if a register is used in another operand then it is
673 used instead of group */
674 for(i = 0;i < nb_ops; i++) {
675 v = op_type[i];
676 if (i != modrm_index &&
677 (v & (OP_REG | OP_MMX | OP_SSE | OP_CR | OP_TR | OP_DB | OP_SEG))) {
678 reg = ops[i].reg;
679 break;
680 }
681 }
682
683 asm_modrm(reg, &ops[modrm_index]);
684 }
685
686 /* emit constants */
687 if (pa->opcode == 0x9a || pa->opcode == 0xea) {
688 /* ljmp or lcall kludge */
689 gen_expr32(&ops[1].e);
690 if (ops[0].e.sym)
691 error("cannot relocate");
692 gen_le16(ops[0].e.v);
693 } else {
694 for(i = 0;i < nb_ops; i++) {
695 v = op_type[i];
696 if (v & (OP_IM8 | OP_IM16 | OP_IM32 | OP_IM8S | OP_ADDR)) {
697 /* if multiple sizes are given it means we must look
698 at the op size */
699 if (v == (OP_IM8 | OP_IM16 | OP_IM32) ||
700 v == (OP_IM16 | OP_IM32)) {
701 if (ss == 0)
702 v = OP_IM8;
703 else if (ss == 1)
704 v = OP_IM16;
705 else
706 v = OP_IM32;
707 }
708 if (v & (OP_IM8 | OP_IM8S)) {
709 if (ops[i].e.sym)
710 goto error_relocate;
711 g(ops[i].e.v);
712 } else if (v & OP_IM16) {
713 if (ops[i].e.sym) {
714 error_relocate:
715 error("cannot relocate");
716 }
717 gen_le16(ops[i].e.v);
718 } else {
719 if (pa->instr_type & (OPC_JMP | OPC_SHORTJMP)) {
720 if (is_short_jmp)
721 g(ops[i].e.v);
722 else
723 gen_disp32(&ops[i].e);
724 } else {
725 gen_expr32(&ops[i].e);
726 }
727 }
728 }
729 }
730 }
731 }
732
733 #define NB_SAVED_REGS 3
734 #define NB_ASM_REGS 8
735
736 /* return the constraint priority (we allocate first the lowest
737 numbered constraints) */
738 static inline int constraint_priority(const char *str)
739 {
740 int priority, c, pr;
741
742 /* we take the lowest priority */
743 priority = 0;
744 for(;;) {
745 c = *str;
746 if (c == '\0')
747 break;
748 str++;
749 switch(c) {
750 case 'A':
751 pr = 0;
752 break;
753 case 'a':
754 case 'b':
755 case 'c':
756 case 'd':
757 case 'S':
758 case 'D':
759 pr = 1;
760 break;
761 case 'q':
762 pr = 2;
763 break;
764 case 'r':
765 pr = 3;
766 break;
767 case 'N':
768 case 'M':
769 case 'I':
770 case 'i':
771 case 'm':
772 case 'g':
773 pr = 4;
774 break;
775 default:
776 error("unknown constraint '%c'", c);
777 pr = 0;
778 }
779 if (pr > priority)
780 priority = pr;
781 }
782 return priority;
783 }
784
785 static const char *skip_constraint_modifiers(const char *p)
786 {
787 while (*p == '=' || *p == '&' || *p == '+' || *p == '%')
788 p++;
789 return p;
790 }
791
792 #define REG_OUT_MASK 0x01
793 #define REG_IN_MASK 0x02
794
795 #define is_reg_allocated(reg) (regs_allocated[reg] & reg_mask)
796
797 static void asm_compute_constraints(ASMOperand *operands,
798 int nb_operands, int nb_outputs,
799 const uint8_t *clobber_regs,
800 int *pout_reg)
801 {
802 ASMOperand *op;
803 int sorted_op[MAX_ASM_OPERANDS];
804 int i, j, k, p1, p2, tmp, reg, c, reg_mask;
805 const char *str;
806 uint8_t regs_allocated[NB_ASM_REGS];
807
808 /* init fields */
809 for(i=0;i<nb_operands;i++) {
810 op = &operands[i];
811 op->input_index = -1;
812 op->ref_index = -1;
813 op->reg = -1;
814 op->is_memory = 0;
815 op->is_rw = 0;
816 }
817 /* compute constraint priority and evaluate references to output
818 constraints if input constraints */
819 for(i=0;i<nb_operands;i++) {
820 op = &operands[i];
821 str = op->constraint;
822 str = skip_constraint_modifiers(str);
823 if (isnum(*str) || *str == '[') {
824 /* this is a reference to another constraint */
825 k = find_constraint(operands, nb_operands, str, NULL);
826 if ((unsigned)k >= i || i < nb_outputs)
827 error("invalid reference in constraint %d ('%s')",
828 i, str);
829 op->ref_index = k;
830 if (operands[k].input_index >= 0)
831 error("cannot reference twice the same operand");
832 operands[k].input_index = i;
833 op->priority = 5;
834 } else {
835 op->priority = constraint_priority(str);
836 }
837 }
838
839 /* sort operands according to their priority */
840 for(i=0;i<nb_operands;i++)
841 sorted_op[i] = i;
842 for(i=0;i<nb_operands - 1;i++) {
843 for(j=i+1;j<nb_operands;j++) {
844 p1 = operands[sorted_op[i]].priority;
845 p2 = operands[sorted_op[j]].priority;
846 if (p2 < p1) {
847 tmp = sorted_op[i];
848 sorted_op[i] = sorted_op[j];
849 sorted_op[j] = tmp;
850 }
851 }
852 }
853
854 for(i = 0;i < NB_ASM_REGS; i++) {
855 if (clobber_regs[i])
856 regs_allocated[i] = REG_IN_MASK | REG_OUT_MASK;
857 else
858 regs_allocated[i] = 0;
859 }
860 /* esp cannot be used */
861 regs_allocated[4] = REG_IN_MASK | REG_OUT_MASK;
862 /* ebp cannot be used yet */
863 regs_allocated[5] = REG_IN_MASK | REG_OUT_MASK;
864
865 /* allocate registers and generate corresponding asm moves */
866 for(i=0;i<nb_operands;i++) {
867 j = sorted_op[i];
868 op = &operands[j];
869 str = op->constraint;
870 /* no need to allocate references */
871 if (op->ref_index >= 0)
872 continue;
873 /* select if register is used for output, input or both */
874 if (op->input_index >= 0) {
875 reg_mask = REG_IN_MASK | REG_OUT_MASK;
876 } else if (j < nb_outputs) {
877 reg_mask = REG_OUT_MASK;
878 } else {
879 reg_mask = REG_IN_MASK;
880 }
881 try_next:
882 c = *str++;
883 switch(c) {
884 case '=':
885 goto try_next;
886 case '+':
887 op->is_rw = 1;
888 /* FALL THRU */
889 case '&':
890 if (j >= nb_outputs)
891 error("'%c' modifier can only be applied to outputs", c);
892 reg_mask = REG_IN_MASK | REG_OUT_MASK;
893 goto try_next;
894 case 'A':
895 /* allocate both eax and edx */
896 if (is_reg_allocated(TREG_EAX) ||
897 is_reg_allocated(TREG_EDX))
898 goto try_next;
899 op->is_llong = 1;
900 op->reg = TREG_EAX;
901 regs_allocated[TREG_EAX] |= reg_mask;
902 regs_allocated[TREG_EDX] |= reg_mask;
903 break;
904 case 'a':
905 reg = TREG_EAX;
906 goto alloc_reg;
907 case 'b':
908 reg = 3;
909 goto alloc_reg;
910 case 'c':
911 reg = TREG_ECX;
912 goto alloc_reg;
913 case 'd':
914 reg = TREG_EDX;
915 goto alloc_reg;
916 case 'S':
917 reg = 6;
918 goto alloc_reg;
919 case 'D':
920 reg = 7;
921 alloc_reg:
922 if (is_reg_allocated(reg))
923 goto try_next;
924 goto reg_found;
925 case 'q':
926 /* eax, ebx, ecx or edx */
927 for(reg = 0; reg < 4; reg++) {
928 if (!is_reg_allocated(reg))
929 goto reg_found;
930 }
931 goto try_next;
932 case 'r':
933 /* any general register */
934 for(reg = 0; reg < 8; reg++) {
935 if (!is_reg_allocated(reg))
936 goto reg_found;
937 }
938 goto try_next;
939 reg_found:
940 /* now we can reload in the register */
941 op->is_llong = 0;
942 op->reg = reg;
943 regs_allocated[reg] |= reg_mask;
944 break;
945 case 'i':
946 if (!((op->vt->r & (VT_VALMASK | VT_LVAL)) == VT_CONST))
947 goto try_next;
948 break;
949 case 'I':
950 case 'N':
951 case 'M':
952 if (!((op->vt->r & (VT_VALMASK | VT_LVAL | VT_SYM)) == VT_CONST))
953 goto try_next;
954 break;
955 case 'm':
956 case 'g':
957 /* nothing special to do because the operand is already in
958 memory, except if the pointer itself is stored in a
959 memory variable (VT_LLOCAL case) */
960 /* XXX: fix constant case */
961 /* if it is a reference to a memory zone, it must lie
962 in a register, so we reserve the register in the
963 input registers and a load will be generated
964 later */
965 if (j < nb_outputs || c == 'm') {
966 if ((op->vt->r & VT_VALMASK) == VT_LLOCAL) {
967 /* any general register */
968 for(reg = 0; reg < 8; reg++) {
969 if (!(regs_allocated[reg] & REG_IN_MASK))
970 goto reg_found1;
971 }
972 goto try_next;
973 reg_found1:
974 /* now we can reload in the register */
975 regs_allocated[reg] |= REG_IN_MASK;
976 op->reg = reg;
977 op->is_memory = 1;
978 }
979 }
980 break;
981 default:
982 error("asm constraint %d ('%s') could not be satisfied",
983 j, op->constraint);
984 break;
985 }
986 /* if a reference is present for that operand, we assign it too */
987 if (op->input_index >= 0) {
988 operands[op->input_index].reg = op->reg;
989 operands[op->input_index].is_llong = op->is_llong;
990 }
991 }
992
993 /* compute out_reg. It is used to store outputs registers to memory
994 locations references by pointers (VT_LLOCAL case) */
995 *pout_reg = -1;
996 for(i=0;i<nb_operands;i++) {
997 op = &operands[i];
998 if (op->reg >= 0 &&
999 (op->vt->r & VT_VALMASK) == VT_LLOCAL &&
1000 !op->is_memory) {
1001 for(reg = 0; reg < 8; reg++) {
1002 if (!(regs_allocated[reg] & REG_OUT_MASK))
1003 goto reg_found2;
1004 }
1005 error("could not find free output register for reloading");
1006 reg_found2:
1007 *pout_reg = reg;
1008 break;
1009 }
1010 }
1011
1012 /* print sorted constraints */
1013 #ifdef ASM_DEBUG
1014 for(i=0;i<nb_operands;i++) {
1015 j = sorted_op[i];
1016 op = &operands[j];
1017 printf("%%%d [%s]: \"%s\" r=0x%04x reg=%d\n",
1018 j,
1019 op->id ? get_tok_str(op->id, NULL) : "",
1020 op->constraint,
1021 op->vt->r,
1022 op->reg);
1023 }
1024 if (*pout_reg >= 0)
1025 printf("out_reg=%d\n", *pout_reg);
1026 #endif
1027 }
1028
1029 static void subst_asm_operand(CString *add_str,
1030 SValue *sv, int modifier)
1031 {
1032 int r, reg, size, val;
1033 char buf[64];
1034
1035 r = sv->r;
1036 if ((r & VT_VALMASK) == VT_CONST) {
1037 if (!(r & VT_LVAL) && modifier != 'c' && modifier != 'n')
1038 cstr_ccat(add_str, '$');
1039 if (r & VT_SYM) {
1040 cstr_cat(add_str, get_tok_str(sv->sym->v, NULL));
1041 if (sv->c.i != 0) {
1042 cstr_ccat(add_str, '+');
1043 } else {
1044 return;
1045 }
1046 }
1047 val = sv->c.i;
1048 if (modifier == 'n')
1049 val = -val;
1050 snprintf(buf, sizeof(buf), "%d", sv->c.i);
1051 cstr_cat(add_str, buf);
1052 } else if ((r & VT_VALMASK) == VT_LOCAL) {
1053 snprintf(buf, sizeof(buf), "%d(%%ebp)", sv->c.i);
1054 cstr_cat(add_str, buf);
1055 } else if (r & VT_LVAL) {
1056 reg = r & VT_VALMASK;
1057 if (reg >= VT_CONST)
1058 error("internal compiler error");
1059 snprintf(buf, sizeof(buf), "(%%%s)",
1060 get_tok_str(TOK_ASM_eax + reg, NULL));
1061 cstr_cat(add_str, buf);
1062 } else {
1063 /* register case */
1064 reg = r & VT_VALMASK;
1065 if (reg >= VT_CONST)
1066 error("internal compiler error");
1067
1068 /* choose register operand size */
1069 if ((sv->type.t & VT_BTYPE) == VT_BYTE)
1070 size = 1;
1071 else if ((sv->type.t & VT_BTYPE) == VT_SHORT)
1072 size = 2;
1073 else
1074 size = 4;
1075 if (size == 1 && reg >= 4)
1076 size = 4;
1077
1078 if (modifier == 'b') {
1079 if (reg >= 4)
1080 error("cannot use byte register");
1081 size = 1;
1082 } else if (modifier == 'h') {
1083 if (reg >= 4)
1084 error("cannot use byte register");
1085 size = -1;
1086 } else if (modifier == 'w') {
1087 size = 2;
1088 }
1089
1090 switch(size) {
1091 case -1:
1092 reg = TOK_ASM_ah + reg;
1093 break;
1094 case 1:
1095 reg = TOK_ASM_al + reg;
1096 break;
1097 case 2:
1098 reg = TOK_ASM_ax + reg;
1099 break;
1100 default:
1101 reg = TOK_ASM_eax + reg;
1102 break;
1103 }
1104 snprintf(buf, sizeof(buf), "%%%s", get_tok_str(reg, NULL));
1105 cstr_cat(add_str, buf);
1106 }
1107 }
1108
1109 /* generate prolog and epilog code for asm statment */
1110 static void asm_gen_code(ASMOperand *operands, int nb_operands,
1111 int nb_outputs, int is_output,
1112 uint8_t *clobber_regs,
1113 int out_reg)
1114 {
1115 uint8_t regs_allocated[NB_ASM_REGS];
1116 ASMOperand *op;
1117 int i, reg;
1118 static uint8_t reg_saved[NB_SAVED_REGS] = { 3, 6, 7 };
1119
1120 /* mark all used registers */
1121 memcpy(regs_allocated, clobber_regs, sizeof(regs_allocated));
1122 for(i = 0; i < nb_operands;i++) {
1123 op = &operands[i];
1124 if (op->reg >= 0)
1125 regs_allocated[op->reg] = 1;
1126 }
1127 if (!is_output) {
1128 /* generate reg save code */
1129 for(i = 0; i < NB_SAVED_REGS; i++) {
1130 reg = reg_saved[i];
1131 if (regs_allocated[reg])
1132 g(0x50 + reg);
1133 }
1134
1135 /* generate load code */
1136 for(i = 0; i < nb_operands; i++) {
1137 op = &operands[i];
1138 if (op->reg >= 0) {
1139 if ((op->vt->r & VT_VALMASK) == VT_LLOCAL &&
1140 op->is_memory) {
1141 /* memory reference case (for both input and
1142 output cases) */
1143 SValue sv;
1144 sv = *op->vt;
1145 sv.r = (sv.r & ~VT_VALMASK) | VT_LOCAL;
1146 load(op->reg, &sv);
1147 } else if (i >= nb_outputs || op->is_rw) {
1148 /* load value in register */
1149 load(op->reg, op->vt);
1150 if (op->is_llong) {
1151 SValue sv;
1152 sv = *op->vt;
1153 sv.c.ul += 4;
1154 load(TREG_EDX, &sv);
1155 }
1156 }
1157 }
1158 }
1159 } else {
1160 /* generate save code */
1161 for(i = 0 ; i < nb_outputs; i++) {
1162 op = &operands[i];
1163 if (op->reg >= 0) {
1164 if ((op->vt->r & VT_VALMASK) == VT_LLOCAL) {
1165 if (!op->is_memory) {
1166 SValue sv;
1167 sv = *op->vt;
1168 sv.r = (sv.r & ~VT_VALMASK) | VT_LOCAL;
1169 load(out_reg, &sv);
1170
1171 sv.r = (sv.r & ~VT_VALMASK) | out_reg;
1172 store(op->reg, &sv);
1173 }
1174 } else {
1175 store(op->reg, op->vt);
1176 if (op->is_llong) {
1177 SValue sv;
1178 sv = *op->vt;
1179 sv.c.ul += 4;
1180 store(TREG_EDX, &sv);
1181 }
1182 }
1183 }
1184 }
1185 /* generate reg restore code */
1186 for(i = NB_SAVED_REGS - 1; i >= 0; i--) {
1187 reg = reg_saved[i];
1188 if (regs_allocated[reg])
1189 g(0x58 + reg);
1190 }
1191 }
1192 }
1193
1194 static void asm_clobber(uint8_t *clobber_regs, const char *str)
1195 {
1196 int reg;
1197 TokenSym *ts;
1198
1199 if (!strcmp(str, "memory") ||
1200 !strcmp(str, "cc"))
1201 return;
1202 ts = tok_alloc(str, strlen(str));
1203 reg = ts->tok;
1204 if (reg >= TOK_ASM_eax && reg <= TOK_ASM_edi) {
1205 reg -= TOK_ASM_eax;
1206 } else if (reg >= TOK_ASM_ax && reg <= TOK_ASM_di) {
1207 reg -= TOK_ASM_ax;
1208 } else {
1209 error("invalid clobber register '%s'", str);
1210 }
1211 clobber_regs[reg] = 1;
1212 }
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