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allow tcc be build from separate objects
[tinycc.git] / i386-asm.c
bloba378191bebee29f2ff095e935e091ee184cf08e6
1 /*
2 * i386 specific functions for TCC assembler
3 *
4 * Copyright (c) 2001, 2002 Fabrice Bellard
5 * Copyright (c) 2009 Frédéric Feret (x86_64 support)
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22 #include "tcc.h"
23
24 // #define NB_ASM_REGS 8
25 #define MAX_OPERANDS 3
26 #define NB_SAVED_REGS 3
27
28 #define TOK_ASM_first TOK_ASM_clc
29 #define TOK_ASM_last TOK_ASM_emms
30
31 #define OPC_JMP 0x01 /* jmp operand */
32 #define OPC_B 0x02 /* only used with OPC_WL */
33 #define OPC_WL 0x04 /* accepts w, l or no suffix */
34 #define OPC_BWL (OPC_B | OPC_WL) /* accepts b, w, l or no suffix */
35 #define OPC_REG 0x08 /* register is added to opcode */
36 #define OPC_MODRM 0x10 /* modrm encoding */
37 #define OPC_FWAIT 0x20 /* add fwait opcode */
38 #define OPC_TEST 0x40 /* test opcodes */
39 #define OPC_SHIFT 0x80 /* shift opcodes */
40 #define OPC_D16 0x0100 /* generate data16 prefix */
41 #define OPC_ARITH 0x0200 /* arithmetic opcodes */
42 #define OPC_SHORTJMP 0x0400 /* short jmp operand */
43 #define OPC_FARITH 0x0800 /* FPU arithmetic opcodes */
44 #ifdef TCC_TARGET_X86_64
45 # define OPC_WLQ 0x1000 /* accepts w, l, q or no suffix */
46 # define OPC_BWLQ (OPC_B | OPC_WLQ) /* accepts b, w, l, q or no suffix */
47 # define OPC_WLX OPC_WLQ
48 #else
49 # define OPC_WLX OPC_WL
50 #endif
51
52 #define OPC_GROUP_SHIFT 13
53
54 /* in order to compress the operand type, we use specific operands and
55 we or only with EA */
56 enum {
57 OPT_REG8=0, /* warning: value is hardcoded from TOK_ASM_xxx */
58 OPT_REG16, /* warning: value is hardcoded from TOK_ASM_xxx */
59 OPT_REG32, /* warning: value is hardcoded from TOK_ASM_xxx */
60 #ifdef TCC_TARGET_X86_64
61 OPT_REG64, /* warning: value is hardcoded from TOK_ASM_xxx */
62 #endif
63 OPT_MMX, /* warning: value is hardcoded from TOK_ASM_xxx */
64 OPT_SSE, /* warning: value is hardcoded from TOK_ASM_xxx */
65 OPT_CR, /* warning: value is hardcoded from TOK_ASM_xxx */
66 OPT_TR, /* warning: value is hardcoded from TOK_ASM_xxx */
67 OPT_DB, /* warning: value is hardcoded from TOK_ASM_xxx */
68 OPT_SEG,
69 OPT_ST,
70 OPT_IM8,
71 OPT_IM8S,
72 OPT_IM16,
73 OPT_IM32,
74 #ifdef TCC_TARGET_X86_64
75 OPT_IM64,
76 #endif
77 OPT_EAX, /* %al, %ax, %eax or %rax register */
78 OPT_ST0, /* %st(0) register */
79 OPT_CL, /* %cl register */
80 OPT_DX, /* %dx register */
81 OPT_ADDR, /* OP_EA with only offset */
82 OPT_INDIR, /* *(expr) */
83 /* composite types */
84 OPT_COMPOSITE_FIRST,
85 OPT_IM, /* IM8 | IM16 | IM32 | IM64 */
86 OPT_REG, /* REG8 | REG16 | REG32 | REG64 */
87 OPT_REGW, /* REG16 | REG32 | REG64 */
88 OPT_IMW, /* IM16 | IM32 | IM64 */
89 #ifdef TCC_TARGET_X86_64
90 OPT_IMNO64, /* IM16 | IM32 */
91 #endif
92 /* can be ored with any OPT_xxx */
93 OPT_EA = 0x80
94 };
95
96 #define OP_REG8 (1 << OPT_REG8)
97 #define OP_REG16 (1 << OPT_REG16)
98 #define OP_REG32 (1 << OPT_REG32)
99 #define OP_MMX (1 << OPT_MMX)
100 #define OP_SSE (1 << OPT_SSE)
101 #define OP_CR (1 << OPT_CR)
102 #define OP_TR (1 << OPT_TR)
103 #define OP_DB (1 << OPT_DB)
104 #define OP_SEG (1 << OPT_SEG)
105 #define OP_ST (1 << OPT_ST)
106 #define OP_IM8 (1 << OPT_IM8)
107 #define OP_IM8S (1 << OPT_IM8S)
108 #define OP_IM16 (1 << OPT_IM16)
109 #define OP_IM32 (1 << OPT_IM32)
110 #define OP_EAX (1 << OPT_EAX)
111 #define OP_ST0 (1 << OPT_ST0)
112 #define OP_CL (1 << OPT_CL)
113 #define OP_DX (1 << OPT_DX)
114 #define OP_ADDR (1 << OPT_ADDR)
115 #define OP_INDIR (1 << OPT_INDIR)
116 #ifdef TCC_TARGET_X86_64
117 # define OP_REG64 (1 << OPT_REG64)
118 # define OP_IM64 (1 << OPT_IM64)
119 #else
120 # define OP_REG64 0
121 # define OP_IM64 0
122 #endif
123
124 #define OP_EA 0x40000000
125 #define OP_REG (OP_REG8 | OP_REG16 | OP_REG32 | OP_REG64)
126
127 #ifdef TCC_TARGET_X86_64
128 # define OP_IM OP_IM64
129 # define TREG_XAX TREG_RAX
130 # define TREG_XCX TREG_RCX
131 # define TREG_XDX TREG_RDX
132 #else
133 # define OP_IM OP_IM32
134 # define TREG_XAX TREG_EAX
135 # define TREG_XCX TREG_ECX
136 # define TREG_XDX TREG_EDX
137 #endif
138
139 typedef struct ASMInstr {
140 uint16_t sym;
141 uint16_t opcode;
142 uint16_t instr_type;
143 uint8_t nb_ops;
144 uint8_t op_type[MAX_OPERANDS]; /* see OP_xxx */
145 } ASMInstr;
146
147 typedef struct Operand {
148 uint32_t type;
149 int8_t reg; /* register, -1 if none */
150 int8_t reg2; /* second register, -1 if none */
151 uint8_t shift;
152 ExprValue e;
153 } Operand;
154
155 static const uint8_t reg_to_size[9] = {
156 /*
157 [OP_REG8] = 0,
158 [OP_REG16] = 1,
159 [OP_REG32] = 2,
160 #ifdef TCC_TARGET_X86_64
161 [OP_REG64] = 3,
162 #endif
163 */
164 0, 0, 1, 0, 2, 0, 0, 0, 3
165 };
166
167 #define NB_TEST_OPCODES 30
168
169 static const uint8_t test_bits[NB_TEST_OPCODES] = {
170 0x00, /* o */
171 0x01, /* no */
172 0x02, /* b */
173 0x02, /* c */
174 0x02, /* nae */
175 0x03, /* nb */
176 0x03, /* nc */
177 0x03, /* ae */
178 0x04, /* e */
179 0x04, /* z */
180 0x05, /* ne */
181 0x05, /* nz */
182 0x06, /* be */
183 0x06, /* na */
184 0x07, /* nbe */
185 0x07, /* a */
186 0x08, /* s */
187 0x09, /* ns */
188 0x0a, /* p */
189 0x0a, /* pe */
190 0x0b, /* np */
191 0x0b, /* po */
192 0x0c, /* l */
193 0x0c, /* nge */
194 0x0d, /* nl */
195 0x0d, /* ge */
196 0x0e, /* le */
197 0x0e, /* ng */
198 0x0f, /* nle */
199 0x0f, /* g */
200 };
201
202 static const uint8_t segment_prefixes[] = {
203 0x26, /* es */
204 0x2e, /* cs */
205 0x36, /* ss */
206 0x3e, /* ds */
207 0x64, /* fs */
208 0x65 /* gs */
209 };
210
211 static const ASMInstr asm_instrs[] = {
212 #define ALT(x) x
213 #define DEF_ASM_OP0(name, opcode)
214 #define DEF_ASM_OP0L(name, opcode, group, instr_type) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 0 },
215 #define DEF_ASM_OP1(name, opcode, group, instr_type, op0) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 1, { op0 }},
216 #define DEF_ASM_OP2(name, opcode, group, instr_type, op0, op1) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 2, { op0, op1 }},
217 #define DEF_ASM_OP3(name, opcode, group, instr_type, op0, op1, op2) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 3, { op0, op1, op2 }},
218 #ifdef TCC_TARGET_X86_64
219 # include "x86_64-asm.h"
220 #else
221 # include "i386-asm.h"
222 #endif
223 /* last operation */
224 { 0, },
225 };
226
227 static const uint16_t op0_codes[] = {
228 #define ALT(x)
229 #define DEF_ASM_OP0(x, opcode) opcode,
230 #define DEF_ASM_OP0L(name, opcode, group, instr_type)
231 #define DEF_ASM_OP1(name, opcode, group, instr_type, op0)
232 #define DEF_ASM_OP2(name, opcode, group, instr_type, op0, op1)
233 #define DEF_ASM_OP3(name, opcode, group, instr_type, op0, op1, op2)
234 #ifdef TCC_TARGET_X86_64
235 # include "x86_64-asm.h"
236 #else
237 # include "i386-asm.h"
238 #endif
239 };
240
241 static inline int get_reg_shift(TCCState *s1)
242 {
243 int shift, v;
244 #ifdef I386_ASM_16
245 if (s1->seg_size == 16)
246 error("invalid effective address");
247 #endif
248 v = asm_int_expr(s1);
249 switch(v) {
250 case 1:
251 shift = 0;
252 break;
253 case 2:
254 shift = 1;
255 break;
256 case 4:
257 shift = 2;
258 break;
259 case 8:
260 shift = 3;
261 break;
262 default:
263 expect("1, 2, 4 or 8 constant");
264 shift = 0;
265 break;
266 }
267 return shift;
268 }
269
270 static int asm_parse_reg(void)
271 {
272 int reg = 0;
273 if (tok != '%')
274 goto error_32;
275 next();
276 if (tok >= TOK_ASM_eax && tok <= TOK_ASM_edi) {
277 reg = tok - TOK_ASM_eax;
278 #ifdef TCC_TARGET_X86_64
279 } else if (tok >= TOK_ASM_rax && tok <= TOK_ASM_rdi) {
280 reg = tok - TOK_ASM_rax;
281 #endif
282 #ifdef I386_ASM_16
283 } else if (tok >= TOK_ASM_ax && tok <= TOK_ASM_di) {
284 reg = tok - TOK_ASM_ax;
285 #endif
286 } else {
287 error_32:
288 expect("register");
289 }
290 next();
291 return reg;
292 }
293
294 static void parse_operand(TCCState *s1, Operand *op)
295 {
296 ExprValue e;
297 int reg, indir;
298 const char *p;
299
300 indir = 0;
301 if (tok == '*') {
302 next();
303 indir = OP_INDIR;
304 }
305
306 if (tok == '%') {
307 next();
308 if (tok >= TOK_ASM_al && tok <= TOK_ASM_db7) {
309 reg = tok - TOK_ASM_al;
310 op->type = 1 << (reg >> 3); /* WARNING: do not change constant order */
311 op->reg = reg & 7;
312 if ((op->type & OP_REG) && op->reg == TREG_XAX)
313 op->type |= OP_EAX;
314 else if (op->type == OP_REG8 && op->reg == TREG_XCX)
315 op->type |= OP_CL;
316 else if (op->type == OP_REG16 && op->reg == TREG_XDX)
317 op->type |= OP_DX;
318 } else if (tok >= TOK_ASM_dr0 && tok <= TOK_ASM_dr7) {
319 op->type = OP_DB;
320 op->reg = tok - TOK_ASM_dr0;
321 } else if (tok >= TOK_ASM_es && tok <= TOK_ASM_gs) {
322 op->type = OP_SEG;
323 op->reg = tok - TOK_ASM_es;
324 } else if (tok == TOK_ASM_st) {
325 op->type = OP_ST;
326 op->reg = 0;
327 next();
328 if (tok == '(') {
329 next();
330 if (tok != TOK_PPNUM)
331 goto reg_error;
332 p = tokc.cstr->data;
333 reg = p[0] - '0';
334 if ((unsigned)reg >= 8 || p[1] != '\0')
335 goto reg_error;
336 op->reg = reg;
337 next();
338 skip(')');
339 }
340 if (op->reg == 0)
341 op->type |= OP_ST0;
342 goto no_skip;
343 } else {
344 reg_error:
345 error("unknown register");
346 }
347 next();
348 no_skip: ;
349 } else if (tok == '$') {
350 /* constant value */
351 next();
352 asm_expr(s1, &e);
353 op->type = OP_IM;
354 op->e.v = e.v;
355 op->e.sym = e.sym;
356 if (!op->e.sym) {
357 if (op->e.v == (uint8_t)op->e.v)
358 op->type |= OP_IM8;
359 if (op->e.v == (int8_t)op->e.v)
360 op->type |= OP_IM8S;
361 if (op->e.v == (uint16_t)op->e.v)
362 op->type |= OP_IM16;
363 #ifdef TCC_TARGET_X86_64
364 if (op->e.v == (uint32_t)op->e.v)
365 op->type |= OP_IM32;
366 #endif
367 }
368 } else {
369 /* address(reg,reg2,shift) with all variants */
370 op->type = OP_EA;
371 op->reg = -1;
372 op->reg2 = -1;
373 op->shift = 0;
374 if (tok != '(') {
375 asm_expr(s1, &e);
376 op->e.v = e.v;
377 op->e.sym = e.sym;
378 } else {
379 op->e.v = 0;
380 op->e.sym = NULL;
381 }
382 if (tok == '(') {
383 next();
384 if (tok != ',') {
385 op->reg = asm_parse_reg();
386 }
387 if (tok == ',') {
388 next();
389 if (tok != ',') {
390 op->reg2 = asm_parse_reg();
391 }
392 if (tok == ',') {
393 next();
394 op->shift = get_reg_shift(s1);
395 }
396 }
397 skip(')');
398 }
399 if (op->reg == -1 && op->reg2 == -1)
400 op->type |= OP_ADDR;
401 }
402 op->type |= indir;
403 }
404
405 /* XXX: unify with C code output ? */
406 ST_FUNC void gen_expr32(ExprValue *pe)
407 {
408 gen_addr32(pe->sym ? VT_SYM : 0, pe->sym, pe->v);
409 }
410
411 #ifdef TCC_TARGET_X86_64
412 static void gen_expr64(ExprValue *pe)
413 {
414 gen_addr64(pe->sym ? VT_SYM : 0, pe->sym, pe->v);
415 }
416 #endif
417
418 /* XXX: unify with C code output ? */
419 static void gen_disp32(ExprValue *pe)
420 {
421 Sym *sym = pe->sym;
422 if (sym && sym->r == cur_text_section->sh_num) {
423 /* same section: we can output an absolute value. Note
424 that the TCC compiler behaves differently here because
425 it always outputs a relocation to ease (future) code
426 elimination in the linker */
427 gen_le32(pe->v + sym->jnext - ind - 4);
428 } else {
429 gen_addrpc32(VT_SYM, sym, pe->v);
430 }
431 }
432
433 #ifdef I386_ASM_16
434 static void gen_expr16(ExprValue *pe)
435 {
436 if (pe->sym)
437 greloc(cur_text_section, pe->sym, ind, R_386_16);
438 gen_le16(pe->v);
439 }
440 static void gen_disp16(ExprValue *pe)
441 {
442 Sym *sym;
443 sym = pe->sym;
444 if (sym) {
445 if (sym->r == cur_text_section->sh_num) {
446 /* same section: we can output an absolute value. Note
447 that the TCC compiler behaves differently here because
448 it always outputs a relocation to ease (future) code
449 elimination in the linker */
450 gen_le16(pe->v + sym->jnext - ind - 2);
451 } else {
452 greloc(cur_text_section, sym, ind, R_386_PC16);
453 gen_le16(pe->v - 2);
454 }
455 } else {
456 /* put an empty PC32 relocation */
457 put_elf_reloc(symtab_section, cur_text_section,
458 ind, R_386_PC16, 0);
459 gen_le16(pe->v - 2);
460 }
461 }
462 #endif
463
464 /* generate the modrm operand */
465 static inline void asm_modrm(int reg, Operand *op)
466 {
467 int mod, reg1, reg2, sib_reg1;
468
469 if (op->type & (OP_REG | OP_MMX | OP_SSE)) {
470 g(0xc0 + (reg << 3) + op->reg);
471 } else if (op->reg == -1 && op->reg2 == -1) {
472 /* displacement only */
473 #ifdef I386_ASM_16
474 if (tcc_state->seg_size == 16) {
475 g(0x06 + (reg << 3));
476 gen_expr16(&op->e);
477 } else if (tcc_state->seg_size == 32)
478 #endif
479 {
480 g(0x05 + (reg << 3));
481 gen_expr32(&op->e);
482 }
483 } else {
484 sib_reg1 = op->reg;
485 /* fist compute displacement encoding */
486 if (sib_reg1 == -1) {
487 sib_reg1 = 5;
488 mod = 0x00;
489 } else if (op->e.v == 0 && !op->e.sym && op->reg != 5) {
490 mod = 0x00;
491 } else if (op->e.v == (int8_t)op->e.v && !op->e.sym) {
492 mod = 0x40;
493 } else {
494 mod = 0x80;
495 }
496 /* compute if sib byte needed */
497 reg1 = op->reg;
498 if (op->reg2 != -1)
499 reg1 = 4;
500 #ifdef I386_ASM_16
501 if (tcc_state->seg_size == 32) {
502 #endif
503 g(mod + (reg << 3) + reg1);
504 if (reg1 == 4) {
505 /* add sib byte */
506 reg2 = op->reg2;
507 if (reg2 == -1)
508 reg2 = 4; /* indicate no index */
509 g((op->shift << 6) + (reg2 << 3) + sib_reg1);
510 }
511 #ifdef I386_ASM_16
512 } else if (tcc_state->seg_size == 16) {
513 /* edi = 7, esi = 6 --> di = 5, si = 4 */
514 if ((reg1 == 6) || (reg1 == 7)) {
515 reg1 -= 2;
516 /* ebx = 3 --> bx = 7 */
517 } else if (reg1 == 3) {
518 reg1 = 7;
519 /* o32 = 5 --> o16 = 6 */
520 } else if (reg1 == 5) {
521 reg1 = 6;
522 /* sib not valid in 16-bit mode */
523 } else if (reg1 == 4) {
524 reg2 = op->reg2;
525 /* bp + si + offset */
526 if ((sib_reg1 == 5) && (reg2 == 6)) {
527 reg1 = 2;
528 /* bp + di + offset */
529 } else if ((sib_reg1 == 5) && (reg2 == 7)) {
530 reg1 = 3;
531 /* bx + si + offset */
532 } else if ((sib_reg1 == 3) && (reg2 == 6)) {
533 reg1 = 0;
534 /* bx + di + offset */
535 } else if ((sib_reg1 == 3) && (reg2 == 7)) {
536 reg1 = 1;
537 } else {
538 error("invalid effective address");
539 }
540 if (op->e.v == 0)
541 mod = 0;
542 } else {
543 error("invalid register");
544 }
545 g(mod + (reg << 3) + reg1);
546 }
547 #endif
548 /* add offset */
549 if (mod == 0x40) {
550 g(op->e.v);
551 } else if (mod == 0x80 || op->reg == -1) {
552 #ifdef I386_ASM_16
553 if (tcc_state->seg_size == 16)
554 gen_expr16(&op->e);
555 else if (tcc_state->seg_size == 32)
556 #endif
557 gen_expr32(&op->e);
558 }
559 }
560 }
561
562 ST_FUNC void asm_opcode(TCCState *s1, int opcode)
563 {
564 const ASMInstr *pa;
565 int i, modrm_index, reg, v, op1, is_short_jmp, seg_prefix;
566 int nb_ops, s;
567 Operand ops[MAX_OPERANDS], *pop;
568 int op_type[3]; /* decoded op type */
569 #ifdef I386_ASM_16
570 static int a32 = 0, o32 = 0, addr32 = 0, data32 = 0;
571 #endif
572
573 /* get operands */
574 pop = ops;
575 nb_ops = 0;
576 seg_prefix = 0;
577 for(;;) {
578 if (tok == ';' || tok == TOK_LINEFEED)
579 break;
580 if (nb_ops >= MAX_OPERANDS) {
581 error("incorrect number of operands");
582 }
583 parse_operand(s1, pop);
584 if (tok == ':') {
585 if (pop->type != OP_SEG || seg_prefix)
586 error("incorrect prefix");
587 seg_prefix = segment_prefixes[pop->reg];
588 next();
589 parse_operand(s1, pop);
590 #ifndef I386_ASM_16
591 if (!(pop->type & OP_EA)) {
592 error("segment prefix must be followed by memory reference");
593 }
594 #endif
595 }
596 pop++;
597 nb_ops++;
598 if (tok != ',')
599 break;
600 next();
601 }
602
603 is_short_jmp = 0;
604 s = 0; /* avoid warning */
605
606 /* optimize matching by using a lookup table (no hashing is needed
607 !) */
608 for(pa = asm_instrs; pa->sym != 0; pa++) {
609 s = 0;
610 if (pa->instr_type & OPC_FARITH) {
611 v = opcode - pa->sym;
612 if (!((unsigned)v < 8 * 6 && (v % 6) == 0))
613 continue;
614 } else if (pa->instr_type & OPC_ARITH) {
615 if (!(opcode >= pa->sym && opcode < pa->sym + 8*NBWLX))
616 continue;
617 s = (opcode - pa->sym) % NBWLX;
618 } else if (pa->instr_type & OPC_SHIFT) {
619 if (!(opcode >= pa->sym && opcode < pa->sym + 7*NBWLX))
620 continue;
621 s = (opcode - pa->sym) % NBWLX;
622 } else if (pa->instr_type & OPC_TEST) {
623 if (!(opcode >= pa->sym && opcode < pa->sym + NB_TEST_OPCODES))
624 continue;
625 } else if (pa->instr_type & OPC_B) {
626 if (!(opcode >= pa->sym && opcode < pa->sym + NBWLX))
627 continue;
628 s = opcode - pa->sym;
629 } else if (pa->instr_type & OPC_WLX) {
630 if (!(opcode >= pa->sym && opcode < pa->sym + NBWLX-1))
631 continue;
632 s = opcode - pa->sym + 1;
633 } else {
634 if (pa->sym != opcode)
635 continue;
636 }
637 if (pa->nb_ops != nb_ops)
638 continue;
639 /* now decode and check each operand */
640 for(i = 0; i < nb_ops; i++) {
641 int op1, op2;
642 op1 = pa->op_type[i];
643 op2 = op1 & 0x1f;
644 switch(op2) {
645 case OPT_IM:
646 v = OP_IM8 | OP_IM16 | OP_IM32 | OP_IM64;
647 break;
648 case OPT_REG:
649 v = OP_REG8 | OP_REG16 | OP_REG32 | OP_REG64;
650 break;
651 case OPT_REGW:
652 v = OP_REG16 | OP_REG32 | OP_REG64;
653 break;
654 case OPT_IMW:
655 v = OP_IM16 | OP_IM32 | OP_IM64;
656 break;
657 #ifdef TCC_TARGET_X86_64
658 case OPT_IMNO64:
659 v = OP_IM16 | OP_IM32;
660 break;
661 #endif
662 default:
663 v = 1 << op2;
664 break;
665 }
666 if (op1 & OPT_EA)
667 v |= OP_EA;
668 op_type[i] = v;
669 if ((ops[i].type & v) == 0)
670 goto next;
671 }
672 /* all is matching ! */
673 break;
674 next: ;
675 }
676 if (pa->sym == 0) {
677 if (opcode >= TOK_ASM_first && opcode <= TOK_ASM_last) {
678 int b;
679 b = op0_codes[opcode - TOK_ASM_first];
680 #ifdef I386_ASM_16
681 if (opcode == TOK_ASM_o32) {
682 if (s1->seg_size == 32)
683 error("incorrect prefix");
684 else
685 o32 = data32 = 1;
686 } else if (opcode == TOK_ASM_a32) {
687 if (s1->seg_size == 32)
688 error("incorrect prefix");
689 else
690 a32 = addr32 = 1;
691 }
692 #endif
693 if (b & 0xff00)
694 g(b >> 8);
695 g(b);
696 return;
697 } else {
698 error("unknown opcode '%s'",
699 get_tok_str(opcode, NULL));
700 }
701 }
702 /* if the size is unknown, then evaluate it (OPC_B or OPC_WL case) */
703 if (s == NBWLX-1) {
704 for(i = 0; s == NBWLX-1 && i < nb_ops; i++) {
705 if ((ops[i].type & OP_REG) && !(op_type[i] & (OP_CL | OP_DX)))
706 s = reg_to_size[ops[i].type & OP_REG];
707 }
708 if (s == NBWLX-1) {
709 if ((opcode == TOK_ASM_push || opcode == TOK_ASM_pop) &&
710 (ops[0].type & (OP_SEG | OP_IM8S | OP_IM32 | OP_IM64)))
711 s = 2;
712 else
713 error("cannot infer opcode suffix");
714 }
715 }
716
717 #ifdef I386_ASM_16
718 for(i = 0; i < nb_ops; i++) {
719 if (ops[i].type & OP_REG32) {
720 if (s1->seg_size == 16)
721 o32 = 1;
722 } else if (!(ops[i].type & OP_REG32)) {
723 if (s1->seg_size == 32)
724 o32 = 1;
725 }
726 }
727
728
729 if (s == 1 || (pa->instr_type & OPC_D16)) {
730 if (s1->seg_size == 32)
731 o32 = 1;
732 } else if (s == 2) {
733 if (s1->seg_size == 16) {
734 if (!(pa->instr_type & OPC_D16))
735 o32 = 1;
736 }
737 }
738
739 /* generate a16/a32 prefix if needed */
740 if ((a32 == 1) && (addr32 == 0))
741 g(0x67);
742 /* generate o16/o32 prefix if needed */
743 if ((o32 == 1) && (data32 == 0))
744 g(0x66);
745
746 addr32 = data32 = 0;
747 #else
748 /* generate data16 prefix if needed */
749 if (s == 1 || (pa->instr_type & OPC_D16))
750 g(0x66);
751 #ifdef TCC_TARGET_X86_64
752 else if (s == 3) {
753 /* generate REX prefix */
754 if ((opcode != TOK_ASM_push && opcode != TOK_ASM_pop)
755 || !(ops[0].type & OP_REG64))
756 g(0x48);
757 }
758 #endif
759 #endif
760
761 /* now generates the operation */
762 if (pa->instr_type & OPC_FWAIT)
763 g(0x9b);
764 if (seg_prefix)
765 g(seg_prefix);
766
767 v = pa->opcode;
768 if ((v == 0x69 || v == 0x6b) && nb_ops == 2) {
769 /* kludge for imul $im, %reg */
770 nb_ops = 3;
771 ops[2] = ops[1];
772 op_type[2] = op_type[1];
773 } else if (v == 0xcd && ops[0].e.v == 3 && !ops[0].e.sym) {
774 v--; /* int $3 case */
775 nb_ops = 0;
776 } else if ((v == 0x06 || v == 0x07)) {
777 if (ops[0].reg >= 4) {
778 /* push/pop %fs or %gs */
779 v = 0x0fa0 + (v - 0x06) + ((ops[0].reg - 4) << 3);
780 } else {
781 v += ops[0].reg << 3;
782 }
783 nb_ops = 0;
784 } else if (v <= 0x05) {
785 /* arith case */
786 v += ((opcode - TOK_ASM_addb) / NBWLX) << 3;
787 } else if ((pa->instr_type & (OPC_FARITH | OPC_MODRM)) == OPC_FARITH) {
788 /* fpu arith case */
789 v += ((opcode - pa->sym) / 6) << 3;
790 }
791 if (pa->instr_type & OPC_REG) {
792 for(i = 0; i < nb_ops; i++) {
793 if (op_type[i] & (OP_REG | OP_ST)) {
794 v += ops[i].reg;
795 break;
796 }
797 }
798 /* mov $im, %reg case */
799 if (pa->opcode == 0xb0 && s >= 1)
800 v += 7;
801 }
802 if (pa->instr_type & OPC_B)
803 v += s >= 1;
804 if (pa->instr_type & OPC_TEST)
805 v += test_bits[opcode - pa->sym];
806 if (pa->instr_type & OPC_SHORTJMP) {
807 Sym *sym;
808 int jmp_disp;
809
810 /* see if we can really generate the jump with a byte offset */
811 sym = ops[0].e.sym;
812 if (!sym)
813 goto no_short_jump;
814 if (sym->r != cur_text_section->sh_num)
815 goto no_short_jump;
816 jmp_disp = ops[0].e.v + sym->jnext - ind - 2;
817 if (jmp_disp == (int8_t)jmp_disp) {
818 /* OK to generate jump */
819 is_short_jmp = 1;
820 ops[0].e.v = jmp_disp;
821 } else {
822 no_short_jump:
823 if (pa->instr_type & OPC_JMP) {
824 /* long jump will be allowed. need to modify the
825 opcode slightly */
826 if (v == 0xeb)
827 v = 0xe9;
828 else
829 v += 0x0f10;
830 } else {
831 error("invalid displacement");
832 }
833 }
834 }
835 op1 = v >> 8;
836 if (op1)
837 g(op1);
838 g(v);
839
840 /* search which operand will used for modrm */
841 modrm_index = 0;
842 if (pa->instr_type & OPC_SHIFT) {
843 reg = (opcode - pa->sym) / NBWLX;
844 if (reg == 6)
845 reg = 7;
846 } else if (pa->instr_type & OPC_ARITH) {
847 reg = (opcode - pa->sym) / NBWLX;
848 } else if (pa->instr_type & OPC_FARITH) {
849 reg = (opcode - pa->sym) / 6;
850 } else {
851 reg = (pa->instr_type >> OPC_GROUP_SHIFT) & 7;
852 }
853 if (pa->instr_type & OPC_MODRM) {
854 /* first look for an ea operand */
855 for(i = 0;i < nb_ops; i++) {
856 if (op_type[i] & OP_EA)
857 goto modrm_found;
858 }
859 /* then if not found, a register or indirection (shift instructions) */
860 for(i = 0;i < nb_ops; i++) {
861 if (op_type[i] & (OP_REG | OP_MMX | OP_SSE | OP_INDIR))
862 goto modrm_found;
863 }
864 #ifdef ASM_DEBUG
865 error("bad op table");
866 #endif
867 modrm_found:
868 modrm_index = i;
869 /* if a register is used in another operand then it is
870 used instead of group */
871 for(i = 0;i < nb_ops; i++) {
872 v = op_type[i];
873 if (i != modrm_index &&
874 (v & (OP_REG | OP_MMX | OP_SSE | OP_CR | OP_TR | OP_DB | OP_SEG))) {
875 reg = ops[i].reg;
876 break;
877 }
878 }
879
880 asm_modrm(reg, &ops[modrm_index]);
881 }
882
883 /* emit constants */
884 #ifndef TCC_TARGET_X86_64
885 if (pa->opcode == 0x9a || pa->opcode == 0xea) {
886 /* ljmp or lcall kludge */
887 #ifdef I386_ASM_16
888 if (s1->seg_size == 16 && o32 == 0)
889 gen_expr16(&ops[1].e);
890 else
891 #endif
892 gen_expr32(&ops[1].e);
893 if (ops[0].e.sym)
894 error("cannot relocate");
895 gen_le16(ops[0].e.v);
896 return;
897 }
898 #endif
899 for(i = 0;i < nb_ops; i++) {
900 v = op_type[i];
901 if (v & (OP_IM8 | OP_IM16 | OP_IM32 | OP_IM64 | OP_IM8S | OP_ADDR)) {
902 /* if multiple sizes are given it means we must look
903 at the op size */
904 if ((v | OP_IM8 | OP_IM64) == (OP_IM8 | OP_IM16 | OP_IM32 | OP_IM64)) {
905 if (s == 0)
906 v = OP_IM8;
907 else if (s == 1)
908 v = OP_IM16;
909 else if (s == 2 || (v & OP_IM64) == 0)
910 v = OP_IM32;
911 else
912 v = OP_IM64;
913 }
914 if (v & (OP_IM8 | OP_IM8S)) {
915 if (ops[i].e.sym)
916 goto error_relocate;
917 g(ops[i].e.v);
918 } else if (v & OP_IM16) {
919 #ifdef I386_ASM_16
920 if (s1->seg_size == 16)
921 gen_expr16(&ops[i].e);
922 else
923 #endif
924 if (ops[i].e.sym)
925 error_relocate:
926 error("cannot relocate");
927 else
928 gen_le16(ops[i].e.v);
929 } else {
930 if (pa->instr_type & (OPC_JMP | OPC_SHORTJMP)) {
931 if (is_short_jmp)
932 g(ops[i].e.v);
933 #ifdef I386_ASM_16
934 else if (s1->seg_size == 16)
935 gen_disp16(&ops[i].e);
936 #endif
937 else
938 gen_disp32(&ops[i].e);
939 } else {
940 #ifdef I386_ASM_16
941 if (s1->seg_size == 16 && !((o32 == 1) && (v & OP_IM32)))
942 gen_expr16(&ops[i].e);
943 else
944 #endif
945 #ifdef TCC_TARGET_X86_64
946 if (v & OP_IM64)
947 gen_expr64(&ops[i].e);
948 else
949 #endif
950 gen_expr32(&ops[i].e);
951 }
952 }
953 #ifdef I386_ASM_16
954 } else if (v & (OP_REG16 | OP_REG32)) {
955 if (pa->instr_type & (OPC_JMP | OPC_SHORTJMP)) {
956 /* jmp $r */
957 g(0xE0 + ops[i].reg);
958 }
959 #endif
960 #ifdef TCC_TARGET_X86_64
961 } else if (v & (OP_REG32 | OP_REG64)) {
962 if (pa->instr_type & (OPC_JMP | OPC_SHORTJMP)) {
963 /* jmp $r */
964 g(0xE0 + ops[i].reg);
965 }
966 #endif
967 }
968 }
969 #ifdef I386_ASM_16
970 a32 = o32 = 0;
971 #endif
972 }
973
974 /* return the constraint priority (we allocate first the lowest
975 numbered constraints) */
976 static inline int constraint_priority(const char *str)
977 {
978 int priority, c, pr;
979
980 /* we take the lowest priority */
981 priority = 0;
982 for(;;) {
983 c = *str;
984 if (c == '\0')
985 break;
986 str++;
987 switch(c) {
988 case 'A':
989 pr = 0;
990 break;
991 case 'a':
992 case 'b':
993 case 'c':
994 case 'd':
995 case 'S':
996 case 'D':
997 pr = 1;
998 break;
999 case 'q':
1000 pr = 2;
1001 break;
1002 case 'r':
1003 pr = 3;
1004 break;
1005 case 'N':
1006 case 'M':
1007 case 'I':
1008 case 'i':
1009 case 'm':
1010 case 'g':
1011 pr = 4;
1012 break;
1013 default:
1014 error("unknown constraint '%c'", c);
1015 pr = 0;
1016 }
1017 if (pr > priority)
1018 priority = pr;
1019 }
1020 return priority;
1021 }
1022
1023 static const char *skip_constraint_modifiers(const char *p)
1024 {
1025 while (*p == '=' || *p == '&' || *p == '+' || *p == '%')
1026 p++;
1027 return p;
1028 }
1029
1030 #define REG_OUT_MASK 0x01
1031 #define REG_IN_MASK 0x02
1032
1033 #define is_reg_allocated(reg) (regs_allocated[reg] & reg_mask)
1034
1035 ST_FUNC void asm_compute_constraints(ASMOperand *operands,
1036 int nb_operands, int nb_outputs,
1037 const uint8_t *clobber_regs,
1038 int *pout_reg)
1039 {
1040 ASMOperand *op;
1041 int sorted_op[MAX_ASM_OPERANDS];
1042 int i, j, k, p1, p2, tmp, reg, c, reg_mask;
1043 const char *str;
1044 uint8_t regs_allocated[NB_ASM_REGS];
1045
1046 /* init fields */
1047 for(i=0;i<nb_operands;i++) {
1048 op = &operands[i];
1049 op->input_index = -1;
1050 op->ref_index = -1;
1051 op->reg = -1;
1052 op->is_memory = 0;
1053 op->is_rw = 0;
1054 }
1055 /* compute constraint priority and evaluate references to output
1056 constraints if input constraints */
1057 for(i=0;i<nb_operands;i++) {
1058 op = &operands[i];
1059 str = op->constraint;
1060 str = skip_constraint_modifiers(str);
1061 if (isnum(*str) || *str == '[') {
1062 /* this is a reference to another constraint */
1063 k = find_constraint(operands, nb_operands, str, NULL);
1064 if ((unsigned)k >= i || i < nb_outputs)
1065 error("invalid reference in constraint %d ('%s')",
1066 i, str);
1067 op->ref_index = k;
1068 if (operands[k].input_index >= 0)
1069 error("cannot reference twice the same operand");
1070 operands[k].input_index = i;
1071 op->priority = 5;
1072 } else {
1073 op->priority = constraint_priority(str);
1074 }
1075 }
1076
1077 /* sort operands according to their priority */
1078 for(i=0;i<nb_operands;i++)
1079 sorted_op[i] = i;
1080 for(i=0;i<nb_operands - 1;i++) {
1081 for(j=i+1;j<nb_operands;j++) {
1082 p1 = operands[sorted_op[i]].priority;
1083 p2 = operands[sorted_op[j]].priority;
1084 if (p2 < p1) {
1085 tmp = sorted_op[i];
1086 sorted_op[i] = sorted_op[j];
1087 sorted_op[j] = tmp;
1088 }
1089 }
1090 }
1091
1092 for(i = 0;i < NB_ASM_REGS; i++) {
1093 if (clobber_regs[i])
1094 regs_allocated[i] = REG_IN_MASK | REG_OUT_MASK;
1095 else
1096 regs_allocated[i] = 0;
1097 }
1098 /* esp cannot be used */
1099 regs_allocated[4] = REG_IN_MASK | REG_OUT_MASK;
1100 /* ebp cannot be used yet */
1101 regs_allocated[5] = REG_IN_MASK | REG_OUT_MASK;
1102
1103 /* allocate registers and generate corresponding asm moves */
1104 for(i=0;i<nb_operands;i++) {
1105 j = sorted_op[i];
1106 op = &operands[j];
1107 str = op->constraint;
1108 /* no need to allocate references */
1109 if (op->ref_index >= 0)
1110 continue;
1111 /* select if register is used for output, input or both */
1112 if (op->input_index >= 0) {
1113 reg_mask = REG_IN_MASK | REG_OUT_MASK;
1114 } else if (j < nb_outputs) {
1115 reg_mask = REG_OUT_MASK;
1116 } else {
1117 reg_mask = REG_IN_MASK;
1118 }
1119 try_next:
1120 c = *str++;
1121 switch(c) {
1122 case '=':
1123 goto try_next;
1124 case '+':
1125 op->is_rw = 1;
1126 /* FALL THRU */
1127 case '&':
1128 if (j >= nb_outputs)
1129 error("'%c' modifier can only be applied to outputs", c);
1130 reg_mask = REG_IN_MASK | REG_OUT_MASK;
1131 goto try_next;
1132 case 'A':
1133 /* allocate both eax and edx */
1134 if (is_reg_allocated(TREG_XAX) ||
1135 is_reg_allocated(TREG_XDX))
1136 goto try_next;
1137 op->is_llong = 1;
1138 op->reg = TREG_XAX;
1139 regs_allocated[TREG_XAX] |= reg_mask;
1140 regs_allocated[TREG_XDX] |= reg_mask;
1141 break;
1142 case 'a':
1143 reg = TREG_XAX;
1144 goto alloc_reg;
1145 case 'b':
1146 reg = 3;
1147 goto alloc_reg;
1148 case 'c':
1149 reg = TREG_XCX;
1150 goto alloc_reg;
1151 case 'd':
1152 reg = TREG_XDX;
1153 goto alloc_reg;
1154 case 'S':
1155 reg = 6;
1156 goto alloc_reg;
1157 case 'D':
1158 reg = 7;
1159 alloc_reg:
1160 if (is_reg_allocated(reg))
1161 goto try_next;
1162 goto reg_found;
1163 case 'q':
1164 /* eax, ebx, ecx or edx */
1165 for(reg = 0; reg < 4; reg++) {
1166 if (!is_reg_allocated(reg))
1167 goto reg_found;
1168 }
1169 goto try_next;
1170 case 'r':
1171 /* any general register */
1172 for(reg = 0; reg < 8; reg++) {
1173 if (!is_reg_allocated(reg))
1174 goto reg_found;
1175 }
1176 goto try_next;
1177 reg_found:
1178 /* now we can reload in the register */
1179 op->is_llong = 0;
1180 op->reg = reg;
1181 regs_allocated[reg] |= reg_mask;
1182 break;
1183 case 'i':
1184 if (!((op->vt->r & (VT_VALMASK | VT_LVAL)) == VT_CONST))
1185 goto try_next;
1186 break;
1187 case 'I':
1188 case 'N':
1189 case 'M':
1190 if (!((op->vt->r & (VT_VALMASK | VT_LVAL | VT_SYM)) == VT_CONST))
1191 goto try_next;
1192 break;
1193 case 'm':
1194 case 'g':
1195 /* nothing special to do because the operand is already in
1196 memory, except if the pointer itself is stored in a
1197 memory variable (VT_LLOCAL case) */
1198 /* XXX: fix constant case */
1199 /* if it is a reference to a memory zone, it must lie
1200 in a register, so we reserve the register in the
1201 input registers and a load will be generated
1202 later */
1203 if (j < nb_outputs || c == 'm') {
1204 if ((op->vt->r & VT_VALMASK) == VT_LLOCAL) {
1205 /* any general register */
1206 for(reg = 0; reg < 8; reg++) {
1207 if (!(regs_allocated[reg] & REG_IN_MASK))
1208 goto reg_found1;
1209 }
1210 goto try_next;
1211 reg_found1:
1212 /* now we can reload in the register */
1213 regs_allocated[reg] |= REG_IN_MASK;
1214 op->reg = reg;
1215 op->is_memory = 1;
1216 }
1217 }
1218 break;
1219 default:
1220 error("asm constraint %d ('%s') could not be satisfied",
1221 j, op->constraint);
1222 break;
1223 }
1224 /* if a reference is present for that operand, we assign it too */
1225 if (op->input_index >= 0) {
1226 operands[op->input_index].reg = op->reg;
1227 operands[op->input_index].is_llong = op->is_llong;
1228 }
1229 }
1230
1231 /* compute out_reg. It is used to store outputs registers to memory
1232 locations references by pointers (VT_LLOCAL case) */
1233 *pout_reg = -1;
1234 for(i=0;i<nb_operands;i++) {
1235 op = &operands[i];
1236 if (op->reg >= 0 &&
1237 (op->vt->r & VT_VALMASK) == VT_LLOCAL &&
1238 !op->is_memory) {
1239 for(reg = 0; reg < 8; reg++) {
1240 if (!(regs_allocated[reg] & REG_OUT_MASK))
1241 goto reg_found2;
1242 }
1243 error("could not find free output register for reloading");
1244 reg_found2:
1245 *pout_reg = reg;
1246 break;
1247 }
1248 }
1249
1250 /* print sorted constraints */
1251 #ifdef ASM_DEBUG
1252 for(i=0;i<nb_operands;i++) {
1253 j = sorted_op[i];
1254 op = &operands[j];
1255 printf("%%%d [%s]: \"%s\" r=0x%04x reg=%d\n",
1256 j,
1257 op->id ? get_tok_str(op->id, NULL) : "",
1258 op->constraint,
1259 op->vt->r,
1260 op->reg);
1261 }
1262 if (*pout_reg >= 0)
1263 printf("out_reg=%d\n", *pout_reg);
1264 #endif
1265 }
1266
1267 ST_FUNC void subst_asm_operand(CString *add_str,
1268 SValue *sv, int modifier)
1269 {
1270 int r, reg, size, val;
1271 char buf[64];
1272
1273 r = sv->r;
1274 if ((r & VT_VALMASK) == VT_CONST) {
1275 if (!(r & VT_LVAL) && modifier != 'c' && modifier != 'n')
1276 cstr_ccat(add_str, '$');
1277 if (r & VT_SYM) {
1278 cstr_cat(add_str, get_tok_str(sv->sym->v, NULL));
1279 if (sv->c.i != 0) {
1280 cstr_ccat(add_str, '+');
1281 } else {
1282 return;
1283 }
1284 }
1285 val = sv->c.i;
1286 if (modifier == 'n')
1287 val = -val;
1288 snprintf(buf, sizeof(buf), "%d", sv->c.i);
1289 cstr_cat(add_str, buf);
1290 } else if ((r & VT_VALMASK) == VT_LOCAL) {
1291 snprintf(buf, sizeof(buf), "%d(%%ebp)", sv->c.i);
1292 cstr_cat(add_str, buf);
1293 } else if (r & VT_LVAL) {
1294 reg = r & VT_VALMASK;
1295 if (reg >= VT_CONST)
1296 error("internal compiler error");
1297 snprintf(buf, sizeof(buf), "(%%%s)",
1298 get_tok_str(TOK_ASM_eax + reg, NULL));
1299 cstr_cat(add_str, buf);
1300 } else {
1301 /* register case */
1302 reg = r & VT_VALMASK;
1303 if (reg >= VT_CONST)
1304 error("internal compiler error");
1305
1306 /* choose register operand size */
1307 if ((sv->type.t & VT_BTYPE) == VT_BYTE)
1308 size = 1;
1309 else if ((sv->type.t & VT_BTYPE) == VT_SHORT)
1310 size = 2;
1311 #ifdef TCC_TARGET_X86_64
1312 else if ((sv->type.t & VT_BTYPE) == VT_LLONG)
1313 size = 8;
1314 #endif
1315 else
1316 size = 4;
1317 if (size == 1 && reg >= 4)
1318 size = 4;
1319
1320 if (modifier == 'b') {
1321 if (reg >= 4)
1322 error("cannot use byte register");
1323 size = 1;
1324 } else if (modifier == 'h') {
1325 if (reg >= 4)
1326 error("cannot use byte register");
1327 size = -1;
1328 } else if (modifier == 'w') {
1329 size = 2;
1330 #ifdef TCC_TARGET_X86_64
1331 } else if (modifier == 'q') {
1332 size = 8;
1333 #endif
1334 }
1335
1336 switch(size) {
1337 case -1:
1338 reg = TOK_ASM_ah + reg;
1339 break;
1340 case 1:
1341 reg = TOK_ASM_al + reg;
1342 break;
1343 case 2:
1344 reg = TOK_ASM_ax + reg;
1345 break;
1346 default:
1347 reg = TOK_ASM_eax + reg;
1348 break;
1349 #ifdef TCC_TARGET_X86_64
1350 case 8:
1351 reg = TOK_ASM_rax + reg;
1352 break;
1353 #endif
1354 }
1355 snprintf(buf, sizeof(buf), "%%%s", get_tok_str(reg, NULL));
1356 cstr_cat(add_str, buf);
1357 }
1358 }
1359
1360 /* generate prolog and epilog code for asm statment */
1361 ST_FUNC void asm_gen_code(ASMOperand *operands, int nb_operands,
1362 int nb_outputs, int is_output,
1363 uint8_t *clobber_regs,
1364 int out_reg)
1365 {
1366 uint8_t regs_allocated[NB_ASM_REGS];
1367 ASMOperand *op;
1368 int i, reg;
1369 static uint8_t reg_saved[NB_SAVED_REGS] = { 3, 6, 7 };
1370
1371 /* mark all used registers */
1372 memcpy(regs_allocated, clobber_regs, sizeof(regs_allocated));
1373 for(i = 0; i < nb_operands;i++) {
1374 op = &operands[i];
1375 if (op->reg >= 0)
1376 regs_allocated[op->reg] = 1;
1377 }
1378 if (!is_output) {
1379 /* generate reg save code */
1380 for(i = 0; i < NB_SAVED_REGS; i++) {
1381 reg = reg_saved[i];
1382 if (regs_allocated[reg]) {
1383 #ifdef I386_ASM_16
1384 if (tcc_state->seg_size == 16)
1385 g(0x66);
1386 #endif
1387 g(0x50 + reg);
1388 }
1389 }
1390
1391 /* generate load code */
1392 for(i = 0; i < nb_operands; i++) {
1393 op = &operands[i];
1394 if (op->reg >= 0) {
1395 if ((op->vt->r & VT_VALMASK) == VT_LLOCAL &&
1396 op->is_memory) {
1397 /* memory reference case (for both input and
1398 output cases) */
1399 SValue sv;
1400 sv = *op->vt;
1401 sv.r = (sv.r & ~VT_VALMASK) | VT_LOCAL;
1402 load(op->reg, &sv);
1403 } else if (i >= nb_outputs || op->is_rw) {
1404 /* load value in register */
1405 load(op->reg, op->vt);
1406 if (op->is_llong) {
1407 SValue sv;
1408 sv = *op->vt;
1409 sv.c.ul += 4;
1410 load(TREG_XDX, &sv);
1411 }
1412 }
1413 }
1414 }
1415 } else {
1416 /* generate save code */
1417 for(i = 0 ; i < nb_outputs; i++) {
1418 op = &operands[i];
1419 if (op->reg >= 0) {
1420 if ((op->vt->r & VT_VALMASK) == VT_LLOCAL) {
1421 if (!op->is_memory) {
1422 SValue sv;
1423 sv = *op->vt;
1424 sv.r = (sv.r & ~VT_VALMASK) | VT_LOCAL;
1425 load(out_reg, &sv);
1426
1427 sv.r = (sv.r & ~VT_VALMASK) | out_reg;
1428 store(op->reg, &sv);
1429 }
1430 } else {
1431 store(op->reg, op->vt);
1432 if (op->is_llong) {
1433 SValue sv;
1434 sv = *op->vt;
1435 sv.c.ul += 4;
1436 store(TREG_XDX, &sv);
1437 }
1438 }
1439 }
1440 }
1441 /* generate reg restore code */
1442 for(i = NB_SAVED_REGS - 1; i >= 0; i--) {
1443 reg = reg_saved[i];
1444 if (regs_allocated[reg]) {
1445 #ifdef I386_ASM_16
1446 if (tcc_state->seg_size == 16)
1447 g(0x66);
1448 #endif
1449 g(0x58 + reg);
1450 }
1451 }
1452 }
1453 }
1454
1455 ST_FUNC void asm_clobber(uint8_t *clobber_regs, const char *str)
1456 {
1457 int reg;
1458 TokenSym *ts;
1459
1460 if (!strcmp(str, "memory") ||
1461 !strcmp(str, "cc"))
1462 return;
1463 ts = tok_alloc(str, strlen(str));
1464 reg = ts->tok;
1465 if (reg >= TOK_ASM_eax && reg <= TOK_ASM_edi) {
1466 reg -= TOK_ASM_eax;
1467 } else if (reg >= TOK_ASM_ax && reg <= TOK_ASM_di) {
1468 reg -= TOK_ASM_ax;
1469 #ifdef TCC_TARGET_X86_64
1470 } else if (reg >= TOK_ASM_rax && reg <= TOK_ASM_rdi) {
1471 reg -= TOK_ASM_rax;
1472 #endif
1473 } else {
1474 error("invalid clobber register '%s'", str);
1475 }
1476 clobber_regs[reg] = 1;
1477 }
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