2 * i386 specific functions for TCC assembler
4 * Copyright (c) 2001, 2002 Fabrice Bellard
5 * Copyright (c) 2009 Frédéric Feret (x86_64 support)
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 // #define NB_ASM_REGS 8
25 #define MAX_OPERANDS 3
26 #define NB_SAVED_REGS 3
28 #define TOK_ASM_first TOK_ASM_clc
29 #define TOK_ASM_last TOK_ASM_emms
31 #define OPC_JMP 0x01 /* jmp operand */
32 #define OPC_B 0x02 /* only used with OPC_WL */
33 #define OPC_WL 0x04 /* accepts w, l or no suffix */
34 #define OPC_BWL (OPC_B | OPC_WL) /* accepts b, w, l or no suffix */
35 #define OPC_REG 0x08 /* register is added to opcode */
36 #define OPC_MODRM 0x10 /* modrm encoding */
37 #define OPC_FWAIT 0x20 /* add fwait opcode */
38 #define OPC_TEST 0x40 /* test opcodes */
39 #define OPC_SHIFT 0x80 /* shift opcodes */
40 #define OPC_D16 0x0100 /* generate data16 prefix */
41 #define OPC_ARITH 0x0200 /* arithmetic opcodes */
42 #define OPC_SHORTJMP 0x0400 /* short jmp operand */
43 #define OPC_FARITH 0x0800 /* FPU arithmetic opcodes */
44 #ifdef TCC_TARGET_X86_64
45 # define OPC_WLQ 0x1000 /* accepts w, l, q or no suffix */
46 # define OPC_BWLQ (OPC_B | OPC_WLQ) /* accepts b, w, l, q or no suffix */
47 # define OPC_WLX OPC_WLQ
49 # define OPC_WLX OPC_WL
52 #define OPC_GROUP_SHIFT 13
54 /* in order to compress the operand type, we use specific operands and
57 OPT_REG8
=0, /* warning: value is hardcoded from TOK_ASM_xxx */
58 OPT_REG16
, /* warning: value is hardcoded from TOK_ASM_xxx */
59 OPT_REG32
, /* warning: value is hardcoded from TOK_ASM_xxx */
60 #ifdef TCC_TARGET_X86_64
61 OPT_REG64
, /* warning: value is hardcoded from TOK_ASM_xxx */
63 OPT_MMX
, /* warning: value is hardcoded from TOK_ASM_xxx */
64 OPT_SSE
, /* warning: value is hardcoded from TOK_ASM_xxx */
65 OPT_CR
, /* warning: value is hardcoded from TOK_ASM_xxx */
66 OPT_TR
, /* warning: value is hardcoded from TOK_ASM_xxx */
67 OPT_DB
, /* warning: value is hardcoded from TOK_ASM_xxx */
74 #ifdef TCC_TARGET_X86_64
77 OPT_EAX
, /* %al, %ax, %eax or %rax register */
78 OPT_ST0
, /* %st(0) register */
79 OPT_CL
, /* %cl register */
80 OPT_DX
, /* %dx register */
81 OPT_ADDR
, /* OP_EA with only offset */
82 OPT_INDIR
, /* *(expr) */
85 OPT_IM
, /* IM8 | IM16 | IM32 | IM64 */
86 OPT_REG
, /* REG8 | REG16 | REG32 | REG64 */
87 OPT_REGW
, /* REG16 | REG32 | REG64 */
88 OPT_IMW
, /* IM16 | IM32 | IM64 */
89 #ifdef TCC_TARGET_X86_64
90 OPT_IMNO64
, /* IM16 | IM32 */
92 /* can be ored with any OPT_xxx */
96 #define OP_REG8 (1 << OPT_REG8)
97 #define OP_REG16 (1 << OPT_REG16)
98 #define OP_REG32 (1 << OPT_REG32)
99 #define OP_MMX (1 << OPT_MMX)
100 #define OP_SSE (1 << OPT_SSE)
101 #define OP_CR (1 << OPT_CR)
102 #define OP_TR (1 << OPT_TR)
103 #define OP_DB (1 << OPT_DB)
104 #define OP_SEG (1 << OPT_SEG)
105 #define OP_ST (1 << OPT_ST)
106 #define OP_IM8 (1 << OPT_IM8)
107 #define OP_IM8S (1 << OPT_IM8S)
108 #define OP_IM16 (1 << OPT_IM16)
109 #define OP_IM32 (1 << OPT_IM32)
110 #define OP_EAX (1 << OPT_EAX)
111 #define OP_ST0 (1 << OPT_ST0)
112 #define OP_CL (1 << OPT_CL)
113 #define OP_DX (1 << OPT_DX)
114 #define OP_ADDR (1 << OPT_ADDR)
115 #define OP_INDIR (1 << OPT_INDIR)
116 #ifdef TCC_TARGET_X86_64
117 # define OP_REG64 (1 << OPT_REG64)
118 # define OP_IM64 (1 << OPT_IM64)
124 #define OP_EA 0x40000000
125 #define OP_REG (OP_REG8 | OP_REG16 | OP_REG32 | OP_REG64)
127 #ifdef TCC_TARGET_X86_64
128 # define OP_IM OP_IM64
129 # define TREG_XAX TREG_RAX
130 # define TREG_XCX TREG_RCX
131 # define TREG_XDX TREG_RDX
133 # define OP_IM OP_IM32
134 # define TREG_XAX TREG_EAX
135 # define TREG_XCX TREG_ECX
136 # define TREG_XDX TREG_EDX
139 typedef struct ASMInstr
{
144 uint8_t op_type
[MAX_OPERANDS
]; /* see OP_xxx */
147 typedef struct Operand
{
149 int8_t reg
; /* register, -1 if none */
150 int8_t reg2
; /* second register, -1 if none */
155 static const uint8_t reg_to_size
[9] = {
160 #ifdef TCC_TARGET_X86_64
164 0, 0, 1, 0, 2, 0, 0, 0, 3
167 #define NB_TEST_OPCODES 30
169 static const uint8_t test_bits
[NB_TEST_OPCODES
] = {
202 static const uint8_t segment_prefixes
[] = {
211 static const ASMInstr asm_instrs
[] = {
213 #define DEF_ASM_OP0(name, opcode)
214 #define DEF_ASM_OP0L(name, opcode, group, instr_type) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 0 },
215 #define DEF_ASM_OP1(name, opcode, group, instr_type, op0) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 1, { op0 }},
216 #define DEF_ASM_OP2(name, opcode, group, instr_type, op0, op1) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 2, { op0, op1 }},
217 #define DEF_ASM_OP3(name, opcode, group, instr_type, op0, op1, op2) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 3, { op0, op1, op2 }},
218 #ifdef TCC_TARGET_X86_64
219 # include "x86_64-asm.h"
221 # include "i386-asm.h"
227 static const uint16_t op0_codes
[] = {
229 #define DEF_ASM_OP0(x, opcode) opcode,
230 #define DEF_ASM_OP0L(name, opcode, group, instr_type)
231 #define DEF_ASM_OP1(name, opcode, group, instr_type, op0)
232 #define DEF_ASM_OP2(name, opcode, group, instr_type, op0, op1)
233 #define DEF_ASM_OP3(name, opcode, group, instr_type, op0, op1, op2)
234 #ifdef TCC_TARGET_X86_64
235 # include "x86_64-asm.h"
237 # include "i386-asm.h"
241 static inline int get_reg_shift(TCCState
*s1
)
245 if (s1
->seg_size
== 16)
246 error("invalid effective address");
248 v
= asm_int_expr(s1
);
263 expect("1, 2, 4 or 8 constant");
270 static int asm_parse_reg(void)
276 if (tok
>= TOK_ASM_eax
&& tok
<= TOK_ASM_edi
) {
277 reg
= tok
- TOK_ASM_eax
;
278 #ifdef TCC_TARGET_X86_64
279 } else if (tok
>= TOK_ASM_rax
&& tok
<= TOK_ASM_rdi
) {
280 reg
= tok
- TOK_ASM_rax
;
283 } else if (tok
>= TOK_ASM_ax
&& tok
<= TOK_ASM_di
) {
284 reg
= tok
- TOK_ASM_ax
;
294 static void parse_operand(TCCState
*s1
, Operand
*op
)
308 if (tok
>= TOK_ASM_al
&& tok
<= TOK_ASM_db7
) {
309 reg
= tok
- TOK_ASM_al
;
310 op
->type
= 1 << (reg
>> 3); /* WARNING: do not change constant order */
312 if ((op
->type
& OP_REG
) && op
->reg
== TREG_XAX
)
314 else if (op
->type
== OP_REG8
&& op
->reg
== TREG_XCX
)
316 else if (op
->type
== OP_REG16
&& op
->reg
== TREG_XDX
)
318 } else if (tok
>= TOK_ASM_dr0
&& tok
<= TOK_ASM_dr7
) {
320 op
->reg
= tok
- TOK_ASM_dr0
;
321 } else if (tok
>= TOK_ASM_es
&& tok
<= TOK_ASM_gs
) {
323 op
->reg
= tok
- TOK_ASM_es
;
324 } else if (tok
== TOK_ASM_st
) {
330 if (tok
!= TOK_PPNUM
)
334 if ((unsigned)reg
>= 8 || p
[1] != '\0')
345 error("unknown register");
349 } else if (tok
== '$') {
357 if (op
->e
.v
== (uint8_t)op
->e
.v
)
359 if (op
->e
.v
== (int8_t)op
->e
.v
)
361 if (op
->e
.v
== (uint16_t)op
->e
.v
)
363 #ifdef TCC_TARGET_X86_64
364 if (op
->e
.v
== (uint32_t)op
->e
.v
)
369 /* address(reg,reg2,shift) with all variants */
385 op
->reg
= asm_parse_reg();
390 op
->reg2
= asm_parse_reg();
394 op
->shift
= get_reg_shift(s1
);
399 if (op
->reg
== -1 && op
->reg2
== -1)
405 /* XXX: unify with C code output ? */
406 ST_FUNC
void gen_expr32(ExprValue
*pe
)
408 gen_addr32(pe
->sym
? VT_SYM
: 0, pe
->sym
, pe
->v
);
411 #ifdef TCC_TARGET_X86_64
412 static void gen_expr64(ExprValue
*pe
)
414 gen_addr64(pe
->sym
? VT_SYM
: 0, pe
->sym
, pe
->v
);
418 /* XXX: unify with C code output ? */
419 static void gen_disp32(ExprValue
*pe
)
422 if (sym
&& sym
->r
== cur_text_section
->sh_num
) {
423 /* same section: we can output an absolute value. Note
424 that the TCC compiler behaves differently here because
425 it always outputs a relocation to ease (future) code
426 elimination in the linker */
427 gen_le32(pe
->v
+ sym
->jnext
- ind
- 4);
429 gen_addrpc32(VT_SYM
, sym
, pe
->v
);
434 static void gen_expr16(ExprValue
*pe
)
437 greloc(cur_text_section
, pe
->sym
, ind
, R_386_16
);
440 static void gen_disp16(ExprValue
*pe
)
445 if (sym
->r
== cur_text_section
->sh_num
) {
446 /* same section: we can output an absolute value. Note
447 that the TCC compiler behaves differently here because
448 it always outputs a relocation to ease (future) code
449 elimination in the linker */
450 gen_le16(pe
->v
+ sym
->jnext
- ind
- 2);
452 greloc(cur_text_section
, sym
, ind
, R_386_PC16
);
456 /* put an empty PC32 relocation */
457 put_elf_reloc(symtab_section
, cur_text_section
,
464 /* generate the modrm operand */
465 static inline void asm_modrm(int reg
, Operand
*op
)
467 int mod
, reg1
, reg2
, sib_reg1
;
469 if (op
->type
& (OP_REG
| OP_MMX
| OP_SSE
)) {
470 g(0xc0 + (reg
<< 3) + op
->reg
);
471 } else if (op
->reg
== -1 && op
->reg2
== -1) {
472 /* displacement only */
474 if (tcc_state
->seg_size
== 16) {
475 g(0x06 + (reg
<< 3));
477 } else if (tcc_state
->seg_size
== 32)
480 g(0x05 + (reg
<< 3));
485 /* fist compute displacement encoding */
486 if (sib_reg1
== -1) {
489 } else if (op
->e
.v
== 0 && !op
->e
.sym
&& op
->reg
!= 5) {
491 } else if (op
->e
.v
== (int8_t)op
->e
.v
&& !op
->e
.sym
) {
496 /* compute if sib byte needed */
501 if (tcc_state
->seg_size
== 32) {
503 g(mod
+ (reg
<< 3) + reg1
);
508 reg2
= 4; /* indicate no index */
509 g((op
->shift
<< 6) + (reg2
<< 3) + sib_reg1
);
512 } else if (tcc_state
->seg_size
== 16) {
513 /* edi = 7, esi = 6 --> di = 5, si = 4 */
514 if ((reg1
== 6) || (reg1
== 7)) {
516 /* ebx = 3 --> bx = 7 */
517 } else if (reg1
== 3) {
519 /* o32 = 5 --> o16 = 6 */
520 } else if (reg1
== 5) {
522 /* sib not valid in 16-bit mode */
523 } else if (reg1
== 4) {
525 /* bp + si + offset */
526 if ((sib_reg1
== 5) && (reg2
== 6)) {
528 /* bp + di + offset */
529 } else if ((sib_reg1
== 5) && (reg2
== 7)) {
531 /* bx + si + offset */
532 } else if ((sib_reg1
== 3) && (reg2
== 6)) {
534 /* bx + di + offset */
535 } else if ((sib_reg1
== 3) && (reg2
== 7)) {
538 error("invalid effective address");
543 error("invalid register");
545 g(mod
+ (reg
<< 3) + reg1
);
551 } else if (mod
== 0x80 || op
->reg
== -1) {
553 if (tcc_state
->seg_size
== 16)
555 else if (tcc_state
->seg_size
== 32)
562 ST_FUNC
void asm_opcode(TCCState
*s1
, int opcode
)
565 int i
, modrm_index
, reg
, v
, op1
, is_short_jmp
, seg_prefix
;
567 Operand ops
[MAX_OPERANDS
], *pop
;
568 int op_type
[3]; /* decoded op type */
570 static int a32
= 0, o32
= 0, addr32
= 0, data32
= 0;
578 if (tok
== ';' || tok
== TOK_LINEFEED
)
580 if (nb_ops
>= MAX_OPERANDS
) {
581 error("incorrect number of operands");
583 parse_operand(s1
, pop
);
585 if (pop
->type
!= OP_SEG
|| seg_prefix
)
586 error("incorrect prefix");
587 seg_prefix
= segment_prefixes
[pop
->reg
];
589 parse_operand(s1
, pop
);
591 if (!(pop
->type
& OP_EA
)) {
592 error("segment prefix must be followed by memory reference");
604 s
= 0; /* avoid warning */
606 /* optimize matching by using a lookup table (no hashing is needed
608 for(pa
= asm_instrs
; pa
->sym
!= 0; pa
++) {
610 if (pa
->instr_type
& OPC_FARITH
) {
611 v
= opcode
- pa
->sym
;
612 if (!((unsigned)v
< 8 * 6 && (v
% 6) == 0))
614 } else if (pa
->instr_type
& OPC_ARITH
) {
615 if (!(opcode
>= pa
->sym
&& opcode
< pa
->sym
+ 8*NBWLX
))
617 s
= (opcode
- pa
->sym
) % NBWLX
;
618 } else if (pa
->instr_type
& OPC_SHIFT
) {
619 if (!(opcode
>= pa
->sym
&& opcode
< pa
->sym
+ 7*NBWLX
))
621 s
= (opcode
- pa
->sym
) % NBWLX
;
622 } else if (pa
->instr_type
& OPC_TEST
) {
623 if (!(opcode
>= pa
->sym
&& opcode
< pa
->sym
+ NB_TEST_OPCODES
))
625 } else if (pa
->instr_type
& OPC_B
) {
626 if (!(opcode
>= pa
->sym
&& opcode
< pa
->sym
+ NBWLX
))
628 s
= opcode
- pa
->sym
;
629 } else if (pa
->instr_type
& OPC_WLX
) {
630 if (!(opcode
>= pa
->sym
&& opcode
< pa
->sym
+ NBWLX
-1))
632 s
= opcode
- pa
->sym
+ 1;
634 if (pa
->sym
!= opcode
)
637 if (pa
->nb_ops
!= nb_ops
)
639 /* now decode and check each operand */
640 for(i
= 0; i
< nb_ops
; i
++) {
642 op1
= pa
->op_type
[i
];
646 v
= OP_IM8
| OP_IM16
| OP_IM32
| OP_IM64
;
649 v
= OP_REG8
| OP_REG16
| OP_REG32
| OP_REG64
;
652 v
= OP_REG16
| OP_REG32
| OP_REG64
;
655 v
= OP_IM16
| OP_IM32
| OP_IM64
;
657 #ifdef TCC_TARGET_X86_64
659 v
= OP_IM16
| OP_IM32
;
669 if ((ops
[i
].type
& v
) == 0)
672 /* all is matching ! */
677 if (opcode
>= TOK_ASM_first
&& opcode
<= TOK_ASM_last
) {
679 b
= op0_codes
[opcode
- TOK_ASM_first
];
681 if (opcode
== TOK_ASM_o32
) {
682 if (s1
->seg_size
== 32)
683 error("incorrect prefix");
686 } else if (opcode
== TOK_ASM_a32
) {
687 if (s1
->seg_size
== 32)
688 error("incorrect prefix");
698 error("unknown opcode '%s'",
699 get_tok_str(opcode
, NULL
));
702 /* if the size is unknown, then evaluate it (OPC_B or OPC_WL case) */
704 for(i
= 0; s
== NBWLX
-1 && i
< nb_ops
; i
++) {
705 if ((ops
[i
].type
& OP_REG
) && !(op_type
[i
] & (OP_CL
| OP_DX
)))
706 s
= reg_to_size
[ops
[i
].type
& OP_REG
];
709 if ((opcode
== TOK_ASM_push
|| opcode
== TOK_ASM_pop
) &&
710 (ops
[0].type
& (OP_SEG
| OP_IM8S
| OP_IM32
| OP_IM64
)))
713 error("cannot infer opcode suffix");
718 for(i
= 0; i
< nb_ops
; i
++) {
719 if (ops
[i
].type
& OP_REG32
) {
720 if (s1
->seg_size
== 16)
722 } else if (!(ops
[i
].type
& OP_REG32
)) {
723 if (s1
->seg_size
== 32)
729 if (s
== 1 || (pa
->instr_type
& OPC_D16
)) {
730 if (s1
->seg_size
== 32)
733 if (s1
->seg_size
== 16) {
734 if (!(pa
->instr_type
& OPC_D16
))
739 /* generate a16/a32 prefix if needed */
740 if ((a32
== 1) && (addr32
== 0))
742 /* generate o16/o32 prefix if needed */
743 if ((o32
== 1) && (data32
== 0))
748 /* generate data16 prefix if needed */
749 if (s
== 1 || (pa
->instr_type
& OPC_D16
))
751 #ifdef TCC_TARGET_X86_64
753 /* generate REX prefix */
754 if ((opcode
!= TOK_ASM_push
&& opcode
!= TOK_ASM_pop
)
755 || !(ops
[0].type
& OP_REG64
))
761 /* now generates the operation */
762 if (pa
->instr_type
& OPC_FWAIT
)
768 if ((v
== 0x69 || v
== 0x6b) && nb_ops
== 2) {
769 /* kludge for imul $im, %reg */
772 op_type
[2] = op_type
[1];
773 } else if (v
== 0xcd && ops
[0].e
.v
== 3 && !ops
[0].e
.sym
) {
774 v
--; /* int $3 case */
776 } else if ((v
== 0x06 || v
== 0x07)) {
777 if (ops
[0].reg
>= 4) {
778 /* push/pop %fs or %gs */
779 v
= 0x0fa0 + (v
- 0x06) + ((ops
[0].reg
- 4) << 3);
781 v
+= ops
[0].reg
<< 3;
784 } else if (v
<= 0x05) {
786 v
+= ((opcode
- TOK_ASM_addb
) / NBWLX
) << 3;
787 } else if ((pa
->instr_type
& (OPC_FARITH
| OPC_MODRM
)) == OPC_FARITH
) {
789 v
+= ((opcode
- pa
->sym
) / 6) << 3;
791 if (pa
->instr_type
& OPC_REG
) {
792 for(i
= 0; i
< nb_ops
; i
++) {
793 if (op_type
[i
] & (OP_REG
| OP_ST
)) {
798 /* mov $im, %reg case */
799 if (pa
->opcode
== 0xb0 && s
>= 1)
802 if (pa
->instr_type
& OPC_B
)
804 if (pa
->instr_type
& OPC_TEST
)
805 v
+= test_bits
[opcode
- pa
->sym
];
806 if (pa
->instr_type
& OPC_SHORTJMP
) {
810 /* see if we can really generate the jump with a byte offset */
814 if (sym
->r
!= cur_text_section
->sh_num
)
816 jmp_disp
= ops
[0].e
.v
+ sym
->jnext
- ind
- 2;
817 if (jmp_disp
== (int8_t)jmp_disp
) {
818 /* OK to generate jump */
820 ops
[0].e
.v
= jmp_disp
;
823 if (pa
->instr_type
& OPC_JMP
) {
824 /* long jump will be allowed. need to modify the
831 error("invalid displacement");
840 /* search which operand will used for modrm */
842 if (pa
->instr_type
& OPC_SHIFT
) {
843 reg
= (opcode
- pa
->sym
) / NBWLX
;
846 } else if (pa
->instr_type
& OPC_ARITH
) {
847 reg
= (opcode
- pa
->sym
) / NBWLX
;
848 } else if (pa
->instr_type
& OPC_FARITH
) {
849 reg
= (opcode
- pa
->sym
) / 6;
851 reg
= (pa
->instr_type
>> OPC_GROUP_SHIFT
) & 7;
853 if (pa
->instr_type
& OPC_MODRM
) {
854 /* first look for an ea operand */
855 for(i
= 0;i
< nb_ops
; i
++) {
856 if (op_type
[i
] & OP_EA
)
859 /* then if not found, a register or indirection (shift instructions) */
860 for(i
= 0;i
< nb_ops
; i
++) {
861 if (op_type
[i
] & (OP_REG
| OP_MMX
| OP_SSE
| OP_INDIR
))
865 error("bad op table");
869 /* if a register is used in another operand then it is
870 used instead of group */
871 for(i
= 0;i
< nb_ops
; i
++) {
873 if (i
!= modrm_index
&&
874 (v
& (OP_REG
| OP_MMX
| OP_SSE
| OP_CR
| OP_TR
| OP_DB
| OP_SEG
))) {
880 asm_modrm(reg
, &ops
[modrm_index
]);
884 #ifndef TCC_TARGET_X86_64
885 if (pa
->opcode
== 0x9a || pa
->opcode
== 0xea) {
886 /* ljmp or lcall kludge */
888 if (s1
->seg_size
== 16 && o32
== 0)
889 gen_expr16(&ops
[1].e
);
892 gen_expr32(&ops
[1].e
);
894 error("cannot relocate");
895 gen_le16(ops
[0].e
.v
);
899 for(i
= 0;i
< nb_ops
; i
++) {
901 if (v
& (OP_IM8
| OP_IM16
| OP_IM32
| OP_IM64
| OP_IM8S
| OP_ADDR
)) {
902 /* if multiple sizes are given it means we must look
904 if ((v
| OP_IM8
| OP_IM64
) == (OP_IM8
| OP_IM16
| OP_IM32
| OP_IM64
)) {
909 else if (s
== 2 || (v
& OP_IM64
) == 0)
914 if (v
& (OP_IM8
| OP_IM8S
)) {
918 } else if (v
& OP_IM16
) {
920 if (s1
->seg_size
== 16)
921 gen_expr16(&ops
[i
].e
);
926 error("cannot relocate");
928 gen_le16(ops
[i
].e
.v
);
930 if (pa
->instr_type
& (OPC_JMP
| OPC_SHORTJMP
)) {
934 else if (s1
->seg_size
== 16)
935 gen_disp16(&ops
[i
].e
);
938 gen_disp32(&ops
[i
].e
);
941 if (s1
->seg_size
== 16 && !((o32
== 1) && (v
& OP_IM32
)))
942 gen_expr16(&ops
[i
].e
);
945 #ifdef TCC_TARGET_X86_64
947 gen_expr64(&ops
[i
].e
);
950 gen_expr32(&ops
[i
].e
);
954 } else if (v
& (OP_REG16
| OP_REG32
)) {
955 if (pa
->instr_type
& (OPC_JMP
| OPC_SHORTJMP
)) {
957 g(0xE0 + ops
[i
].reg
);
960 #ifdef TCC_TARGET_X86_64
961 } else if (v
& (OP_REG32
| OP_REG64
)) {
962 if (pa
->instr_type
& (OPC_JMP
| OPC_SHORTJMP
)) {
964 g(0xE0 + ops
[i
].reg
);
974 /* return the constraint priority (we allocate first the lowest
975 numbered constraints) */
976 static inline int constraint_priority(const char *str
)
980 /* we take the lowest priority */
1014 error("unknown constraint '%c'", c
);
1023 static const char *skip_constraint_modifiers(const char *p
)
1025 while (*p
== '=' || *p
== '&' || *p
== '+' || *p
== '%')
1030 #define REG_OUT_MASK 0x01
1031 #define REG_IN_MASK 0x02
1033 #define is_reg_allocated(reg) (regs_allocated[reg] & reg_mask)
1035 ST_FUNC
void asm_compute_constraints(ASMOperand
*operands
,
1036 int nb_operands
, int nb_outputs
,
1037 const uint8_t *clobber_regs
,
1041 int sorted_op
[MAX_ASM_OPERANDS
];
1042 int i
, j
, k
, p1
, p2
, tmp
, reg
, c
, reg_mask
;
1044 uint8_t regs_allocated
[NB_ASM_REGS
];
1047 for(i
=0;i
<nb_operands
;i
++) {
1049 op
->input_index
= -1;
1055 /* compute constraint priority and evaluate references to output
1056 constraints if input constraints */
1057 for(i
=0;i
<nb_operands
;i
++) {
1059 str
= op
->constraint
;
1060 str
= skip_constraint_modifiers(str
);
1061 if (isnum(*str
) || *str
== '[') {
1062 /* this is a reference to another constraint */
1063 k
= find_constraint(operands
, nb_operands
, str
, NULL
);
1064 if ((unsigned)k
>= i
|| i
< nb_outputs
)
1065 error("invalid reference in constraint %d ('%s')",
1068 if (operands
[k
].input_index
>= 0)
1069 error("cannot reference twice the same operand");
1070 operands
[k
].input_index
= i
;
1073 op
->priority
= constraint_priority(str
);
1077 /* sort operands according to their priority */
1078 for(i
=0;i
<nb_operands
;i
++)
1080 for(i
=0;i
<nb_operands
- 1;i
++) {
1081 for(j
=i
+1;j
<nb_operands
;j
++) {
1082 p1
= operands
[sorted_op
[i
]].priority
;
1083 p2
= operands
[sorted_op
[j
]].priority
;
1086 sorted_op
[i
] = sorted_op
[j
];
1092 for(i
= 0;i
< NB_ASM_REGS
; i
++) {
1093 if (clobber_regs
[i
])
1094 regs_allocated
[i
] = REG_IN_MASK
| REG_OUT_MASK
;
1096 regs_allocated
[i
] = 0;
1098 /* esp cannot be used */
1099 regs_allocated
[4] = REG_IN_MASK
| REG_OUT_MASK
;
1100 /* ebp cannot be used yet */
1101 regs_allocated
[5] = REG_IN_MASK
| REG_OUT_MASK
;
1103 /* allocate registers and generate corresponding asm moves */
1104 for(i
=0;i
<nb_operands
;i
++) {
1107 str
= op
->constraint
;
1108 /* no need to allocate references */
1109 if (op
->ref_index
>= 0)
1111 /* select if register is used for output, input or both */
1112 if (op
->input_index
>= 0) {
1113 reg_mask
= REG_IN_MASK
| REG_OUT_MASK
;
1114 } else if (j
< nb_outputs
) {
1115 reg_mask
= REG_OUT_MASK
;
1117 reg_mask
= REG_IN_MASK
;
1128 if (j
>= nb_outputs
)
1129 error("'%c' modifier can only be applied to outputs", c
);
1130 reg_mask
= REG_IN_MASK
| REG_OUT_MASK
;
1133 /* allocate both eax and edx */
1134 if (is_reg_allocated(TREG_XAX
) ||
1135 is_reg_allocated(TREG_XDX
))
1139 regs_allocated
[TREG_XAX
] |= reg_mask
;
1140 regs_allocated
[TREG_XDX
] |= reg_mask
;
1160 if (is_reg_allocated(reg
))
1164 /* eax, ebx, ecx or edx */
1165 for(reg
= 0; reg
< 4; reg
++) {
1166 if (!is_reg_allocated(reg
))
1171 /* any general register */
1172 for(reg
= 0; reg
< 8; reg
++) {
1173 if (!is_reg_allocated(reg
))
1178 /* now we can reload in the register */
1181 regs_allocated
[reg
] |= reg_mask
;
1184 if (!((op
->vt
->r
& (VT_VALMASK
| VT_LVAL
)) == VT_CONST
))
1190 if (!((op
->vt
->r
& (VT_VALMASK
| VT_LVAL
| VT_SYM
)) == VT_CONST
))
1195 /* nothing special to do because the operand is already in
1196 memory, except if the pointer itself is stored in a
1197 memory variable (VT_LLOCAL case) */
1198 /* XXX: fix constant case */
1199 /* if it is a reference to a memory zone, it must lie
1200 in a register, so we reserve the register in the
1201 input registers and a load will be generated
1203 if (j
< nb_outputs
|| c
== 'm') {
1204 if ((op
->vt
->r
& VT_VALMASK
) == VT_LLOCAL
) {
1205 /* any general register */
1206 for(reg
= 0; reg
< 8; reg
++) {
1207 if (!(regs_allocated
[reg
] & REG_IN_MASK
))
1212 /* now we can reload in the register */
1213 regs_allocated
[reg
] |= REG_IN_MASK
;
1220 error("asm constraint %d ('%s') could not be satisfied",
1224 /* if a reference is present for that operand, we assign it too */
1225 if (op
->input_index
>= 0) {
1226 operands
[op
->input_index
].reg
= op
->reg
;
1227 operands
[op
->input_index
].is_llong
= op
->is_llong
;
1231 /* compute out_reg. It is used to store outputs registers to memory
1232 locations references by pointers (VT_LLOCAL case) */
1234 for(i
=0;i
<nb_operands
;i
++) {
1237 (op
->vt
->r
& VT_VALMASK
) == VT_LLOCAL
&&
1239 for(reg
= 0; reg
< 8; reg
++) {
1240 if (!(regs_allocated
[reg
] & REG_OUT_MASK
))
1243 error("could not find free output register for reloading");
1250 /* print sorted constraints */
1252 for(i
=0;i
<nb_operands
;i
++) {
1255 printf("%%%d [%s]: \"%s\" r=0x%04x reg=%d\n",
1257 op
->id
? get_tok_str(op
->id
, NULL
) : "",
1263 printf("out_reg=%d\n", *pout_reg
);
1267 ST_FUNC
void subst_asm_operand(CString
*add_str
,
1268 SValue
*sv
, int modifier
)
1270 int r
, reg
, size
, val
;
1274 if ((r
& VT_VALMASK
) == VT_CONST
) {
1275 if (!(r
& VT_LVAL
) && modifier
!= 'c' && modifier
!= 'n')
1276 cstr_ccat(add_str
, '$');
1278 cstr_cat(add_str
, get_tok_str(sv
->sym
->v
, NULL
));
1280 cstr_ccat(add_str
, '+');
1286 if (modifier
== 'n')
1288 snprintf(buf
, sizeof(buf
), "%d", sv
->c
.i
);
1289 cstr_cat(add_str
, buf
);
1290 } else if ((r
& VT_VALMASK
) == VT_LOCAL
) {
1291 snprintf(buf
, sizeof(buf
), "%d(%%ebp)", sv
->c
.i
);
1292 cstr_cat(add_str
, buf
);
1293 } else if (r
& VT_LVAL
) {
1294 reg
= r
& VT_VALMASK
;
1295 if (reg
>= VT_CONST
)
1296 error("internal compiler error");
1297 snprintf(buf
, sizeof(buf
), "(%%%s)",
1298 get_tok_str(TOK_ASM_eax
+ reg
, NULL
));
1299 cstr_cat(add_str
, buf
);
1302 reg
= r
& VT_VALMASK
;
1303 if (reg
>= VT_CONST
)
1304 error("internal compiler error");
1306 /* choose register operand size */
1307 if ((sv
->type
.t
& VT_BTYPE
) == VT_BYTE
)
1309 else if ((sv
->type
.t
& VT_BTYPE
) == VT_SHORT
)
1311 #ifdef TCC_TARGET_X86_64
1312 else if ((sv
->type
.t
& VT_BTYPE
) == VT_LLONG
)
1317 if (size
== 1 && reg
>= 4)
1320 if (modifier
== 'b') {
1322 error("cannot use byte register");
1324 } else if (modifier
== 'h') {
1326 error("cannot use byte register");
1328 } else if (modifier
== 'w') {
1330 #ifdef TCC_TARGET_X86_64
1331 } else if (modifier
== 'q') {
1338 reg
= TOK_ASM_ah
+ reg
;
1341 reg
= TOK_ASM_al
+ reg
;
1344 reg
= TOK_ASM_ax
+ reg
;
1347 reg
= TOK_ASM_eax
+ reg
;
1349 #ifdef TCC_TARGET_X86_64
1351 reg
= TOK_ASM_rax
+ reg
;
1355 snprintf(buf
, sizeof(buf
), "%%%s", get_tok_str(reg
, NULL
));
1356 cstr_cat(add_str
, buf
);
1360 /* generate prolog and epilog code for asm statment */
1361 ST_FUNC
void asm_gen_code(ASMOperand
*operands
, int nb_operands
,
1362 int nb_outputs
, int is_output
,
1363 uint8_t *clobber_regs
,
1366 uint8_t regs_allocated
[NB_ASM_REGS
];
1369 static uint8_t reg_saved
[NB_SAVED_REGS
] = { 3, 6, 7 };
1371 /* mark all used registers */
1372 memcpy(regs_allocated
, clobber_regs
, sizeof(regs_allocated
));
1373 for(i
= 0; i
< nb_operands
;i
++) {
1376 regs_allocated
[op
->reg
] = 1;
1379 /* generate reg save code */
1380 for(i
= 0; i
< NB_SAVED_REGS
; i
++) {
1382 if (regs_allocated
[reg
]) {
1384 if (tcc_state
->seg_size
== 16)
1391 /* generate load code */
1392 for(i
= 0; i
< nb_operands
; i
++) {
1395 if ((op
->vt
->r
& VT_VALMASK
) == VT_LLOCAL
&&
1397 /* memory reference case (for both input and
1401 sv
.r
= (sv
.r
& ~VT_VALMASK
) | VT_LOCAL
;
1403 } else if (i
>= nb_outputs
|| op
->is_rw
) {
1404 /* load value in register */
1405 load(op
->reg
, op
->vt
);
1410 load(TREG_XDX
, &sv
);
1416 /* generate save code */
1417 for(i
= 0 ; i
< nb_outputs
; i
++) {
1420 if ((op
->vt
->r
& VT_VALMASK
) == VT_LLOCAL
) {
1421 if (!op
->is_memory
) {
1424 sv
.r
= (sv
.r
& ~VT_VALMASK
) | VT_LOCAL
;
1427 sv
.r
= (sv
.r
& ~VT_VALMASK
) | out_reg
;
1428 store(op
->reg
, &sv
);
1431 store(op
->reg
, op
->vt
);
1436 store(TREG_XDX
, &sv
);
1441 /* generate reg restore code */
1442 for(i
= NB_SAVED_REGS
- 1; i
>= 0; i
--) {
1444 if (regs_allocated
[reg
]) {
1446 if (tcc_state
->seg_size
== 16)
1455 ST_FUNC
void asm_clobber(uint8_t *clobber_regs
, const char *str
)
1460 if (!strcmp(str
, "memory") ||
1463 ts
= tok_alloc(str
, strlen(str
));
1465 if (reg
>= TOK_ASM_eax
&& reg
<= TOK_ASM_edi
) {
1467 } else if (reg
>= TOK_ASM_ax
&& reg
<= TOK_ASM_di
) {
1469 #ifdef TCC_TARGET_X86_64
1470 } else if (reg
>= TOK_ASM_rax
&& reg
<= TOK_ASM_rdi
) {
1474 error("invalid clobber register '%s'", str
);
1476 clobber_regs
[reg
] = 1;