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tccasm: allow one-line prefix+op things like "rep stosb"
[tinycc.git] / i386-asm.c
blob2623ef64ff7a13ba73ed9eaaf2e5d65df4bc81d6
1 /*
2 * i386 specific functions for TCC assembler
3 *
4 * Copyright (c) 2001, 2002 Fabrice Bellard
5 * Copyright (c) 2009 Frédéric Feret (x86_64 support)
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22 #include "tcc.h"
23
24 // #define NB_ASM_REGS 8
25 #define MAX_OPERANDS 3
26 #define NB_SAVED_REGS 3
27
28 #define TOK_ASM_first TOK_ASM_clc
29 #define TOK_ASM_last TOK_ASM_emms
30
31 #define OPC_JMP 0x01 /* jmp operand */
32 #define OPC_B 0x02 /* only used with OPC_WL */
33 #define OPC_WL 0x04 /* accepts w, l or no suffix */
34 #define OPC_BWL (OPC_B | OPC_WL) /* accepts b, w, l or no suffix */
35 #define OPC_REG 0x08 /* register is added to opcode */
36 #define OPC_MODRM 0x10 /* modrm encoding */
37 #define OPC_FWAIT 0x20 /* add fwait opcode */
38 #define OPC_TEST 0x40 /* test opcodes */
39 #define OPC_SHIFT 0x80 /* shift opcodes */
40 #define OPC_D16 0x0100 /* generate data16 prefix */
41 #define OPC_ARITH 0x0200 /* arithmetic opcodes */
42 #define OPC_SHORTJMP 0x0400 /* short jmp operand */
43 #define OPC_FARITH 0x0800 /* FPU arithmetic opcodes */
44 #ifdef TCC_TARGET_X86_64
45 # define OPC_WLQ 0x1000 /* accepts w, l, q or no suffix */
46 # define OPC_BWLQ (OPC_B | OPC_WLQ) /* accepts b, w, l, q or no suffix */
47 # define OPC_WLX OPC_WLQ
48 #else
49 # define OPC_WLX OPC_WL
50 #endif
51
52 #define OPC_GROUP_SHIFT 13
53
54 /* in order to compress the operand type, we use specific operands and
55 we or only with EA */
56 enum {
57 OPT_REG8=0, /* warning: value is hardcoded from TOK_ASM_xxx */
58 OPT_REG16, /* warning: value is hardcoded from TOK_ASM_xxx */
59 OPT_REG32, /* warning: value is hardcoded from TOK_ASM_xxx */
60 #ifdef TCC_TARGET_X86_64
61 OPT_REG64, /* warning: value is hardcoded from TOK_ASM_xxx */
62 #endif
63 OPT_MMX, /* warning: value is hardcoded from TOK_ASM_xxx */
64 OPT_SSE, /* warning: value is hardcoded from TOK_ASM_xxx */
65 OPT_CR, /* warning: value is hardcoded from TOK_ASM_xxx */
66 OPT_TR, /* warning: value is hardcoded from TOK_ASM_xxx */
67 OPT_DB, /* warning: value is hardcoded from TOK_ASM_xxx */
68 OPT_SEG,
69 OPT_ST,
70 OPT_IM8,
71 OPT_IM8S,
72 OPT_IM16,
73 OPT_IM32,
74 #ifdef TCC_TARGET_X86_64
75 OPT_IM64,
76 #endif
77 OPT_EAX, /* %al, %ax, %eax or %rax register */
78 OPT_ST0, /* %st(0) register */
79 OPT_CL, /* %cl register */
80 OPT_DX, /* %dx register */
81 OPT_ADDR, /* OP_EA with only offset */
82 OPT_INDIR, /* *(expr) */
83 /* composite types */
84 OPT_COMPOSITE_FIRST,
85 OPT_IM, /* IM8 | IM16 | IM32 | IM64 */
86 OPT_REG, /* REG8 | REG16 | REG32 | REG64 */
87 OPT_REGW, /* REG16 | REG32 | REG64 */
88 OPT_IMW, /* IM16 | IM32 | IM64 */
89 #ifdef TCC_TARGET_X86_64
90 OPT_IMNO64, /* IM16 | IM32 */
91 #endif
92 /* can be ored with any OPT_xxx */
93 OPT_EA = 0x80
94 };
95
96 #define OP_REG8 (1 << OPT_REG8)
97 #define OP_REG16 (1 << OPT_REG16)
98 #define OP_REG32 (1 << OPT_REG32)
99 #define OP_MMX (1 << OPT_MMX)
100 #define OP_SSE (1 << OPT_SSE)
101 #define OP_CR (1 << OPT_CR)
102 #define OP_TR (1 << OPT_TR)
103 #define OP_DB (1 << OPT_DB)
104 #define OP_SEG (1 << OPT_SEG)
105 #define OP_ST (1 << OPT_ST)
106 #define OP_IM8 (1 << OPT_IM8)
107 #define OP_IM8S (1 << OPT_IM8S)
108 #define OP_IM16 (1 << OPT_IM16)
109 #define OP_IM32 (1 << OPT_IM32)
110 #define OP_EAX (1 << OPT_EAX)
111 #define OP_ST0 (1 << OPT_ST0)
112 #define OP_CL (1 << OPT_CL)
113 #define OP_DX (1 << OPT_DX)
114 #define OP_ADDR (1 << OPT_ADDR)
115 #define OP_INDIR (1 << OPT_INDIR)
116 #ifdef TCC_TARGET_X86_64
117 # define OP_REG64 (1 << OPT_REG64)
118 # define OP_IM64 (1 << OPT_IM64)
119 #else
120 # define OP_REG64 0
121 # define OP_IM64 0
122 #endif
123
124 #define OP_EA 0x40000000
125 #define OP_REG (OP_REG8 | OP_REG16 | OP_REG32 | OP_REG64)
126
127 #ifdef TCC_TARGET_X86_64
128 # define OP_IM OP_IM64
129 # define TREG_XAX TREG_RAX
130 # define TREG_XCX TREG_RCX
131 # define TREG_XDX TREG_RDX
132 #else
133 # define OP_IM OP_IM32
134 # define TREG_XAX TREG_EAX
135 # define TREG_XCX TREG_ECX
136 # define TREG_XDX TREG_EDX
137 #endif
138
139 typedef struct ASMInstr {
140 uint16_t sym;
141 uint16_t opcode;
142 uint16_t instr_type;
143 uint8_t nb_ops;
144 uint8_t op_type[MAX_OPERANDS]; /* see OP_xxx */
145 } ASMInstr;
146
147 typedef struct Operand {
148 uint32_t type;
149 int8_t reg; /* register, -1 if none */
150 int8_t reg2; /* second register, -1 if none */
151 uint8_t shift;
152 ExprValue e;
153 } Operand;
154
155 static const uint8_t reg_to_size[9] = {
156 /*
157 [OP_REG8] = 0,
158 [OP_REG16] = 1,
159 [OP_REG32] = 2,
160 #ifdef TCC_TARGET_X86_64
161 [OP_REG64] = 3,
162 #endif
163 */
164 0, 0, 1, 0, 2, 0, 0, 0, 3
165 };
166
167 #define NB_TEST_OPCODES 30
168
169 static const uint8_t test_bits[NB_TEST_OPCODES] = {
170 0x00, /* o */
171 0x01, /* no */
172 0x02, /* b */
173 0x02, /* c */
174 0x02, /* nae */
175 0x03, /* nb */
176 0x03, /* nc */
177 0x03, /* ae */
178 0x04, /* e */
179 0x04, /* z */
180 0x05, /* ne */
181 0x05, /* nz */
182 0x06, /* be */
183 0x06, /* na */
184 0x07, /* nbe */
185 0x07, /* a */
186 0x08, /* s */
187 0x09, /* ns */
188 0x0a, /* p */
189 0x0a, /* pe */
190 0x0b, /* np */
191 0x0b, /* po */
192 0x0c, /* l */
193 0x0c, /* nge */
194 0x0d, /* nl */
195 0x0d, /* ge */
196 0x0e, /* le */
197 0x0e, /* ng */
198 0x0f, /* nle */
199 0x0f, /* g */
200 };
201
202 static const uint8_t segment_prefixes[] = {
203 0x26, /* es */
204 0x2e, /* cs */
205 0x36, /* ss */
206 0x3e, /* ds */
207 0x64, /* fs */
208 0x65 /* gs */
209 };
210
211 static const ASMInstr asm_instrs[] = {
212 #define ALT(x) x
213 #define DEF_ASM_OP0(name, opcode)
214 #define DEF_ASM_OP0L(name, opcode, group, instr_type) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 0 },
215 #define DEF_ASM_OP1(name, opcode, group, instr_type, op0) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 1, { op0 }},
216 #define DEF_ASM_OP2(name, opcode, group, instr_type, op0, op1) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 2, { op0, op1 }},
217 #define DEF_ASM_OP3(name, opcode, group, instr_type, op0, op1, op2) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 3, { op0, op1, op2 }},
218 #ifdef TCC_TARGET_X86_64
219 # include "x86_64-asm.h"
220 #else
221 # include "i386-asm.h"
222 #endif
223 /* last operation */
224 { 0, },
225 };
226
227 static const uint16_t op0_codes[] = {
228 #define ALT(x)
229 #define DEF_ASM_OP0(x, opcode) opcode,
230 #define DEF_ASM_OP0L(name, opcode, group, instr_type)
231 #define DEF_ASM_OP1(name, opcode, group, instr_type, op0)
232 #define DEF_ASM_OP2(name, opcode, group, instr_type, op0, op1)
233 #define DEF_ASM_OP3(name, opcode, group, instr_type, op0, op1, op2)
234 #ifdef TCC_TARGET_X86_64
235 # include "x86_64-asm.h"
236 #else
237 # include "i386-asm.h"
238 #endif
239 };
240
241 static inline int get_reg_shift(TCCState *s1)
242 {
243 int shift, v;
244 #ifdef I386_ASM_16
245 if (s1->seg_size == 16)
246 error("invalid effective address");
247 #endif
248 v = asm_int_expr(s1);
249 switch(v) {
250 case 1:
251 shift = 0;
252 break;
253 case 2:
254 shift = 1;
255 break;
256 case 4:
257 shift = 2;
258 break;
259 case 8:
260 shift = 3;
261 break;
262 default:
263 expect("1, 2, 4 or 8 constant");
264 shift = 0;
265 break;
266 }
267 return shift;
268 }
269
270 static int asm_parse_reg(void)
271 {
272 int reg = 0;
273 if (tok != '%')
274 goto error_32;
275 next();
276 if (tok >= TOK_ASM_eax && tok <= TOK_ASM_edi) {
277 reg = tok - TOK_ASM_eax;
278 #ifdef TCC_TARGET_X86_64
279 } else if (tok >= TOK_ASM_rax && tok <= TOK_ASM_rdi) {
280 reg = tok - TOK_ASM_rax;
281 #endif
282 #ifdef I386_ASM_16
283 } else if (tok >= TOK_ASM_ax && tok <= TOK_ASM_di) {
284 reg = tok - TOK_ASM_ax;
285 #endif
286 } else {
287 error_32:
288 expect("register");
289 }
290 next();
291 return reg;
292 }
293
294 static void parse_operand(TCCState *s1, Operand *op)
295 {
296 ExprValue e;
297 int reg, indir;
298 const char *p;
299
300 indir = 0;
301 if (tok == '*') {
302 next();
303 indir = OP_INDIR;
304 }
305
306 if (tok == '%') {
307 next();
308 if (tok >= TOK_ASM_al && tok <= TOK_ASM_db7) {
309 reg = tok - TOK_ASM_al;
310 op->type = 1 << (reg >> 3); /* WARNING: do not change constant order */
311 op->reg = reg & 7;
312 if ((op->type & OP_REG) && op->reg == TREG_XAX)
313 op->type |= OP_EAX;
314 else if (op->type == OP_REG8 && op->reg == TREG_XCX)
315 op->type |= OP_CL;
316 else if (op->type == OP_REG16 && op->reg == TREG_XDX)
317 op->type |= OP_DX;
318 } else if (tok >= TOK_ASM_dr0 && tok <= TOK_ASM_dr7) {
319 op->type = OP_DB;
320 op->reg = tok - TOK_ASM_dr0;
321 } else if (tok >= TOK_ASM_es && tok <= TOK_ASM_gs) {
322 op->type = OP_SEG;
323 op->reg = tok - TOK_ASM_es;
324 } else if (tok == TOK_ASM_st) {
325 op->type = OP_ST;
326 op->reg = 0;
327 next();
328 if (tok == '(') {
329 next();
330 if (tok != TOK_PPNUM)
331 goto reg_error;
332 p = tokc.cstr->data;
333 reg = p[0] - '0';
334 if ((unsigned)reg >= 8 || p[1] != '\0')
335 goto reg_error;
336 op->reg = reg;
337 next();
338 skip(')');
339 }
340 if (op->reg == 0)
341 op->type |= OP_ST0;
342 goto no_skip;
343 } else {
344 reg_error:
345 error("unknown register");
346 }
347 next();
348 no_skip: ;
349 } else if (tok == '$') {
350 /* constant value */
351 next();
352 asm_expr(s1, &e);
353 op->type = OP_IM;
354 op->e.v = e.v;
355 op->e.sym = e.sym;
356 if (!op->e.sym) {
357 if (op->e.v == (uint8_t)op->e.v)
358 op->type |= OP_IM8;
359 if (op->e.v == (int8_t)op->e.v)
360 op->type |= OP_IM8S;
361 if (op->e.v == (uint16_t)op->e.v)
362 op->type |= OP_IM16;
363 #ifdef TCC_TARGET_X86_64
364 if (op->e.v == (uint32_t)op->e.v)
365 op->type |= OP_IM32;
366 #endif
367 }
368 } else {
369 /* address(reg,reg2,shift) with all variants */
370 op->type = OP_EA;
371 op->reg = -1;
372 op->reg2 = -1;
373 op->shift = 0;
374 if (tok != '(') {
375 asm_expr(s1, &e);
376 op->e.v = e.v;
377 op->e.sym = e.sym;
378 } else {
379 op->e.v = 0;
380 op->e.sym = NULL;
381 }
382 if (tok == '(') {
383 next();
384 if (tok != ',') {
385 op->reg = asm_parse_reg();
386 }
387 if (tok == ',') {
388 next();
389 if (tok != ',') {
390 op->reg2 = asm_parse_reg();
391 }
392 if (tok == ',') {
393 next();
394 op->shift = get_reg_shift(s1);
395 }
396 }
397 skip(')');
398 }
399 if (op->reg == -1 && op->reg2 == -1)
400 op->type |= OP_ADDR;
401 }
402 op->type |= indir;
403 }
404
405 /* XXX: unify with C code output ? */
406 ST_FUNC void gen_expr32(ExprValue *pe)
407 {
408 gen_addr32(pe->sym ? VT_SYM : 0, pe->sym, pe->v);
409 }
410
411 #ifdef TCC_TARGET_X86_64
412 static void gen_expr64(ExprValue *pe)
413 {
414 gen_addr64(pe->sym ? VT_SYM : 0, pe->sym, pe->v);
415 }
416 #endif
417
418 /* XXX: unify with C code output ? */
419 static void gen_disp32(ExprValue *pe)
420 {
421 Sym *sym = pe->sym;
422 if (sym && sym->r == cur_text_section->sh_num) {
423 /* same section: we can output an absolute value. Note
424 that the TCC compiler behaves differently here because
425 it always outputs a relocation to ease (future) code
426 elimination in the linker */
427 gen_le32(pe->v + sym->jnext - ind - 4);
428 } else {
429 if (sym && sym->type.t == VT_VOID) {
430 sym->type.t = VT_FUNC;
431 sym->type.ref = NULL;
432 }
433 gen_addrpc32(VT_SYM, sym, pe->v);
434 }
435 }
436
437 #ifdef I386_ASM_16
438 static void gen_expr16(ExprValue *pe)
439 {
440 if (pe->sym)
441 greloc(cur_text_section, pe->sym, ind, R_386_16);
442 gen_le16(pe->v);
443 }
444 static void gen_disp16(ExprValue *pe)
445 {
446 Sym *sym;
447 sym = pe->sym;
448 if (sym) {
449 if (sym->r == cur_text_section->sh_num) {
450 /* same section: we can output an absolute value. Note
451 that the TCC compiler behaves differently here because
452 it always outputs a relocation to ease (future) code
453 elimination in the linker */
454 gen_le16(pe->v + sym->jnext - ind - 2);
455 } else {
456 greloc(cur_text_section, sym, ind, R_386_PC16);
457 gen_le16(pe->v - 2);
458 }
459 } else {
460 /* put an empty PC32 relocation */
461 put_elf_reloc(symtab_section, cur_text_section,
462 ind, R_386_PC16, 0);
463 gen_le16(pe->v - 2);
464 }
465 }
466 #endif
467
468 /* generate the modrm operand */
469 static inline void asm_modrm(int reg, Operand *op)
470 {
471 int mod, reg1, reg2, sib_reg1;
472
473 if (op->type & (OP_REG | OP_MMX | OP_SSE)) {
474 g(0xc0 + (reg << 3) + op->reg);
475 } else if (op->reg == -1 && op->reg2 == -1) {
476 /* displacement only */
477 #ifdef I386_ASM_16
478 if (tcc_state->seg_size == 16) {
479 g(0x06 + (reg << 3));
480 gen_expr16(&op->e);
481 } else if (tcc_state->seg_size == 32)
482 #endif
483 {
484 g(0x05 + (reg << 3));
485 gen_expr32(&op->e);
486 }
487 } else {
488 sib_reg1 = op->reg;
489 /* fist compute displacement encoding */
490 if (sib_reg1 == -1) {
491 sib_reg1 = 5;
492 mod = 0x00;
493 } else if (op->e.v == 0 && !op->e.sym && op->reg != 5) {
494 mod = 0x00;
495 } else if (op->e.v == (int8_t)op->e.v && !op->e.sym) {
496 mod = 0x40;
497 } else {
498 mod = 0x80;
499 }
500 /* compute if sib byte needed */
501 reg1 = op->reg;
502 if (op->reg2 != -1)
503 reg1 = 4;
504 #ifdef I386_ASM_16
505 if (tcc_state->seg_size == 32) {
506 #endif
507 g(mod + (reg << 3) + reg1);
508 if (reg1 == 4) {
509 /* add sib byte */
510 reg2 = op->reg2;
511 if (reg2 == -1)
512 reg2 = 4; /* indicate no index */
513 g((op->shift << 6) + (reg2 << 3) + sib_reg1);
514 }
515 #ifdef I386_ASM_16
516 } else if (tcc_state->seg_size == 16) {
517 /* edi = 7, esi = 6 --> di = 5, si = 4 */
518 if ((reg1 == 6) || (reg1 == 7)) {
519 reg1 -= 2;
520 /* ebx = 3 --> bx = 7 */
521 } else if (reg1 == 3) {
522 reg1 = 7;
523 /* o32 = 5 --> o16 = 6 */
524 } else if (reg1 == 5) {
525 reg1 = 6;
526 /* sib not valid in 16-bit mode */
527 } else if (reg1 == 4) {
528 reg2 = op->reg2;
529 /* bp + si + offset */
530 if ((sib_reg1 == 5) && (reg2 == 6)) {
531 reg1 = 2;
532 /* bp + di + offset */
533 } else if ((sib_reg1 == 5) && (reg2 == 7)) {
534 reg1 = 3;
535 /* bx + si + offset */
536 } else if ((sib_reg1 == 3) && (reg2 == 6)) {
537 reg1 = 0;
538 /* bx + di + offset */
539 } else if ((sib_reg1 == 3) && (reg2 == 7)) {
540 reg1 = 1;
541 } else {
542 error("invalid effective address");
543 }
544 if (op->e.v == 0)
545 mod = 0;
546 } else {
547 error("invalid register");
548 }
549 g(mod + (reg << 3) + reg1);
550 }
551 #endif
552 /* add offset */
553 if (mod == 0x40) {
554 g(op->e.v);
555 } else if (mod == 0x80 || op->reg == -1) {
556 #ifdef I386_ASM_16
557 if (tcc_state->seg_size == 16)
558 gen_expr16(&op->e);
559 else if (tcc_state->seg_size == 32)
560 #endif
561 gen_expr32(&op->e);
562 }
563 }
564 }
565
566 ST_FUNC void asm_opcode(TCCState *s1, int opcode)
567 {
568 const ASMInstr *pa;
569 int i, modrm_index, reg, v, op1, is_short_jmp, seg_prefix;
570 int nb_ops, s;
571 Operand ops[MAX_OPERANDS], *pop;
572 int op_type[3]; /* decoded op type */
573 #ifdef I386_ASM_16
574 static int a32 = 0, o32 = 0, addr32 = 0, data32 = 0;
575 #endif
576
577 /* force synthetic ';' after prefix instruction, so we can handle */
578 /* one-line things like "rep stosb" instead of only "rep\nstosb" */
579 if (opcode >= TOK_ASM_wait && opcode <= TOK_ASM_repnz)
580 unget_tok(';');
581
582 /* get operands */
583 pop = ops;
584 nb_ops = 0;
585 seg_prefix = 0;
586 for(;;) {
587 if (tok == ';' || tok == TOK_LINEFEED)
588 break;
589 if (nb_ops >= MAX_OPERANDS) {
590 error("incorrect number of operands");
591 }
592 parse_operand(s1, pop);
593 if (tok == ':') {
594 if (pop->type != OP_SEG || seg_prefix)
595 error("incorrect prefix");
596 seg_prefix = segment_prefixes[pop->reg];
597 next();
598 parse_operand(s1, pop);
599 #ifndef I386_ASM_16
600 if (!(pop->type & OP_EA)) {
601 error("segment prefix must be followed by memory reference");
602 }
603 #endif
604 }
605 pop++;
606 nb_ops++;
607 if (tok != ',')
608 break;
609 next();
610 }
611
612 is_short_jmp = 0;
613 s = 0; /* avoid warning */
614
615 /* optimize matching by using a lookup table (no hashing is needed
616 !) */
617 for(pa = asm_instrs; pa->sym != 0; pa++) {
618 s = 0;
619 if (pa->instr_type & OPC_FARITH) {
620 v = opcode - pa->sym;
621 if (!((unsigned)v < 8 * 6 && (v % 6) == 0))
622 continue;
623 } else if (pa->instr_type & OPC_ARITH) {
624 if (!(opcode >= pa->sym && opcode < pa->sym + 8*NBWLX))
625 continue;
626 s = (opcode - pa->sym) % NBWLX;
627 } else if (pa->instr_type & OPC_SHIFT) {
628 if (!(opcode >= pa->sym && opcode < pa->sym + 7*NBWLX))
629 continue;
630 s = (opcode - pa->sym) % NBWLX;
631 } else if (pa->instr_type & OPC_TEST) {
632 if (!(opcode >= pa->sym && opcode < pa->sym + NB_TEST_OPCODES))
633 continue;
634 } else if (pa->instr_type & OPC_B) {
635 if (!(opcode >= pa->sym && opcode < pa->sym + NBWLX))
636 continue;
637 s = opcode - pa->sym;
638 } else if (pa->instr_type & OPC_WLX) {
639 if (!(opcode >= pa->sym && opcode < pa->sym + NBWLX-1))
640 continue;
641 s = opcode - pa->sym + 1;
642 } else {
643 if (pa->sym != opcode)
644 continue;
645 }
646 if (pa->nb_ops != nb_ops)
647 continue;
648 /* now decode and check each operand */
649 for(i = 0; i < nb_ops; i++) {
650 int op1, op2;
651 op1 = pa->op_type[i];
652 op2 = op1 & 0x1f;
653 switch(op2) {
654 case OPT_IM:
655 v = OP_IM8 | OP_IM16 | OP_IM32 | OP_IM64;
656 break;
657 case OPT_REG:
658 v = OP_REG8 | OP_REG16 | OP_REG32 | OP_REG64;
659 break;
660 case OPT_REGW:
661 v = OP_REG16 | OP_REG32 | OP_REG64;
662 break;
663 case OPT_IMW:
664 v = OP_IM16 | OP_IM32 | OP_IM64;
665 break;
666 #ifdef TCC_TARGET_X86_64
667 case OPT_IMNO64:
668 v = OP_IM16 | OP_IM32;
669 break;
670 #endif
671 default:
672 v = 1 << op2;
673 break;
674 }
675 if (op1 & OPT_EA)
676 v |= OP_EA;
677 op_type[i] = v;
678 if ((ops[i].type & v) == 0)
679 goto next;
680 }
681 /* all is matching ! */
682 break;
683 next: ;
684 }
685 if (pa->sym == 0) {
686 if (opcode >= TOK_ASM_first && opcode <= TOK_ASM_last) {
687 int b;
688 b = op0_codes[opcode - TOK_ASM_first];
689 #ifdef I386_ASM_16
690 if (opcode == TOK_ASM_o32) {
691 if (s1->seg_size == 32)
692 error("incorrect prefix");
693 else
694 o32 = data32 = 1;
695 } else if (opcode == TOK_ASM_a32) {
696 if (s1->seg_size == 32)
697 error("incorrect prefix");
698 else
699 a32 = addr32 = 1;
700 }
701 #endif
702 if (b & 0xff00)
703 g(b >> 8);
704 g(b);
705 return;
706 } else {
707 error("unknown opcode '%s'",
708 get_tok_str(opcode, NULL));
709 }
710 }
711 /* if the size is unknown, then evaluate it (OPC_B or OPC_WL case) */
712 if (s == NBWLX-1) {
713 for(i = 0; s == NBWLX-1 && i < nb_ops; i++) {
714 if ((ops[i].type & OP_REG) && !(op_type[i] & (OP_CL | OP_DX)))
715 s = reg_to_size[ops[i].type & OP_REG];
716 }
717 if (s == NBWLX-1) {
718 if ((opcode == TOK_ASM_push || opcode == TOK_ASM_pop) &&
719 (ops[0].type & (OP_SEG | OP_IM8S | OP_IM32 | OP_IM64)))
720 s = 2;
721 else
722 error("cannot infer opcode suffix");
723 }
724 }
725
726 #ifdef I386_ASM_16
727 for(i = 0; i < nb_ops; i++) {
728 if (ops[i].type & OP_REG32) {
729 if (s1->seg_size == 16)
730 o32 = 1;
731 } else if (!(ops[i].type & OP_REG32)) {
732 if (s1->seg_size == 32)
733 o32 = 1;
734 }
735 }
736
737
738 if (s == 1 || (pa->instr_type & OPC_D16)) {
739 if (s1->seg_size == 32)
740 o32 = 1;
741 } else if (s == 2) {
742 if (s1->seg_size == 16) {
743 if (!(pa->instr_type & OPC_D16))
744 o32 = 1;
745 }
746 }
747
748 /* generate a16/a32 prefix if needed */
749 if ((a32 == 1) && (addr32 == 0))
750 g(0x67);
751 /* generate o16/o32 prefix if needed */
752 if ((o32 == 1) && (data32 == 0))
753 g(0x66);
754
755 addr32 = data32 = 0;
756 #else
757 /* generate data16 prefix if needed */
758 if (s == 1 || (pa->instr_type & OPC_D16))
759 g(0x66);
760 #ifdef TCC_TARGET_X86_64
761 else if (s == 3) {
762 /* generate REX prefix */
763 if ((opcode != TOK_ASM_push && opcode != TOK_ASM_pop)
764 || !(ops[0].type & OP_REG64))
765 g(0x48);
766 }
767 #endif
768 #endif
769
770 /* now generates the operation */
771 if (pa->instr_type & OPC_FWAIT)
772 g(0x9b);
773 if (seg_prefix)
774 g(seg_prefix);
775
776 v = pa->opcode;
777 if ((v == 0x69 || v == 0x6b) && nb_ops == 2) {
778 /* kludge for imul $im, %reg */
779 nb_ops = 3;
780 ops[2] = ops[1];
781 op_type[2] = op_type[1];
782 } else if (v == 0xcd && ops[0].e.v == 3 && !ops[0].e.sym) {
783 v--; /* int $3 case */
784 nb_ops = 0;
785 } else if ((v == 0x06 || v == 0x07)) {
786 if (ops[0].reg >= 4) {
787 /* push/pop %fs or %gs */
788 v = 0x0fa0 + (v - 0x06) + ((ops[0].reg - 4) << 3);
789 } else {
790 v += ops[0].reg << 3;
791 }
792 nb_ops = 0;
793 } else if (v <= 0x05) {
794 /* arith case */
795 v += ((opcode - TOK_ASM_addb) / NBWLX) << 3;
796 } else if ((pa->instr_type & (OPC_FARITH | OPC_MODRM)) == OPC_FARITH) {
797 /* fpu arith case */
798 v += ((opcode - pa->sym) / 6) << 3;
799 }
800 if (pa->instr_type & OPC_REG) {
801 for(i = 0; i < nb_ops; i++) {
802 if (op_type[i] & (OP_REG | OP_ST)) {
803 v += ops[i].reg;
804 break;
805 }
806 }
807 /* mov $im, %reg case */
808 if (pa->opcode == 0xb0 && s >= 1)
809 v += 7;
810 }
811 if (pa->instr_type & OPC_B)
812 v += s >= 1;
813 if (pa->instr_type & OPC_TEST)
814 v += test_bits[opcode - pa->sym];
815 if (pa->instr_type & OPC_SHORTJMP) {
816 Sym *sym;
817 int jmp_disp;
818
819 /* see if we can really generate the jump with a byte offset */
820 sym = ops[0].e.sym;
821 if (!sym)
822 goto no_short_jump;
823 if (sym->r != cur_text_section->sh_num)
824 goto no_short_jump;
825 jmp_disp = ops[0].e.v + sym->jnext - ind - 2;
826 if (jmp_disp == (int8_t)jmp_disp) {
827 /* OK to generate jump */
828 is_short_jmp = 1;
829 ops[0].e.v = jmp_disp;
830 } else {
831 no_short_jump:
832 if (pa->instr_type & OPC_JMP) {
833 /* long jump will be allowed. need to modify the
834 opcode slightly */
835 if (v == 0xeb)
836 v = 0xe9;
837 else
838 v += 0x0f10;
839 } else {
840 error("invalid displacement");
841 }
842 }
843 }
844 op1 = v >> 8;
845 if (op1)
846 g(op1);
847 g(v);
848
849 /* search which operand will used for modrm */
850 modrm_index = 0;
851 if (pa->instr_type & OPC_SHIFT) {
852 reg = (opcode - pa->sym) / NBWLX;
853 if (reg == 6)
854 reg = 7;
855 } else if (pa->instr_type & OPC_ARITH) {
856 reg = (opcode - pa->sym) / NBWLX;
857 } else if (pa->instr_type & OPC_FARITH) {
858 reg = (opcode - pa->sym) / 6;
859 } else {
860 reg = (pa->instr_type >> OPC_GROUP_SHIFT) & 7;
861 }
862 if (pa->instr_type & OPC_MODRM) {
863 /* first look for an ea operand */
864 for(i = 0;i < nb_ops; i++) {
865 if (op_type[i] & OP_EA)
866 goto modrm_found;
867 }
868 /* then if not found, a register or indirection (shift instructions) */
869 for(i = 0;i < nb_ops; i++) {
870 if (op_type[i] & (OP_REG | OP_MMX | OP_SSE | OP_INDIR))
871 goto modrm_found;
872 }
873 #ifdef ASM_DEBUG
874 error("bad op table");
875 #endif
876 modrm_found:
877 modrm_index = i;
878 /* if a register is used in another operand then it is
879 used instead of group */
880 for(i = 0;i < nb_ops; i++) {
881 v = op_type[i];
882 if (i != modrm_index &&
883 (v & (OP_REG | OP_MMX | OP_SSE | OP_CR | OP_TR | OP_DB | OP_SEG))) {
884 reg = ops[i].reg;
885 break;
886 }
887 }
888
889 asm_modrm(reg, &ops[modrm_index]);
890 }
891
892 /* emit constants */
893 #ifndef TCC_TARGET_X86_64
894 if (pa->opcode == 0x9a || pa->opcode == 0xea) {
895 /* ljmp or lcall kludge */
896 #ifdef I386_ASM_16
897 if (s1->seg_size == 16 && o32 == 0)
898 gen_expr16(&ops[1].e);
899 else
900 #endif
901 gen_expr32(&ops[1].e);
902 if (ops[0].e.sym)
903 error("cannot relocate");
904 gen_le16(ops[0].e.v);
905 return;
906 }
907 #endif
908 for(i = 0;i < nb_ops; i++) {
909 v = op_type[i];
910 if (v & (OP_IM8 | OP_IM16 | OP_IM32 | OP_IM64 | OP_IM8S | OP_ADDR)) {
911 /* if multiple sizes are given it means we must look
912 at the op size */
913 if ((v | OP_IM8 | OP_IM64) == (OP_IM8 | OP_IM16 | OP_IM32 | OP_IM64)) {
914 if (s == 0)
915 v = OP_IM8;
916 else if (s == 1)
917 v = OP_IM16;
918 else if (s == 2 || (v & OP_IM64) == 0)
919 v = OP_IM32;
920 else
921 v = OP_IM64;
922 }
923 if (v & (OP_IM8 | OP_IM8S)) {
924 if (ops[i].e.sym)
925 goto error_relocate;
926 g(ops[i].e.v);
927 } else if (v & OP_IM16) {
928 #ifdef I386_ASM_16
929 if (s1->seg_size == 16)
930 gen_expr16(&ops[i].e);
931 else
932 #endif
933 if (ops[i].e.sym)
934 error_relocate:
935 error("cannot relocate");
936 else
937 gen_le16(ops[i].e.v);
938 } else {
939 if (pa->instr_type & (OPC_JMP | OPC_SHORTJMP)) {
940 if (is_short_jmp)
941 g(ops[i].e.v);
942 #ifdef I386_ASM_16
943 else if (s1->seg_size == 16)
944 gen_disp16(&ops[i].e);
945 #endif
946 else
947 gen_disp32(&ops[i].e);
948 } else {
949 #ifdef I386_ASM_16
950 if (s1->seg_size == 16 && !((o32 == 1) && (v & OP_IM32)))
951 gen_expr16(&ops[i].e);
952 else
953 #endif
954 #ifdef TCC_TARGET_X86_64
955 if (v & OP_IM64)
956 gen_expr64(&ops[i].e);
957 else
958 #endif
959 gen_expr32(&ops[i].e);
960 }
961 }
962 #ifdef I386_ASM_16
963 } else if (v & (OP_REG16 | OP_REG32)) {
964 if (pa->instr_type & (OPC_JMP | OPC_SHORTJMP)) {
965 /* jmp $r */
966 g(0xE0 + ops[i].reg);
967 }
968 #endif
969 #ifdef TCC_TARGET_X86_64
970 } else if (v & (OP_REG32 | OP_REG64)) {
971 if (pa->instr_type & (OPC_JMP | OPC_SHORTJMP)) {
972 /* jmp $r */
973 g(0xE0 + ops[i].reg);
974 }
975 #endif
976 }
977 }
978 #ifdef I386_ASM_16
979 a32 = o32 = 0;
980 #endif
981 }
982
983 /* return the constraint priority (we allocate first the lowest
984 numbered constraints) */
985 static inline int constraint_priority(const char *str)
986 {
987 int priority, c, pr;
988
989 /* we take the lowest priority */
990 priority = 0;
991 for(;;) {
992 c = *str;
993 if (c == '\0')
994 break;
995 str++;
996 switch(c) {
997 case 'A':
998 pr = 0;
999 break;
1000 case 'a':
1001 case 'b':
1002 case 'c':
1003 case 'd':
1004 case 'S':
1005 case 'D':
1006 pr = 1;
1007 break;
1008 case 'q':
1009 pr = 2;
1010 break;
1011 case 'r':
1012 pr = 3;
1013 break;
1014 case 'N':
1015 case 'M':
1016 case 'I':
1017 case 'i':
1018 case 'm':
1019 case 'g':
1020 pr = 4;
1021 break;
1022 default:
1023 error("unknown constraint '%c'", c);
1024 pr = 0;
1025 }
1026 if (pr > priority)
1027 priority = pr;
1028 }
1029 return priority;
1030 }
1031
1032 static const char *skip_constraint_modifiers(const char *p)
1033 {
1034 while (*p == '=' || *p == '&' || *p == '+' || *p == '%')
1035 p++;
1036 return p;
1037 }
1038
1039 #define REG_OUT_MASK 0x01
1040 #define REG_IN_MASK 0x02
1041
1042 #define is_reg_allocated(reg) (regs_allocated[reg] & reg_mask)
1043
1044 ST_FUNC void asm_compute_constraints(ASMOperand *operands,
1045 int nb_operands, int nb_outputs,
1046 const uint8_t *clobber_regs,
1047 int *pout_reg)
1048 {
1049 ASMOperand *op;
1050 int sorted_op[MAX_ASM_OPERANDS];
1051 int i, j, k, p1, p2, tmp, reg, c, reg_mask;
1052 const char *str;
1053 uint8_t regs_allocated[NB_ASM_REGS];
1054
1055 /* init fields */
1056 for(i=0;i<nb_operands;i++) {
1057 op = &operands[i];
1058 op->input_index = -1;
1059 op->ref_index = -1;
1060 op->reg = -1;
1061 op->is_memory = 0;
1062 op->is_rw = 0;
1063 }
1064 /* compute constraint priority and evaluate references to output
1065 constraints if input constraints */
1066 for(i=0;i<nb_operands;i++) {
1067 op = &operands[i];
1068 str = op->constraint;
1069 str = skip_constraint_modifiers(str);
1070 if (isnum(*str) || *str == '[') {
1071 /* this is a reference to another constraint */
1072 k = find_constraint(operands, nb_operands, str, NULL);
1073 if ((unsigned)k >= i || i < nb_outputs)
1074 error("invalid reference in constraint %d ('%s')",
1075 i, str);
1076 op->ref_index = k;
1077 if (operands[k].input_index >= 0)
1078 error("cannot reference twice the same operand");
1079 operands[k].input_index = i;
1080 op->priority = 5;
1081 } else {
1082 op->priority = constraint_priority(str);
1083 }
1084 }
1085
1086 /* sort operands according to their priority */
1087 for(i=0;i<nb_operands;i++)
1088 sorted_op[i] = i;
1089 for(i=0;i<nb_operands - 1;i++) {
1090 for(j=i+1;j<nb_operands;j++) {
1091 p1 = operands[sorted_op[i]].priority;
1092 p2 = operands[sorted_op[j]].priority;
1093 if (p2 < p1) {
1094 tmp = sorted_op[i];
1095 sorted_op[i] = sorted_op[j];
1096 sorted_op[j] = tmp;
1097 }
1098 }
1099 }
1100
1101 for(i = 0;i < NB_ASM_REGS; i++) {
1102 if (clobber_regs[i])
1103 regs_allocated[i] = REG_IN_MASK | REG_OUT_MASK;
1104 else
1105 regs_allocated[i] = 0;
1106 }
1107 /* esp cannot be used */
1108 regs_allocated[4] = REG_IN_MASK | REG_OUT_MASK;
1109 /* ebp cannot be used yet */
1110 regs_allocated[5] = REG_IN_MASK | REG_OUT_MASK;
1111
1112 /* allocate registers and generate corresponding asm moves */
1113 for(i=0;i<nb_operands;i++) {
1114 j = sorted_op[i];
1115 op = &operands[j];
1116 str = op->constraint;
1117 /* no need to allocate references */
1118 if (op->ref_index >= 0)
1119 continue;
1120 /* select if register is used for output, input or both */
1121 if (op->input_index >= 0) {
1122 reg_mask = REG_IN_MASK | REG_OUT_MASK;
1123 } else if (j < nb_outputs) {
1124 reg_mask = REG_OUT_MASK;
1125 } else {
1126 reg_mask = REG_IN_MASK;
1127 }
1128 try_next:
1129 c = *str++;
1130 switch(c) {
1131 case '=':
1132 goto try_next;
1133 case '+':
1134 op->is_rw = 1;
1135 /* FALL THRU */
1136 case '&':
1137 if (j >= nb_outputs)
1138 error("'%c' modifier can only be applied to outputs", c);
1139 reg_mask = REG_IN_MASK | REG_OUT_MASK;
1140 goto try_next;
1141 case 'A':
1142 /* allocate both eax and edx */
1143 if (is_reg_allocated(TREG_XAX) ||
1144 is_reg_allocated(TREG_XDX))
1145 goto try_next;
1146 op->is_llong = 1;
1147 op->reg = TREG_XAX;
1148 regs_allocated[TREG_XAX] |= reg_mask;
1149 regs_allocated[TREG_XDX] |= reg_mask;
1150 break;
1151 case 'a':
1152 reg = TREG_XAX;
1153 goto alloc_reg;
1154 case 'b':
1155 reg = 3;
1156 goto alloc_reg;
1157 case 'c':
1158 reg = TREG_XCX;
1159 goto alloc_reg;
1160 case 'd':
1161 reg = TREG_XDX;
1162 goto alloc_reg;
1163 case 'S':
1164 reg = 6;
1165 goto alloc_reg;
1166 case 'D':
1167 reg = 7;
1168 alloc_reg:
1169 if (is_reg_allocated(reg))
1170 goto try_next;
1171 goto reg_found;
1172 case 'q':
1173 /* eax, ebx, ecx or edx */
1174 for(reg = 0; reg < 4; reg++) {
1175 if (!is_reg_allocated(reg))
1176 goto reg_found;
1177 }
1178 goto try_next;
1179 case 'r':
1180 /* any general register */
1181 for(reg = 0; reg < 8; reg++) {
1182 if (!is_reg_allocated(reg))
1183 goto reg_found;
1184 }
1185 goto try_next;
1186 reg_found:
1187 /* now we can reload in the register */
1188 op->is_llong = 0;
1189 op->reg = reg;
1190 regs_allocated[reg] |= reg_mask;
1191 break;
1192 case 'i':
1193 if (!((op->vt->r & (VT_VALMASK | VT_LVAL)) == VT_CONST))
1194 goto try_next;
1195 break;
1196 case 'I':
1197 case 'N':
1198 case 'M':
1199 if (!((op->vt->r & (VT_VALMASK | VT_LVAL | VT_SYM)) == VT_CONST))
1200 goto try_next;
1201 break;
1202 case 'm':
1203 case 'g':
1204 /* nothing special to do because the operand is already in
1205 memory, except if the pointer itself is stored in a
1206 memory variable (VT_LLOCAL case) */
1207 /* XXX: fix constant case */
1208 /* if it is a reference to a memory zone, it must lie
1209 in a register, so we reserve the register in the
1210 input registers and a load will be generated
1211 later */
1212 if (j < nb_outputs || c == 'm') {
1213 if ((op->vt->r & VT_VALMASK) == VT_LLOCAL) {
1214 /* any general register */
1215 for(reg = 0; reg < 8; reg++) {
1216 if (!(regs_allocated[reg] & REG_IN_MASK))
1217 goto reg_found1;
1218 }
1219 goto try_next;
1220 reg_found1:
1221 /* now we can reload in the register */
1222 regs_allocated[reg] |= REG_IN_MASK;
1223 op->reg = reg;
1224 op->is_memory = 1;
1225 }
1226 }
1227 break;
1228 default:
1229 error("asm constraint %d ('%s') could not be satisfied",
1230 j, op->constraint);
1231 break;
1232 }
1233 /* if a reference is present for that operand, we assign it too */
1234 if (op->input_index >= 0) {
1235 operands[op->input_index].reg = op->reg;
1236 operands[op->input_index].is_llong = op->is_llong;
1237 }
1238 }
1239
1240 /* compute out_reg. It is used to store outputs registers to memory
1241 locations references by pointers (VT_LLOCAL case) */
1242 *pout_reg = -1;
1243 for(i=0;i<nb_operands;i++) {
1244 op = &operands[i];
1245 if (op->reg >= 0 &&
1246 (op->vt->r & VT_VALMASK) == VT_LLOCAL &&
1247 !op->is_memory) {
1248 for(reg = 0; reg < 8; reg++) {
1249 if (!(regs_allocated[reg] & REG_OUT_MASK))
1250 goto reg_found2;
1251 }
1252 error("could not find free output register for reloading");
1253 reg_found2:
1254 *pout_reg = reg;
1255 break;
1256 }
1257 }
1258
1259 /* print sorted constraints */
1260 #ifdef ASM_DEBUG
1261 for(i=0;i<nb_operands;i++) {
1262 j = sorted_op[i];
1263 op = &operands[j];
1264 printf("%%%d [%s]: \"%s\" r=0x%04x reg=%d\n",
1265 j,
1266 op->id ? get_tok_str(op->id, NULL) : "",
1267 op->constraint,
1268 op->vt->r,
1269 op->reg);
1270 }
1271 if (*pout_reg >= 0)
1272 printf("out_reg=%d\n", *pout_reg);
1273 #endif
1274 }
1275
1276 ST_FUNC void subst_asm_operand(CString *add_str,
1277 SValue *sv, int modifier)
1278 {
1279 int r, reg, size, val;
1280 char buf[64];
1281
1282 r = sv->r;
1283 if ((r & VT_VALMASK) == VT_CONST) {
1284 if (!(r & VT_LVAL) && modifier != 'c' && modifier != 'n')
1285 cstr_ccat(add_str, '$');
1286 if (r & VT_SYM) {
1287 cstr_cat(add_str, get_tok_str(sv->sym->v, NULL));
1288 if (sv->c.i != 0) {
1289 cstr_ccat(add_str, '+');
1290 } else {
1291 return;
1292 }
1293 }
1294 val = sv->c.i;
1295 if (modifier == 'n')
1296 val = -val;
1297 snprintf(buf, sizeof(buf), "%d", sv->c.i);
1298 cstr_cat(add_str, buf);
1299 } else if ((r & VT_VALMASK) == VT_LOCAL) {
1300 snprintf(buf, sizeof(buf), "%d(%%ebp)", sv->c.i);
1301 cstr_cat(add_str, buf);
1302 } else if (r & VT_LVAL) {
1303 reg = r & VT_VALMASK;
1304 if (reg >= VT_CONST)
1305 error("internal compiler error");
1306 snprintf(buf, sizeof(buf), "(%%%s)",
1307 get_tok_str(TOK_ASM_eax + reg, NULL));
1308 cstr_cat(add_str, buf);
1309 } else {
1310 /* register case */
1311 reg = r & VT_VALMASK;
1312 if (reg >= VT_CONST)
1313 error("internal compiler error");
1314
1315 /* choose register operand size */
1316 if ((sv->type.t & VT_BTYPE) == VT_BYTE)
1317 size = 1;
1318 else if ((sv->type.t & VT_BTYPE) == VT_SHORT)
1319 size = 2;
1320 #ifdef TCC_TARGET_X86_64
1321 else if ((sv->type.t & VT_BTYPE) == VT_LLONG)
1322 size = 8;
1323 #endif
1324 else
1325 size = 4;
1326 if (size == 1 && reg >= 4)
1327 size = 4;
1328
1329 if (modifier == 'b') {
1330 if (reg >= 4)
1331 error("cannot use byte register");
1332 size = 1;
1333 } else if (modifier == 'h') {
1334 if (reg >= 4)
1335 error("cannot use byte register");
1336 size = -1;
1337 } else if (modifier == 'w') {
1338 size = 2;
1339 #ifdef TCC_TARGET_X86_64
1340 } else if (modifier == 'q') {
1341 size = 8;
1342 #endif
1343 }
1344
1345 switch(size) {
1346 case -1:
1347 reg = TOK_ASM_ah + reg;
1348 break;
1349 case 1:
1350 reg = TOK_ASM_al + reg;
1351 break;
1352 case 2:
1353 reg = TOK_ASM_ax + reg;
1354 break;
1355 default:
1356 reg = TOK_ASM_eax + reg;
1357 break;
1358 #ifdef TCC_TARGET_X86_64
1359 case 8:
1360 reg = TOK_ASM_rax + reg;
1361 break;
1362 #endif
1363 }
1364 snprintf(buf, sizeof(buf), "%%%s", get_tok_str(reg, NULL));
1365 cstr_cat(add_str, buf);
1366 }
1367 }
1368
1369 /* generate prolog and epilog code for asm statment */
1370 ST_FUNC void asm_gen_code(ASMOperand *operands, int nb_operands,
1371 int nb_outputs, int is_output,
1372 uint8_t *clobber_regs,
1373 int out_reg)
1374 {
1375 uint8_t regs_allocated[NB_ASM_REGS];
1376 ASMOperand *op;
1377 int i, reg;
1378 static uint8_t reg_saved[NB_SAVED_REGS] = { 3, 6, 7 };
1379
1380 /* mark all used registers */
1381 memcpy(regs_allocated, clobber_regs, sizeof(regs_allocated));
1382 for(i = 0; i < nb_operands;i++) {
1383 op = &operands[i];
1384 if (op->reg >= 0)
1385 regs_allocated[op->reg] = 1;
1386 }
1387 if (!is_output) {
1388 /* generate reg save code */
1389 for(i = 0; i < NB_SAVED_REGS; i++) {
1390 reg = reg_saved[i];
1391 if (regs_allocated[reg]) {
1392 #ifdef I386_ASM_16
1393 if (tcc_state->seg_size == 16)
1394 g(0x66);
1395 #endif
1396 g(0x50 + reg);
1397 }
1398 }
1399
1400 /* generate load code */
1401 for(i = 0; i < nb_operands; i++) {
1402 op = &operands[i];
1403 if (op->reg >= 0) {
1404 if ((op->vt->r & VT_VALMASK) == VT_LLOCAL &&
1405 op->is_memory) {
1406 /* memory reference case (for both input and
1407 output cases) */
1408 SValue sv;
1409 sv = *op->vt;
1410 sv.r = (sv.r & ~VT_VALMASK) | VT_LOCAL;
1411 load(op->reg, &sv);
1412 } else if (i >= nb_outputs || op->is_rw) {
1413 /* load value in register */
1414 load(op->reg, op->vt);
1415 if (op->is_llong) {
1416 SValue sv;
1417 sv = *op->vt;
1418 sv.c.ul += 4;
1419 load(TREG_XDX, &sv);
1420 }
1421 }
1422 }
1423 }
1424 } else {
1425 /* generate save code */
1426 for(i = 0 ; i < nb_outputs; i++) {
1427 op = &operands[i];
1428 if (op->reg >= 0) {
1429 if ((op->vt->r & VT_VALMASK) == VT_LLOCAL) {
1430 if (!op->is_memory) {
1431 SValue sv;
1432 sv = *op->vt;
1433 sv.r = (sv.r & ~VT_VALMASK) | VT_LOCAL;
1434 load(out_reg, &sv);
1435
1436 sv.r = (sv.r & ~VT_VALMASK) | out_reg;
1437 store(op->reg, &sv);
1438 }
1439 } else {
1440 store(op->reg, op->vt);
1441 if (op->is_llong) {
1442 SValue sv;
1443 sv = *op->vt;
1444 sv.c.ul += 4;
1445 store(TREG_XDX, &sv);
1446 }
1447 }
1448 }
1449 }
1450 /* generate reg restore code */
1451 for(i = NB_SAVED_REGS - 1; i >= 0; i--) {
1452 reg = reg_saved[i];
1453 if (regs_allocated[reg]) {
1454 #ifdef I386_ASM_16
1455 if (tcc_state->seg_size == 16)
1456 g(0x66);
1457 #endif
1458 g(0x58 + reg);
1459 }
1460 }
1461 }
1462 }
1463
1464 ST_FUNC void asm_clobber(uint8_t *clobber_regs, const char *str)
1465 {
1466 int reg;
1467 TokenSym *ts;
1468
1469 if (!strcmp(str, "memory") ||
1470 !strcmp(str, "cc"))
1471 return;
1472 ts = tok_alloc(str, strlen(str));
1473 reg = ts->tok;
1474 if (reg >= TOK_ASM_eax && reg <= TOK_ASM_edi) {
1475 reg -= TOK_ASM_eax;
1476 } else if (reg >= TOK_ASM_ax && reg <= TOK_ASM_di) {
1477 reg -= TOK_ASM_ax;
1478 #ifdef TCC_TARGET_X86_64
1479 } else if (reg >= TOK_ASM_rax && reg <= TOK_ASM_rdi) {
1480 reg -= TOK_ASM_rax;
1481 #endif
1482 } else {
1483 error("invalid clobber register '%s'", str);
1484 }
1485 clobber_regs[reg] = 1;
1486 }
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