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asm 32/64: replace (long)sym->next by sym->jnext
[tinycc.git] / i386-asm.c
blob4b1dd8f2101e3517665ff78d1c38c05b58c104d9
1 /*
2 * i386 specific functions for TCC assembler
3 *
4 * Copyright (c) 2001, 2002 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21 #define MAX_OPERANDS 3
22
23 typedef struct ASMInstr {
24 uint16_t sym;
25 uint16_t opcode;
26 uint16_t instr_type;
27 #define OPC_JMP 0x01 /* jmp operand */
28 #define OPC_B 0x02 /* only used zith OPC_WL */
29 #define OPC_WL 0x04 /* accepts w, l or no suffix */
30 #define OPC_BWL (OPC_B | OPC_WL) /* accepts b, w, l or no suffix */
31 #define OPC_REG 0x08 /* register is added to opcode */
32 #define OPC_MODRM 0x10 /* modrm encoding */
33 #define OPC_FWAIT 0x20 /* add fwait opcode */
34 #define OPC_TEST 0x40 /* test opcodes */
35 #define OPC_SHIFT 0x80 /* shift opcodes */
36 #define OPC_D16 0x0100 /* generate data16 prefix */
37 #define OPC_ARITH 0x0200 /* arithmetic opcodes */
38 #define OPC_SHORTJMP 0x0400 /* short jmp operand */
39 #define OPC_FARITH 0x0800 /* FPU arithmetic opcodes */
40 #define OPC_GROUP_SHIFT 13
41
42 /* in order to compress the operand type, we use specific operands and
43 we or only with EA */
44 #define OPT_REG8 0 /* warning: value is hardcoded from TOK_ASM_xxx */
45 #define OPT_REG16 1 /* warning: value is hardcoded from TOK_ASM_xxx */
46 #define OPT_REG32 2 /* warning: value is hardcoded from TOK_ASM_xxx */
47 #define OPT_MMX 3 /* warning: value is hardcoded from TOK_ASM_xxx */
48 #define OPT_SSE 4 /* warning: value is hardcoded from TOK_ASM_xxx */
49 #define OPT_CR 5 /* warning: value is hardcoded from TOK_ASM_xxx */
50 #define OPT_TR 6 /* warning: value is hardcoded from TOK_ASM_xxx */
51 #define OPT_DB 7 /* warning: value is hardcoded from TOK_ASM_xxx */
52 #define OPT_SEG 8
53 #define OPT_ST 9
54 #define OPT_IM8 10
55 #define OPT_IM8S 11
56 #define OPT_IM16 12
57 #define OPT_IM32 13
58 #define OPT_EAX 14 /* %al, %ax or %eax register */
59 #define OPT_ST0 15 /* %st(0) register */
60 #define OPT_CL 16 /* %cl register */
61 #define OPT_DX 17 /* %dx register */
62 #define OPT_ADDR 18 /* OP_EA with only offset */
63 #define OPT_INDIR 19 /* *(expr) */
64
65 /* composite types */
66 #define OPT_COMPOSITE_FIRST 20
67 #define OPT_IM 20 /* IM8 | IM16 | IM32 */
68 #define OPT_REG 21 /* REG8 | REG16 | REG32 */
69 #define OPT_REGW 22 /* REG16 | REG32 */
70 #define OPT_IMW 23 /* IM16 | IM32 */
71
72 /* can be ored with any OPT_xxx */
73 #define OPT_EA 0x80
74
75 uint8_t nb_ops;
76 uint8_t op_type[MAX_OPERANDS]; /* see OP_xxx */
77 } ASMInstr;
78
79 typedef struct Operand {
80 uint32_t type;
81 #define OP_REG8 (1 << OPT_REG8)
82 #define OP_REG16 (1 << OPT_REG16)
83 #define OP_REG32 (1 << OPT_REG32)
84 #define OP_MMX (1 << OPT_MMX)
85 #define OP_SSE (1 << OPT_SSE)
86 #define OP_CR (1 << OPT_CR)
87 #define OP_TR (1 << OPT_TR)
88 #define OP_DB (1 << OPT_DB)
89 #define OP_SEG (1 << OPT_SEG)
90 #define OP_ST (1 << OPT_ST)
91 #define OP_IM8 (1 << OPT_IM8)
92 #define OP_IM8S (1 << OPT_IM8S)
93 #define OP_IM16 (1 << OPT_IM16)
94 #define OP_IM32 (1 << OPT_IM32)
95 #define OP_EAX (1 << OPT_EAX)
96 #define OP_ST0 (1 << OPT_ST0)
97 #define OP_CL (1 << OPT_CL)
98 #define OP_DX (1 << OPT_DX)
99 #define OP_ADDR (1 << OPT_ADDR)
100 #define OP_INDIR (1 << OPT_INDIR)
101
102 #define OP_EA 0x40000000
103 #define OP_REG (OP_REG8 | OP_REG16 | OP_REG32)
104 #define OP_IM OP_IM32
105 int8_t reg; /* register, -1 if none */
106 int8_t reg2; /* second register, -1 if none */
107 uint8_t shift;
108 ExprValue e;
109 } Operand;
110
111 static const uint8_t reg_to_size[5] = {
112 /*
113 [OP_REG8] = 0,
114 [OP_REG16] = 1,
115 [OP_REG32] = 2,
116 */
117 0, 0, 1, 0, 2
118 };
119
120 #define NB_TEST_OPCODES 30
121
122 static const uint8_t test_bits[NB_TEST_OPCODES] = {
123 0x00, /* o */
124 0x01, /* no */
125 0x02, /* b */
126 0x02, /* c */
127 0x02, /* nae */
128 0x03, /* nb */
129 0x03, /* nc */
130 0x03, /* ae */
131 0x04, /* e */
132 0x04, /* z */
133 0x05, /* ne */
134 0x05, /* nz */
135 0x06, /* be */
136 0x06, /* na */
137 0x07, /* nbe */
138 0x07, /* a */
139 0x08, /* s */
140 0x09, /* ns */
141 0x0a, /* p */
142 0x0a, /* pe */
143 0x0b, /* np */
144 0x0b, /* po */
145 0x0c, /* l */
146 0x0c, /* nge */
147 0x0d, /* nl */
148 0x0d, /* ge */
149 0x0e, /* le */
150 0x0e, /* ng */
151 0x0f, /* nle */
152 0x0f, /* g */
153 };
154
155 static const uint8_t segment_prefixes[] = {
156 0x26, /* es */
157 0x2e, /* cs */
158 0x36, /* ss */
159 0x3e, /* ds */
160 0x64, /* fs */
161 0x65 /* gs */
162 };
163
164 static const ASMInstr asm_instrs[] = {
165 #define ALT(x) x
166 #define DEF_ASM_OP0(name, opcode)
167 #define DEF_ASM_OP0L(name, opcode, group, instr_type) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 0 },
168 #define DEF_ASM_OP1(name, opcode, group, instr_type, op0) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 1, { op0 }},
169 #define DEF_ASM_OP2(name, opcode, group, instr_type, op0, op1) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 2, { op0, op1 }},
170 #define DEF_ASM_OP3(name, opcode, group, instr_type, op0, op1, op2) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 3, { op0, op1, op2 }},
171 #include "i386-asm.h"
172
173 /* last operation */
174 { 0, },
175 };
176
177 static const uint16_t op0_codes[] = {
178 #define ALT(x)
179 #define DEF_ASM_OP0(x, opcode) opcode,
180 #define DEF_ASM_OP0L(name, opcode, group, instr_type)
181 #define DEF_ASM_OP1(name, opcode, group, instr_type, op0)
182 #define DEF_ASM_OP2(name, opcode, group, instr_type, op0, op1)
183 #define DEF_ASM_OP3(name, opcode, group, instr_type, op0, op1, op2)
184 #include "i386-asm.h"
185 };
186
187 static inline int get_reg_shift(TCCState *s1)
188 {
189 int shift, v;
190
191 if (s1->seg_size == 16) {
192 error("invalid effective address");
193 }
194
195 v = asm_int_expr(s1);
196 switch(v) {
197 case 1:
198 shift = 0;
199 break;
200 case 2:
201 shift = 1;
202 break;
203 case 4:
204 shift = 2;
205 break;
206 case 8:
207 shift = 3;
208 break;
209 default:
210 expect("1, 2, 4 or 8 constant");
211 shift = 0;
212 break;
213 }
214 return shift;
215 }
216
217 static int asm_parse_reg(void)
218 {
219 int reg;
220 if (tok != '%')
221 goto error_32;
222 next();
223 if (tok >= TOK_ASM_eax && tok <= TOK_ASM_edi) {
224 reg = tok - TOK_ASM_eax;
225 next();
226 return reg;
227 } else if (tok >= TOK_ASM_ax && tok <= TOK_ASM_di) {
228 reg = tok - TOK_ASM_ax;
229 next();
230 return reg;
231 } else {
232 error_32:
233 expect("register");
234 return 0;
235 }
236 }
237
238 static void parse_operand(TCCState *s1, Operand *op)
239 {
240 ExprValue e;
241 int reg, indir;
242 const char *p;
243
244 indir = 0;
245 if (tok == '*') {
246 next();
247 indir = OP_INDIR;
248 }
249
250 if (tok == '%') {
251 next();
252 if (tok >= TOK_ASM_al && tok <= TOK_ASM_db7) {
253 reg = tok - TOK_ASM_al;
254 op->type = 1 << (reg >> 3); /* WARNING: do not change constant order */
255 op->reg = reg & 7;
256 if ((op->type & OP_REG) && op->reg == TREG_EAX)
257 op->type |= OP_EAX;
258 else if (op->type == OP_REG8 && op->reg == TREG_ECX)
259 op->type |= OP_CL;
260 else if (op->type == OP_REG16 && op->reg == TREG_EDX)
261 op->type |= OP_DX;
262 } else if (tok >= TOK_ASM_dr0 && tok <= TOK_ASM_dr7) {
263 op->type = OP_DB;
264 op->reg = tok - TOK_ASM_dr0;
265 } else if (tok >= TOK_ASM_es && tok <= TOK_ASM_gs) {
266 op->type = OP_SEG;
267 op->reg = tok - TOK_ASM_es;
268 } else if (tok == TOK_ASM_st) {
269 op->type = OP_ST;
270 op->reg = 0;
271 next();
272 if (tok == '(') {
273 next();
274 if (tok != TOK_PPNUM)
275 goto reg_error;
276 p = tokc.cstr->data;
277 reg = p[0] - '0';
278 if ((unsigned)reg >= 8 || p[1] != '\0')
279 goto reg_error;
280 op->reg = reg;
281 next();
282 skip(')');
283 }
284 if (op->reg == 0)
285 op->type |= OP_ST0;
286 goto no_skip;
287 } else {
288 reg_error:
289 error("unknown register");
290 }
291 next();
292 no_skip: ;
293 } else if (tok == '$') {
294 /* constant value */
295 next();
296 asm_expr(s1, &e);
297 op->type = OP_IM32;
298 op->e.v = e.v;
299 op->e.sym = e.sym;
300 if (!op->e.sym) {
301 if (op->e.v == (uint8_t)op->e.v)
302 op->type |= OP_IM8;
303 if (op->e.v == (int8_t)op->e.v)
304 op->type |= OP_IM8S;
305 if (op->e.v == (uint16_t)op->e.v)
306 op->type |= OP_IM16;
307 }
308 } else {
309 /* address(reg,reg2,shift) with all variants */
310 op->type = OP_EA;
311 op->reg = -1;
312 op->reg2 = -1;
313 op->shift = 0;
314 if (tok != '(') {
315 asm_expr(s1, &e);
316 op->e.v = e.v;
317 op->e.sym = e.sym;
318 } else {
319 op->e.v = 0;
320 op->e.sym = NULL;
321 }
322 if (tok == '(') {
323 next();
324 if (tok != ',') {
325 op->reg = asm_parse_reg();
326 }
327 if (tok == ',') {
328 next();
329 if (tok != ',') {
330 op->reg2 = asm_parse_reg();
331 }
332 if (tok == ',') {
333 next();
334 op->shift = get_reg_shift(s1);
335 }
336 }
337 skip(')');
338 }
339 if (op->reg == -1 && op->reg2 == -1)
340 op->type |= OP_ADDR;
341 }
342 op->type |= indir;
343 }
344
345 static void gen_le16(int v)
346 {
347 g(v);
348 g(v >> 8);
349 }
350
351 /* XXX: unify with C code output ? */
352 static void gen_expr32(ExprValue *pe)
353 {
354 if (pe->sym)
355 greloc(cur_text_section, pe->sym, ind, R_386_32);
356 gen_le32(pe->v);
357 }
358
359 static void gen_expr16(ExprValue *pe)
360 {
361 if (pe->sym)
362 greloc(cur_text_section, pe->sym, ind, R_386_16);
363 gen_le16(pe->v);
364 }
365
366 /* XXX: unify with C code output ? */
367 static void gen_disp32(ExprValue *pe)
368 {
369 Sym *sym;
370 sym = pe->sym;
371 if (sym) {
372 if (sym->r == cur_text_section->sh_num) {
373 /* same section: we can output an absolute value. Note
374 that the TCC compiler behaves differently here because
375 it always outputs a relocation to ease (future) code
376 elimination in the linker */
377 gen_le32(pe->v + sym->jnext - ind - 4);
378 } else {
379 greloc(cur_text_section, sym, ind, R_386_PC32);
380 gen_le32(pe->v - 4);
381 }
382 } else {
383 /* put an empty PC32 relocation */
384 put_elf_reloc(symtab_section, cur_text_section,
385 ind, R_386_PC32, 0);
386 gen_le32(pe->v - 4);
387 }
388 }
389
390 static void gen_disp16(ExprValue *pe)
391 {
392 Sym *sym;
393 sym = pe->sym;
394 if (sym) {
395 if (sym->r == cur_text_section->sh_num) {
396 /* same section: we can output an absolute value. Note
397 that the TCC compiler behaves differently here because
398 it always outputs a relocation to ease (future) code
399 elimination in the linker */
400 gen_le16(pe->v + sym->jnext - ind - 2);
401 } else {
402 greloc(cur_text_section, sym, ind, R_386_PC16);
403 gen_le16(pe->v - 2);
404 }
405 } else {
406 /* put an empty PC32 relocation */
407 put_elf_reloc(symtab_section, cur_text_section,
408 ind, R_386_PC16, 0);
409 gen_le16(pe->v - 2);
410 }
411 }
412
413 /* generate the modrm operand */
414 static inline void asm_modrm(int reg, Operand *op)
415 {
416 int mod, reg1, reg2, sib_reg1;
417
418 if (op->type & (OP_REG | OP_MMX | OP_SSE)) {
419 g(0xc0 + (reg << 3) + op->reg);
420 } else if (op->reg == -1 && op->reg2 == -1) {
421 /* displacement only */
422 if (tcc_state->seg_size == 16) {
423 g(0x06 + (reg << 3));
424 gen_expr16(&op->e);
425 } else if (tcc_state->seg_size == 32) {
426 g(0x05 + (reg << 3));
427 gen_expr32(&op->e);
428 }
429 } else {
430 sib_reg1 = op->reg;
431 /* fist compute displacement encoding */
432 if (sib_reg1 == -1) {
433 sib_reg1 = 5;
434 mod = 0x00;
435 } else if (op->e.v == 0 && !op->e.sym && op->reg != 5) {
436 mod = 0x00;
437 } else if (op->e.v == (int8_t)op->e.v && !op->e.sym) {
438 mod = 0x40;
439 } else {
440 mod = 0x80;
441 }
442 /* compute if sib byte needed */
443 reg1 = op->reg;
444 if (op->reg2 != -1)
445 reg1 = 4;
446 if (tcc_state->seg_size == 32) {
447 g(mod + (reg << 3) + reg1);
448 if (reg1 == 4) {
449 /* add sib byte */
450 reg2 = op->reg2;
451 if (reg2 == -1)
452 reg2 = 4; /* indicate no index */
453 g((op->shift << 6) + (reg2 << 3) + sib_reg1);
454 }
455 } else if (tcc_state->seg_size == 16) {
456 /* edi = 7, esi = 6 --> di = 5, si = 4 */
457 if ((reg1 == 6) || (reg1 == 7)) {
458 reg1 -= 2;
459 /* ebx = 3 --> bx = 7 */
460 } else if (reg1 == 3) {
461 reg1 = 7;
462 /* o32 = 5 --> o16 = 6 */
463 } else if (reg1 == 5) {
464 reg1 = 6;
465 /* sib not valid in 16-bit mode */
466 } else if (reg1 == 4) {
467 reg2 = op->reg2;
468 /* bp + si + offset */
469 if ((sib_reg1 == 5) && (reg2 == 6)) {
470 reg1 = 2;
471 /* bp + di + offset */
472 } else if ((sib_reg1 == 5) && (reg2 == 7)) {
473 reg1 = 3;
474 /* bx + si + offset */
475 } else if ((sib_reg1 == 3) && (reg2 == 6)) {
476 reg1 = 0;
477 /* bx + di + offset */
478 } else if ((sib_reg1 == 3) && (reg2 == 7)) {
479 reg1 = 1;
480 } else {
481 error("invalid effective address");
482 }
483 if (op->e.v == 0)
484 mod = 0;
485 } else {
486 error("invalid register");
487 }
488 g(mod + (reg << 3) + reg1);
489 }
490
491 /* add offset */
492 if (mod == 0x40) {
493 g(op->e.v);
494 } else if (mod == 0x80 || op->reg == -1) {
495 if (tcc_state->seg_size == 16)
496 gen_expr16(&op->e);
497 else if (tcc_state->seg_size == 32)
498 gen_expr32(&op->e);
499 }
500 }
501 }
502
503 static void asm_opcode(TCCState *s1, int opcode)
504 {
505 const ASMInstr *pa;
506 int i, modrm_index, reg, v, op1, is_short_jmp, seg_prefix;
507 int nb_ops, s;
508 Operand ops[MAX_OPERANDS], *pop;
509 int op_type[3]; /* decoded op type */
510
511 int a32, o32;
512 static int addr32 = 0, data32 = 0;
513
514 /* get operands */
515 pop = ops;
516 nb_ops = 0;
517 seg_prefix = 0;
518 for(;;) {
519 if (tok == ';' || tok == TOK_LINEFEED)
520 break;
521 if (nb_ops >= MAX_OPERANDS) {
522 error("incorrect number of operands");
523 }
524 parse_operand(s1, pop);
525 if (tok == ':') {
526 if (pop->type != OP_SEG || seg_prefix) {
527 bad_prefix:
528 error("incorrect prefix");
529 }
530 seg_prefix = segment_prefixes[pop->reg];
531 next();
532 parse_operand(s1, pop);
533 #if 0
534 if (!(pop->type & OP_EA)) {
535 error("segment prefix must be followed by memory reference");
536 }
537 #endif
538 }
539 pop++;
540 nb_ops++;
541 if (tok != ',')
542 break;
543 next();
544 }
545
546 is_short_jmp = 0;
547 s = 0; /* avoid warning */
548
549 /* optimize matching by using a lookup table (no hashing is needed
550 !) */
551 for(pa = asm_instrs; pa->sym != 0; pa++) {
552 s = 0;
553 if (pa->instr_type & OPC_FARITH) {
554 v = opcode - pa->sym;
555 if (!((unsigned)v < 8 * 6 && (v % 6) == 0))
556 continue;
557 } else if (pa->instr_type & OPC_ARITH) {
558 if (!(opcode >= pa->sym && opcode < pa->sym + 8 * 4))
559 continue;
560 goto compute_size;
561 } else if (pa->instr_type & OPC_SHIFT) {
562 if (!(opcode >= pa->sym && opcode < pa->sym + 7 * 4))
563 continue;
564 goto compute_size;
565 } else if (pa->instr_type & OPC_TEST) {
566 if (!(opcode >= pa->sym && opcode < pa->sym + NB_TEST_OPCODES))
567 continue;
568 } else if (pa->instr_type & OPC_B) {
569 if (!(opcode >= pa->sym && opcode <= pa->sym + 3))
570 continue;
571 compute_size:
572 s = (opcode - pa->sym) & 3;
573 } else if (pa->instr_type & OPC_WL) {
574 if (!(opcode >= pa->sym && opcode <= pa->sym + 2))
575 continue;
576 s = opcode - pa->sym + 1;
577 } else {
578 if (pa->sym != opcode)
579 continue;
580 }
581 if (pa->nb_ops != nb_ops)
582 continue;
583 /* now decode and check each operand */
584 for(i = 0; i < nb_ops; i++) {
585 int op1, op2;
586 op1 = pa->op_type[i];
587 op2 = op1 & 0x1f;
588 switch(op2) {
589 case OPT_IM:
590 v = OP_IM8 | OP_IM16 | OP_IM32;
591 break;
592 case OPT_REG:
593 v = OP_REG8 | OP_REG16 | OP_REG32;
594 break;
595 case OPT_REGW:
596 v = OP_REG16 | OP_REG32;
597 break;
598 case OPT_IMW:
599 v = OP_IM16 | OP_IM32;
600 break;
601 default:
602 v = 1 << op2;
603 break;
604 }
605 if (op1 & OPT_EA)
606 v |= OP_EA;
607 op_type[i] = v;
608 if ((ops[i].type & v) == 0)
609 goto next;
610 }
611 /* all is matching ! */
612 break;
613 next: ;
614 }
615 if (pa->sym == 0) {
616 if (opcode >= TOK_ASM_pusha && opcode <= TOK_ASM_emms) {
617 int b;
618 b = op0_codes[opcode - TOK_ASM_pusha];
619 if (opcode == TOK_ASM_o32) {
620 if (s1->seg_size == 32)
621 goto bad_prefix;
622 else
623 data32 = 1;
624 } else if (opcode == TOK_ASM_a32) {
625 if (s1->seg_size == 32)
626 goto bad_prefix;
627 else
628 addr32 = 1;
629 }
630 if (b & 0xff00)
631 g(b >> 8);
632 g(b);
633 return;
634 } else {
635 error("unknown opcode '%s'",
636 get_tok_str(opcode, NULL));
637 }
638 }
639 /* if the size is unknown, then evaluate it (OPC_B or OPC_WL case) */
640 if (s == 3) {
641 for(i = 0; s == 3 && i < nb_ops; i++) {
642 if ((ops[i].type & OP_REG) && !(op_type[i] & (OP_CL | OP_DX)))
643 s = reg_to_size[ops[i].type & OP_REG];
644 }
645 if (s == 3) {
646 if ((opcode == TOK_ASM_push || opcode == TOK_ASM_pop) &&
647 (ops[0].type & (OP_SEG | OP_IM8S | OP_IM32)))
648 s = 2;
649 else
650 error("cannot infer opcode suffix");
651 }
652 }
653
654 a32 = o32 = 0;
655 if (s == 1 || (pa->instr_type & OPC_D16)) {
656 if (s1->seg_size == 32)
657 o32 = 1;
658 } else if (s == 2 && !(pa->instr_type & OPC_D16)) {
659 if (s1->seg_size == 16)
660 o32 = 1;
661 }
662
663 /* generate a16/a32 prefix if needed */
664 if ((a32 == 1) && (addr32 == 0))
665 g(0x67);
666 /* generate o16/o32 prefix if needed */
667 if ((o32 == 1) && (data32 == 0))
668 g(0x66);
669
670 addr32 = data32 = 0;
671
672 /* now generates the operation */
673 if (pa->instr_type & OPC_FWAIT)
674 g(0x9b);
675 if (seg_prefix)
676 g(seg_prefix);
677
678 v = pa->opcode;
679 if (v == 0x69 || v == 0x69) {
680 /* kludge for imul $im, %reg */
681 nb_ops = 3;
682 ops[2] = ops[1];
683 } else if (v == 0xcd && ops[0].e.v == 3 && !ops[0].e.sym) {
684 v--; /* int $3 case */
685 nb_ops = 0;
686 } else if ((v == 0x06 || v == 0x07)) {
687 if (ops[0].reg >= 4) {
688 /* push/pop %fs or %gs */
689 v = 0x0fa0 + (v - 0x06) + ((ops[0].reg - 4) << 3);
690 } else {
691 v += ops[0].reg << 3;
692 }
693 nb_ops = 0;
694 } else if (v <= 0x05) {
695 /* arith case */
696 v += ((opcode - TOK_ASM_addb) >> 2) << 3;
697 } else if ((pa->instr_type & (OPC_FARITH | OPC_MODRM)) == OPC_FARITH) {
698 /* fpu arith case */
699 v += ((opcode - pa->sym) / 6) << 3;
700 }
701 if (pa->instr_type & OPC_REG) {
702 for(i = 0; i < nb_ops; i++) {
703 if (op_type[i] & (OP_REG | OP_ST)) {
704 v += ops[i].reg;
705 break;
706 }
707 }
708 /* mov $im, %reg case */
709 if (pa->opcode == 0xb0 && s >= 1)
710 v += 7;
711 }
712 if (pa->instr_type & OPC_B)
713 v += s >= 1;
714 if (pa->instr_type & OPC_TEST)
715 v += test_bits[opcode - pa->sym];
716 if (pa->instr_type & OPC_SHORTJMP) {
717 Sym *sym;
718 int jmp_disp;
719
720 /* see if we can really generate the jump with a byte offset */
721 sym = ops[0].e.sym;
722 if (!sym)
723 goto no_short_jump;
724 if (sym->r != cur_text_section->sh_num)
725 goto no_short_jump;
726 jmp_disp = ops[0].e.v + sym->jnext - ind - 2;
727 if (jmp_disp == (int8_t)jmp_disp) {
728 /* OK to generate jump */
729 is_short_jmp = 1;
730 ops[0].e.v = jmp_disp;
731 } else {
732 no_short_jump:
733 if (pa->instr_type & OPC_JMP) {
734 /* long jump will be allowed. need to modify the
735 opcode slightly */
736 if (v == 0xeb)
737 v = 0xe9;
738 else
739 v += 0x0f10;
740 } else {
741 error("invalid displacement");
742 }
743 }
744 }
745 op1 = v >> 8;
746 if (op1)
747 g(op1);
748 g(v);
749
750 /* search which operand will used for modrm */
751 modrm_index = 0;
752 if (pa->instr_type & OPC_SHIFT) {
753 reg = (opcode - pa->sym) >> 2;
754 if (reg == 6)
755 reg = 7;
756 } else if (pa->instr_type & OPC_ARITH) {
757 reg = (opcode - pa->sym) >> 2;
758 } else if (pa->instr_type & OPC_FARITH) {
759 reg = (opcode - pa->sym) / 6;
760 } else {
761 reg = (pa->instr_type >> OPC_GROUP_SHIFT) & 7;
762 }
763 if (pa->instr_type & OPC_MODRM) {
764 /* first look for an ea operand */
765 for(i = 0;i < nb_ops; i++) {
766 if (op_type[i] & OP_EA)
767 goto modrm_found;
768 }
769 /* then if not found, a register or indirection (shift instructions) */
770 for(i = 0;i < nb_ops; i++) {
771 if (op_type[i] & (OP_REG | OP_MMX | OP_SSE | OP_INDIR))
772 goto modrm_found;
773 }
774 #ifdef ASM_DEBUG
775 error("bad op table");
776 #endif
777 modrm_found:
778 modrm_index = i;
779 /* if a register is used in another operand then it is
780 used instead of group */
781 for(i = 0;i < nb_ops; i++) {
782 v = op_type[i];
783 if (i != modrm_index &&
784 (v & (OP_REG | OP_MMX | OP_SSE | OP_CR | OP_TR | OP_DB | OP_SEG))) {
785 reg = ops[i].reg;
786 break;
787 }
788 }
789
790 asm_modrm(reg, &ops[modrm_index]);
791 }
792
793 /* emit constants */
794 if (pa->opcode == 0x9a || pa->opcode == 0xea) {
795 /* ljmp or lcall kludge */
796 if (s1->seg_size == 16) {
797 if (o32 == 0)
798 gen_expr16(&ops[1].e);
799 else if (o32 == 1)
800 gen_expr32(&ops[1].e);
801 } else
802 gen_expr32(&ops[1].e);
803 if (ops[0].e.sym) {
804 error_relocate:
805 error("cannot relocate");
806 }
807 gen_le16(ops[0].e.v);
808 } else {
809 for(i = 0;i < nb_ops; i++) {
810 v = op_type[i];
811 if (v & (OP_IM8 | OP_IM16 | OP_IM32 | OP_IM8S | OP_ADDR)) {
812 /* if multiple sizes are given it means we must look
813 at the op size */
814 if (v == (OP_IM8 | OP_IM16 | OP_IM32) ||
815 v == (OP_IM16 | OP_IM32)) {
816 if (s == 0)
817 v = OP_IM8;
818 else if (s == 1)
819 v = OP_IM16;
820 else
821 v = OP_IM32;
822 }
823 if (v & (OP_IM8 | OP_IM8S)) {
824 if (ops[i].e.sym)
825 goto error_relocate;
826 g(ops[i].e.v);
827 } else if (v & OP_IM16) {
828 if (s1->seg_size == 16)
829 gen_expr16(&ops[i].e);
830 else {
831 if (ops[i].e.sym)
832 goto error_relocate;
833 gen_le16(ops[i].e.v);
834 }
835 } else {
836 if (pa->instr_type & (OPC_JMP | OPC_SHORTJMP)) {
837 if (is_short_jmp)
838 g(ops[i].e.v);
839 else {
840 if (s1->seg_size == 16)
841 gen_disp16(&ops[i].e);
842 else
843 gen_disp32(&ops[i].e);
844 }
845 } else {
846 if (s1->seg_size == 16) {
847 if ((o32 == 1) && (v & OP_IM32))
848 gen_expr32(&ops[i].e);
849 else
850 gen_expr16(&ops[i].e);
851 } else if (s1->seg_size == 32) {
852 if (o32 == 1)
853 gen_expr16(&ops[i].e);
854 else
855 gen_expr32(&ops[i].e);
856 }
857 }
858 }
859 } else if (v & (OP_REG16 | OP_REG32)) {
860 if (pa->instr_type & (OPC_JMP | OPC_SHORTJMP)) {
861 /* jmp $r */
862 g(0xE0 + ops[i].reg);
863 }
864 }
865 }
866 }
867 }
868
869 #define NB_SAVED_REGS 3
870 #define NB_ASM_REGS 8
871
872 /* return the constraint priority (we allocate first the lowest
873 numbered constraints) */
874 static inline int constraint_priority(const char *str)
875 {
876 int priority, c, pr;
877
878 /* we take the lowest priority */
879 priority = 0;
880 for(;;) {
881 c = *str;
882 if (c == '\0')
883 break;
884 str++;
885 switch(c) {
886 case 'A':
887 pr = 0;
888 break;
889 case 'a':
890 case 'b':
891 case 'c':
892 case 'd':
893 case 'S':
894 case 'D':
895 pr = 1;
896 break;
897 case 'q':
898 pr = 2;
899 break;
900 case 'r':
901 pr = 3;
902 break;
903 case 'N':
904 case 'M':
905 case 'I':
906 case 'i':
907 case 'm':
908 case 'g':
909 pr = 4;
910 break;
911 default:
912 error("unknown constraint '%c'", c);
913 pr = 0;
914 }
915 if (pr > priority)
916 priority = pr;
917 }
918 return priority;
919 }
920
921 static const char *skip_constraint_modifiers(const char *p)
922 {
923 while (*p == '=' || *p == '&' || *p == '+' || *p == '%')
924 p++;
925 return p;
926 }
927
928 #define REG_OUT_MASK 0x01
929 #define REG_IN_MASK 0x02
930
931 #define is_reg_allocated(reg) (regs_allocated[reg] & reg_mask)
932
933 static void asm_compute_constraints(ASMOperand *operands,
934 int nb_operands, int nb_outputs,
935 const uint8_t *clobber_regs,
936 int *pout_reg)
937 {
938 ASMOperand *op;
939 int sorted_op[MAX_ASM_OPERANDS];
940 int i, j, k, p1, p2, tmp, reg, c, reg_mask;
941 const char *str;
942 uint8_t regs_allocated[NB_ASM_REGS];
943
944 /* init fields */
945 for(i=0;i<nb_operands;i++) {
946 op = &operands[i];
947 op->input_index = -1;
948 op->ref_index = -1;
949 op->reg = -1;
950 op->is_memory = 0;
951 op->is_rw = 0;
952 }
953 /* compute constraint priority and evaluate references to output
954 constraints if input constraints */
955 for(i=0;i<nb_operands;i++) {
956 op = &operands[i];
957 str = op->constraint;
958 str = skip_constraint_modifiers(str);
959 if (isnum(*str) || *str == '[') {
960 /* this is a reference to another constraint */
961 k = find_constraint(operands, nb_operands, str, NULL);
962 if ((unsigned)k >= i || i < nb_outputs)
963 error("invalid reference in constraint %d ('%s')",
964 i, str);
965 op->ref_index = k;
966 if (operands[k].input_index >= 0)
967 error("cannot reference twice the same operand");
968 operands[k].input_index = i;
969 op->priority = 5;
970 } else {
971 op->priority = constraint_priority(str);
972 }
973 }
974
975 /* sort operands according to their priority */
976 for(i=0;i<nb_operands;i++)
977 sorted_op[i] = i;
978 for(i=0;i<nb_operands - 1;i++) {
979 for(j=i+1;j<nb_operands;j++) {
980 p1 = operands[sorted_op[i]].priority;
981 p2 = operands[sorted_op[j]].priority;
982 if (p2 < p1) {
983 tmp = sorted_op[i];
984 sorted_op[i] = sorted_op[j];
985 sorted_op[j] = tmp;
986 }
987 }
988 }
989
990 for(i = 0;i < NB_ASM_REGS; i++) {
991 if (clobber_regs[i])
992 regs_allocated[i] = REG_IN_MASK | REG_OUT_MASK;
993 else
994 regs_allocated[i] = 0;
995 }
996 /* esp cannot be used */
997 regs_allocated[4] = REG_IN_MASK | REG_OUT_MASK;
998 /* ebp cannot be used yet */
999 regs_allocated[5] = REG_IN_MASK | REG_OUT_MASK;
1000
1001 /* allocate registers and generate corresponding asm moves */
1002 for(i=0;i<nb_operands;i++) {
1003 j = sorted_op[i];
1004 op = &operands[j];
1005 str = op->constraint;
1006 /* no need to allocate references */
1007 if (op->ref_index >= 0)
1008 continue;
1009 /* select if register is used for output, input or both */
1010 if (op->input_index >= 0) {
1011 reg_mask = REG_IN_MASK | REG_OUT_MASK;
1012 } else if (j < nb_outputs) {
1013 reg_mask = REG_OUT_MASK;
1014 } else {
1015 reg_mask = REG_IN_MASK;
1016 }
1017 try_next:
1018 c = *str++;
1019 switch(c) {
1020 case '=':
1021 goto try_next;
1022 case '+':
1023 op->is_rw = 1;
1024 /* FALL THRU */
1025 case '&':
1026 if (j >= nb_outputs)
1027 error("'%c' modifier can only be applied to outputs", c);
1028 reg_mask = REG_IN_MASK | REG_OUT_MASK;
1029 goto try_next;
1030 case 'A':
1031 /* allocate both eax and edx */
1032 if (is_reg_allocated(TREG_EAX) ||
1033 is_reg_allocated(TREG_EDX))
1034 goto try_next;
1035 op->is_llong = 1;
1036 op->reg = TREG_EAX;
1037 regs_allocated[TREG_EAX] |= reg_mask;
1038 regs_allocated[TREG_EDX] |= reg_mask;
1039 break;
1040 case 'a':
1041 reg = TREG_EAX;
1042 goto alloc_reg;
1043 case 'b':
1044 reg = 3;
1045 goto alloc_reg;
1046 case 'c':
1047 reg = TREG_ECX;
1048 goto alloc_reg;
1049 case 'd':
1050 reg = TREG_EDX;
1051 goto alloc_reg;
1052 case 'S':
1053 reg = 6;
1054 goto alloc_reg;
1055 case 'D':
1056 reg = 7;
1057 alloc_reg:
1058 if (is_reg_allocated(reg))
1059 goto try_next;
1060 goto reg_found;
1061 case 'q':
1062 /* eax, ebx, ecx or edx */
1063 for(reg = 0; reg < 4; reg++) {
1064 if (!is_reg_allocated(reg))
1065 goto reg_found;
1066 }
1067 goto try_next;
1068 case 'r':
1069 /* any general register */
1070 for(reg = 0; reg < 8; reg++) {
1071 if (!is_reg_allocated(reg))
1072 goto reg_found;
1073 }
1074 goto try_next;
1075 reg_found:
1076 /* now we can reload in the register */
1077 op->is_llong = 0;
1078 op->reg = reg;
1079 regs_allocated[reg] |= reg_mask;
1080 break;
1081 case 'i':
1082 if (!((op->vt->r & (VT_VALMASK | VT_LVAL)) == VT_CONST))
1083 goto try_next;
1084 break;
1085 case 'I':
1086 case 'N':
1087 case 'M':
1088 if (!((op->vt->r & (VT_VALMASK | VT_LVAL | VT_SYM)) == VT_CONST))
1089 goto try_next;
1090 break;
1091 case 'm':
1092 case 'g':
1093 /* nothing special to do because the operand is already in
1094 memory, except if the pointer itself is stored in a
1095 memory variable (VT_LLOCAL case) */
1096 /* XXX: fix constant case */
1097 /* if it is a reference to a memory zone, it must lie
1098 in a register, so we reserve the register in the
1099 input registers and a load will be generated
1100 later */
1101 if (j < nb_outputs || c == 'm') {
1102 if ((op->vt->r & VT_VALMASK) == VT_LLOCAL) {
1103 /* any general register */
1104 for(reg = 0; reg < 8; reg++) {
1105 if (!(regs_allocated[reg] & REG_IN_MASK))
1106 goto reg_found1;
1107 }
1108 goto try_next;
1109 reg_found1:
1110 /* now we can reload in the register */
1111 regs_allocated[reg] |= REG_IN_MASK;
1112 op->reg = reg;
1113 op->is_memory = 1;
1114 }
1115 }
1116 break;
1117 default:
1118 error("asm constraint %d ('%s') could not be satisfied",
1119 j, op->constraint);
1120 break;
1121 }
1122 /* if a reference is present for that operand, we assign it too */
1123 if (op->input_index >= 0) {
1124 operands[op->input_index].reg = op->reg;
1125 operands[op->input_index].is_llong = op->is_llong;
1126 }
1127 }
1128
1129 /* compute out_reg. It is used to store outputs registers to memory
1130 locations references by pointers (VT_LLOCAL case) */
1131 *pout_reg = -1;
1132 for(i=0;i<nb_operands;i++) {
1133 op = &operands[i];
1134 if (op->reg >= 0 &&
1135 (op->vt->r & VT_VALMASK) == VT_LLOCAL &&
1136 !op->is_memory) {
1137 for(reg = 0; reg < 8; reg++) {
1138 if (!(regs_allocated[reg] & REG_OUT_MASK))
1139 goto reg_found2;
1140 }
1141 error("could not find free output register for reloading");
1142 reg_found2:
1143 *pout_reg = reg;
1144 break;
1145 }
1146 }
1147
1148 /* print sorted constraints */
1149 #ifdef ASM_DEBUG
1150 for(i=0;i<nb_operands;i++) {
1151 j = sorted_op[i];
1152 op = &operands[j];
1153 printf("%%%d [%s]: \"%s\" r=0x%04x reg=%d\n",
1154 j,
1155 op->id ? get_tok_str(op->id, NULL) : "",
1156 op->constraint,
1157 op->vt->r,
1158 op->reg);
1159 }
1160 if (*pout_reg >= 0)
1161 printf("out_reg=%d\n", *pout_reg);
1162 #endif
1163 }
1164
1165 static void subst_asm_operand(CString *add_str,
1166 SValue *sv, int modifier)
1167 {
1168 int r, reg, size, val;
1169 char buf[64];
1170
1171 r = sv->r;
1172 if ((r & VT_VALMASK) == VT_CONST) {
1173 if (!(r & VT_LVAL) && modifier != 'c' && modifier != 'n')
1174 cstr_ccat(add_str, '$');
1175 if (r & VT_SYM) {
1176 cstr_cat(add_str, get_tok_str(sv->sym->v, NULL));
1177 if (sv->c.i != 0) {
1178 cstr_ccat(add_str, '+');
1179 } else {
1180 return;
1181 }
1182 }
1183 val = sv->c.i;
1184 if (modifier == 'n')
1185 val = -val;
1186 snprintf(buf, sizeof(buf), "%d", sv->c.i);
1187 cstr_cat(add_str, buf);
1188 } else if ((r & VT_VALMASK) == VT_LOCAL) {
1189 snprintf(buf, sizeof(buf), "%d(%%ebp)", sv->c.i);
1190 cstr_cat(add_str, buf);
1191 } else if (r & VT_LVAL) {
1192 reg = r & VT_VALMASK;
1193 if (reg >= VT_CONST)
1194 error("internal compiler error");
1195 snprintf(buf, sizeof(buf), "(%%%s)",
1196 get_tok_str(TOK_ASM_eax + reg, NULL));
1197 cstr_cat(add_str, buf);
1198 } else {
1199 /* register case */
1200 reg = r & VT_VALMASK;
1201 if (reg >= VT_CONST)
1202 error("internal compiler error");
1203
1204 /* choose register operand size */
1205 if ((sv->type.t & VT_BTYPE) == VT_BYTE)
1206 size = 1;
1207 else if ((sv->type.t & VT_BTYPE) == VT_SHORT)
1208 size = 2;
1209 else
1210 size = 4;
1211 if (size == 1 && reg >= 4)
1212 size = 4;
1213
1214 if (modifier == 'b') {
1215 if (reg >= 4)
1216 error("cannot use byte register");
1217 size = 1;
1218 } else if (modifier == 'h') {
1219 if (reg >= 4)
1220 error("cannot use byte register");
1221 size = -1;
1222 } else if (modifier == 'w') {
1223 size = 2;
1224 }
1225
1226 switch(size) {
1227 case -1:
1228 reg = TOK_ASM_ah + reg;
1229 break;
1230 case 1:
1231 reg = TOK_ASM_al + reg;
1232 break;
1233 case 2:
1234 reg = TOK_ASM_ax + reg;
1235 break;
1236 default:
1237 reg = TOK_ASM_eax + reg;
1238 break;
1239 }
1240 snprintf(buf, sizeof(buf), "%%%s", get_tok_str(reg, NULL));
1241 cstr_cat(add_str, buf);
1242 }
1243 }
1244
1245 /* generate prolog and epilog code for asm statment */
1246 static void asm_gen_code(ASMOperand *operands, int nb_operands,
1247 int nb_outputs, int is_output,
1248 uint8_t *clobber_regs,
1249 int out_reg)
1250 {
1251 uint8_t regs_allocated[NB_ASM_REGS];
1252 ASMOperand *op;
1253 int i, reg;
1254 static uint8_t reg_saved[NB_SAVED_REGS] = { 3, 6, 7 };
1255
1256 /* mark all used registers */
1257 memcpy(regs_allocated, clobber_regs, sizeof(regs_allocated));
1258 for(i = 0; i < nb_operands;i++) {
1259 op = &operands[i];
1260 if (op->reg >= 0)
1261 regs_allocated[op->reg] = 1;
1262 }
1263 if (!is_output) {
1264 /* generate reg save code */
1265 for(i = 0; i < NB_SAVED_REGS; i++) {
1266 reg = reg_saved[i];
1267 if (regs_allocated[reg]) {
1268 if (tcc_state->seg_size == 16)
1269 g(0x66);
1270 g(0x50 + reg);
1271 }
1272 }
1273
1274 /* generate load code */
1275 for(i = 0; i < nb_operands; i++) {
1276 op = &operands[i];
1277 if (op->reg >= 0) {
1278 if ((op->vt->r & VT_VALMASK) == VT_LLOCAL &&
1279 op->is_memory) {
1280 /* memory reference case (for both input and
1281 output cases) */
1282 SValue sv;
1283 sv = *op->vt;
1284 sv.r = (sv.r & ~VT_VALMASK) | VT_LOCAL;
1285 load(op->reg, &sv);
1286 } else if (i >= nb_outputs || op->is_rw) {
1287 /* load value in register */
1288 load(op->reg, op->vt);
1289 if (op->is_llong) {
1290 SValue sv;
1291 sv = *op->vt;
1292 sv.c.ul += 4;
1293 load(TREG_EDX, &sv);
1294 }
1295 }
1296 }
1297 }
1298 } else {
1299 /* generate save code */
1300 for(i = 0 ; i < nb_outputs; i++) {
1301 op = &operands[i];
1302 if (op->reg >= 0) {
1303 if ((op->vt->r & VT_VALMASK) == VT_LLOCAL) {
1304 if (!op->is_memory) {
1305 SValue sv;
1306 sv = *op->vt;
1307 sv.r = (sv.r & ~VT_VALMASK) | VT_LOCAL;
1308 load(out_reg, &sv);
1309
1310 sv.r = (sv.r & ~VT_VALMASK) | out_reg;
1311 store(op->reg, &sv);
1312 }
1313 } else {
1314 store(op->reg, op->vt);
1315 if (op->is_llong) {
1316 SValue sv;
1317 sv = *op->vt;
1318 sv.c.ul += 4;
1319 store(TREG_EDX, &sv);
1320 }
1321 }
1322 }
1323 }
1324 /* generate reg restore code */
1325 for(i = NB_SAVED_REGS - 1; i >= 0; i--) {
1326 reg = reg_saved[i];
1327 if (regs_allocated[reg]) {
1328 if (tcc_state->seg_size == 16)
1329 g(0x66);
1330 g(0x58 + reg);
1331 }
1332 }
1333 }
1334 }
1335
1336 static void asm_clobber(uint8_t *clobber_regs, const char *str)
1337 {
1338 int reg;
1339 TokenSym *ts;
1340
1341 if (!strcmp(str, "memory") ||
1342 !strcmp(str, "cc"))
1343 return;
1344 ts = tok_alloc(str, strlen(str));
1345 reg = ts->tok;
1346 if (reg >= TOK_ASM_eax && reg <= TOK_ASM_edi) {
1347 reg -= TOK_ASM_eax;
1348 } else if (reg >= TOK_ASM_ax && reg <= TOK_ASM_di) {
1349 reg -= TOK_ASM_ax;
1350 } else {
1351 error("invalid clobber register '%s'", str);
1352 }
1353 clobber_regs[reg] = 1;
1354 }
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