add emc emulation
authoryajin <yajin@vm-kernel.org>
Sun, 11 Jan 2009 01:00:15 +0000 (11 09:00 +0800)
committeryajin <yajin@vm-kernel.org>
Sun, 11 Jan 2009 01:00:15 +0000 (11 09:00 +0800)
reformat the source code

hw/mips_jz.c
hw/mips_jz.h
hw/mips_jz_clk.c
hw/mips_pavo.c

index a86481f..07c8c4c 100755 (executable)
@@ -71,8 +71,12 @@ static void debug_out(uint32_t flag, const char *format, ...)
     }
 }
 #else
-static void debug_init(void) { }
-static void debug_out(uint32_t flag, const char *format, ...){}
+static void debug_init(void)
+{
+}
+static void debug_out(uint32_t flag, const char *format, ...)
+{
+}
 #endif
 
 static uint32_t jz4740_badwidth_read8(void *opaque, target_phys_addr_t addr)
@@ -85,7 +89,7 @@ static uint32_t jz4740_badwidth_read8(void *opaque, target_phys_addr_t addr)
 }
 
 static void jz4740_badwidth_write8(void *opaque, target_phys_addr_t addr,
-                            uint32_t value)
+                                   uint32_t value)
 {
     uint8_t val8 = value;
 
@@ -102,7 +106,7 @@ static uint32_t jz4740_badwidth_read16(void *opaque, target_phys_addr_t addr)
 }
 
 static void jz4740_badwidth_write16(void *opaque, target_phys_addr_t addr,
-                             uint32_t value)
+                                    uint32_t value)
 {
     uint16_t val16 = value;
 
@@ -120,7 +124,7 @@ static uint32_t jz4740_badwidth_read32(void *opaque, target_phys_addr_t addr)
 }
 
 static void jz4740_badwidth_write32(void *opaque, target_phys_addr_t addr,
-                             uint32_t value)
+                                    uint32_t value)
 {
     JZ4740_32B_REG(addr);
     cpu_physical_memory_write(addr, (void *) &value, 4);
@@ -143,7 +147,7 @@ struct jz4740_cpm_s
     uint32_t ssicdr;
 };
 
-static void  jz4740_dump_clocks(jz_clk parent)
+static void jz4740_dump_clocks(jz_clk parent)
 {
     jz_clk i = parent;
 
@@ -461,7 +465,7 @@ static void jz4740_intc_write(void *opaque, target_phys_addr_t addr,
         JZ4740_RO_REG(addr);
         break;
     case 0x4:
-        s->icmr = value ;
+        s->icmr = value;
         break;
     case 0x8:
         s->icmr |= value;
@@ -471,8 +475,8 @@ static void jz4740_intc_write(void *opaque, target_phys_addr_t addr,
         break;
     default:
         cpu_abort(s->soc->env,
-                  "jz4740_intc_write undefined addr " JZ_FMT_plx "  value %x \n",
-                  addr, value);
+                  "jz4740_intc_write undefined addr " JZ_FMT_plx
+                  "  value %x \n", addr, value);
     }
 }
 
@@ -498,20 +502,20 @@ static void jz4740_intc_reset(struct jz4740_intc_s *s)
 
 static void jz4740_set_irq(void *opaque, int irq, int level)
 {
-       struct jz4740_intc_s *s = (struct jz4740_intc_s *) opaque;
-       uint32_t irq_mask = 1<<irq;
-       
-       s->icsr |= irq_mask;
-       s->icpr |= irq_mask;
-       s->icpr &= ~s->icmr;
-       
-       if ((~s->icmr)&irq_mask)
-               qemu_set_irq(s->parent_irq,1);
-       else
-               qemu_set_irq(s->parent_irq,0);
+    struct jz4740_intc_s *s = (struct jz4740_intc_s *) opaque;
+    uint32_t irq_mask = 1 << irq;
+
+    s->icsr |= irq_mask;
+    s->icpr |= irq_mask;
+    s->icpr &= ~s->icmr;
+
+    if (((~s->icmr) & irq_mask) && (level))
+        qemu_set_irq(s->parent_irq, 1);
+    else
+        qemu_set_irq(s->parent_irq, 0);
 }
 
-static qemu_irq *jz4740_intc_init(struct jz_state_s  *soc,qemu_irq parent_irq)
+static qemu_irq *jz4740_intc_init(struct jz_state_s *soc, qemu_irq parent_irq)
 {
     int iomemtype;
     struct jz4740_intc_s *s = (struct jz4740_intc_s *) qemu_mallocz(sizeof(*s));
@@ -534,58 +538,441 @@ struct jz4740_emc_s
     target_phys_addr_t base;
     struct jz_state_s *soc;
 
-    uint32_t smcr1;                    /*0x13010014*/
-    uint32_t smcr2;                    /*0x13010018*/
-    uint32_t smcr3;                    /*0x1301001c*/
-    uint32_t smcr4;                    /*0x13010020*/
-    uint32_t sacr1;                     /*0x13010034*/
-    uint32_t sacr2;                    /*0x13010038*/
-    uint32_t sacr3;                    /*0x1301003c*/
-    uint32_t sacr4;                    /*0x13010040*/
-
-    uint32_t nfcsr;                    /*0x13010050*/
-    uint32_t nfeccr;                  /*0x13010100*/
-    uint32_t nfecc;                    /*0x13010104*/
-    uint32_t nfpar0;                  /*0x13010108*/
-    uint32_t nfpar1;                  /*0x1301010c*/
-    uint32_t nfpar2;                  /*0x13010110*/
-    uint32_t nfints;                    /*0x13010114*/
-    uint32_t nfinte;                    /*0x13010118*/
-    uint32_t nferr0;                    /*0x1301011c*/
-    uint32_t nferr1;                    /*0x13010120*/
-    uint32_t nferr2;                    /*0x13010124*/
-    uint32_t nferr3;                    /*0x13010128*/
-
-    uint32_t dmcr;                     /*0x13010080*/
-    uint32_t rtcsr;                      /*0x13010084*/                 
-    uint32_t rtcnt;                      /*0x13010088*/
-    uint32_t rtcor;                     /*0x1301008c*/
-    uint32_t dmar;                     /*0x13010090*/
-    uint32_t sdmr;                     /*0x1301a000*/
-    
+    uint32_t smcr1;             /*0x13010014 */
+    uint32_t smcr2;             /*0x13010018 */
+    uint32_t smcr3;             /*0x1301001c */
+    uint32_t smcr4;             /*0x13010020 */
+    uint32_t sacr1;             /*0x13010034 */
+    uint32_t sacr2;             /*0x13010038 */
+    uint32_t sacr3;             /*0x1301003c */
+    uint32_t sacr4;             /*0x13010040 */
+
+    uint32_t nfcsr;             /*0x13010050 */
+    uint32_t nfeccr;            /*0x13010100 */
+    uint32_t nfecc;             /*0x13010104 */
+    uint32_t nfpar0;            /*0x13010108 */
+    uint32_t nfpar1;            /*0x1301010c */
+    uint32_t nfpar2;            /*0x13010110 */
+    uint32_t nfints;            /*0x13010114 */
+    uint32_t nfinte;            /*0x13010118 */
+    uint32_t nferr0;            /*0x1301011c */
+    uint32_t nferr1;            /*0x13010120 */
+    uint32_t nferr2;            /*0x13010124 */
+    uint32_t nferr3;            /*0x13010128 */
+
+    uint32_t dmcr;              /*0x13010080 */
+    uint32_t rtcsr;             /*0x13010084 */
+    uint32_t rtcnt;             /*0x13010088 */
+    uint32_t rtcor;             /*0x1301008c */
+    uint32_t dmar;              /*0x13010090 */
+    uint32_t sdmr;              /*0x1301a000 */
+
+};
+
+
+static void jz4740_emc_reset(struct jz4740_emc_s *s)
+{
+    s->smcr1 = 0xfff7700;
+    s->smcr2 = 0xfff7700;
+    s->smcr3 = 0xfff7700;
+    s->smcr4 = 0xfff7700;
+    s->sacr1 = 0x18fc;
+    s->sacr2 = 0x16fe;
+    s->sacr3 = 0x14fe;
+    s->sacr4 = 0xcfc;
+
+    s->nfcsr = 0x0;
+    s->nfeccr = 0x0;
+    s->nfecc = 0x0;
+    s->nfpar0 = 0x0;
+    s->nfpar1 = 0x0;
+    s->nfpar2 = 0x0;
+    s->nfints = 0x0;
+    s->nfinte = 0x0;
+    s->nferr0 = 0x0;
+    s->nferr1 = 0x0;
+    s->nferr2 = 0x0;
+    s->nferr3 = 0x0;
+
+    s->dmcr = 0x0;
+    s->rtcsr = 0x0;
+    s->rtcnt = 0x0;
+    s->rtcor = 0x0;
+    s->dmar = 0x20f8;
+    s->sdmr = 0x0;
+
+}
+
+static uint32_t jz4740_emc_read8(void *opaque, target_phys_addr_t addr)
+{
+    struct jz4740_emc_s *s = (struct jz4740_emc_s *) opaque;
+    int offset = addr - s->base;
+    switch (offset)
+    {
+    case 0x108:
+    case 0x109:
+    case 0x10a:
+    case 0x10b:
+        return (s->nfpar0 >> ((offset - 0x108) * 8)) & 0xff;
+    case 0x10c:
+    case 0x10d:
+    case 0x10e:
+    case 0x10f:
+        return (s->nfpar1 >> ((offset - 0x10c) * 8)) & 0xff;
+    case 0x110:
+    case 0x111:
+    case 0x112:
+    case 0x113:
+        return (s->nfpar2 >> ((offset - 0x110) * 8)) & 0xff;
+    case 0xa000:
+    case 0xa001:
+    case 0xa002:
+    case 0xa003:
+        return (s->sdmr >> ((offset - 0xa000) * 8)) & 0xff;
+    default:
+        cpu_abort(s->soc->env,
+                  "jz4740_emc_read8 undefined addr " JZ_FMT_plx " \n", addr);
+
+
+    }
+    return (0);
+}
+
+static uint32_t jz4740_emc_read16(void *opaque, target_phys_addr_t addr)
+{
+    struct jz4740_emc_s *s = (struct jz4740_emc_s *) opaque;
+    int offset = addr - s->base;
+    switch (offset)
+    {
+    case 0x108:
+    case 0x10a:
+        return (s->nfpar0 >> ((offset - 0x108) * 8)) & 0xffff;
+    case 0x10c:
+    case 0x10e:
+        return (s->nfpar1 >> ((offset - 0x10c) * 8)) & 0xffff;
+    case 0x110:
+    case 0x112:
+        return (s->nfpar2 >> ((offset - 0x110) * 8)) & 0xffff;
+    case 0x11c:
+    case 0x11e:
+        return (s->nferr0 >> ((offset - 0x11c) * 8)) & 0xffff;
+    case 0x120:
+    case 0x122:
+        return (s->nferr1 >> ((offset - 0x120) * 8)) & 0xffff;
+    case 0x124:
+    case 0x126:
+        return (s->nferr2 >> ((offset - 0x124) * 8)) & 0xffff;
+    case 0x128:
+    case 0x12a:
+        return (s->nferr3 >> ((offset - 0x128) * 8)) & 0xffff;
+    default:
+        cpu_abort(s->soc->env,
+                  "jz4740_emc_read16 undefined addr " JZ_FMT_plx " \n", addr);
+    }
+    return (0);
+}
+
+static uint32_t jz4740_emc_read32(void *opaque, target_phys_addr_t addr)
+{
+    struct jz4740_emc_s *s = (struct jz4740_emc_s *) opaque;
+    int offset = addr - s->base;
+    switch (offset)
+    {
+    case 0x14:
+        return s->smcr1;
+    case 0x18:
+        return s->smcr2;
+    case 0x1c:
+        return s->smcr3;
+    case 0x20:
+        return s->smcr4;
+    case 0x34:
+        return s->sacr1;
+    case 0x38:
+        return s->sacr2;
+    case 0x3c:
+        return s->sacr3;
+    case 0x40:
+        return s->sacr4;
+    case 0x50:
+        return s->nfcsr;
+    case 0x100:
+        return s->nfeccr;
+    case 0x104:
+        return s->nfecc;
+    case 0x108:
+        return s->nfpar0;
+    case 0x10c:
+        return s->nfpar1;
+    case 0x110:
+        return s->nfpar2;
+    case 0x114:
+        return s->nfints;
+    case 0x118:
+        return s->nfinte;
+    case 0x11c:
+        return s->nferr0;
+    case 0x120:
+        return s->nferr1;
+    case 0x124:
+        return s->nferr2;
+    case 0x128:
+        return s->nferr3;
+    case 0x80:
+        return s->dmcr;
+    case 0x90:
+        return s->dmar;
+    default:
+        cpu_abort(s->soc->env,
+                  "jz4740_emc_read32 undefined addr " JZ_FMT_plx " \n", addr);
+    }
+    return (0);
+}
+
+static void jz4740_emc_write8(void *opaque, target_phys_addr_t addr,
+                              uint32_t value)
+{
+    struct jz4740_emc_s *s = (struct jz4740_emc_s *) opaque;
+    int offset = addr - s->base;
+
+    switch (offset)
+    {
+    case 0x108:
+    case 0x109:
+    case 0x10a:
+    case 0x10b:
+        s->nfpar0 |= (value & 0xff) << ((offset - 0x108) * 8);
+        break;
+    case 0x10c:
+    case 0x10d:
+    case 0x10e:
+    case 0x10f:
+        s->nfpar1 |= (value & 0xff) << ((offset - 0x10c) * 8);
+        break;
+    case 0x110:
+    case 0x111:
+    case 0x112:
+    case 0x113:
+        s->nfpar2 |= (value & 0xff) << ((offset - 0x110) * 8);
+        break;
+    case 0xa000:
+    case 0xa001:
+    case 0xa002:
+    case 0xa003:
+        s->sdmr |= (value & 0xff) << ((offset - 0x110) * 8);
+        break;
+    default:
+        cpu_abort(s->soc->env,
+                  "jz4740_emc_write8 undefined addr " JZ_FMT_plx
+                  "  value %x \n", addr, value);
+    }
+}
+static void jz4740_emc_write16(void *opaque, target_phys_addr_t addr,
+                               uint32_t value)
+{
+    struct jz4740_emc_s *s = (struct jz4740_emc_s *) opaque;
+    int offset = addr - s->base;
+
+    switch (offset)
+    {
+    case 0x108:
+    case 0x10a:
+        s->nfpar0 |= (value & 0xffff) << ((offset - 0x108) * 8);
+        break;
+    case 0x10c:
+    case 0x10e:
+        s->nfpar1 |= (value & 0xffff) << ((offset - 0x10c) * 8);
+        break;
+    case 0x110:
+    case 0x112:
+        s->nfpar2 |= (value & 0xffff) << ((offset - 0x110) * 8);
+        break;
+    case 0x84:
+    case 0x86:
+        s->rtcsr |= (value & 0xffff) << ((offset - 0x84) * 8);
+        break;
+    case 0x88:
+    case 0x8a:
+        s->rtcnt |= (value & 0xffff) << ((offset - 0x88) * 8);
+        break;
+    case 0x8c:
+        s->rtcor |= (value & 0xffff) << ((offset - 0x8c) * 8);
+        break;
+    default:
+        cpu_abort(s->soc->env,
+                  "jz4740_emc_write16 undefined addr " JZ_FMT_plx
+                  "  value %x \n", addr, value);
+    }
+}
+
+static void jz4740_emc_upate_interrupt(struct jz4740_emc_s *s)
+{
+    qemu_set_irq(s->irq, s->nfints & s->nfinte);
+}
+
+static void jz4740_emc_write32(void *opaque, target_phys_addr_t addr,
+                               uint32_t value)
+{
+    struct jz4740_emc_s *s = (struct jz4740_emc_s *) opaque;
+    int offset = addr - s->base;
+
+    switch (offset)
+    {
+    case 0x104:
+    case 0x11c:
+    case 0x120:
+    case 0x124:
+    case 0x128:
+        JZ4740_RO_REG(addr);
+        break;
+    case 0x14:
+        s->smcr1 = value & 0xfff77cf;
+        break;
+    case 0x18:
+        s->smcr2 = value & 0xfff77cf;
+        break;
+    case 0x1c:
+        s->smcr3 = value & 0xfff77cf;
+        break;
+    case 0x20:
+        s->smcr4 = value & 0xfff77cf;
+        break;
+    case 0x34:
+        s->sacr1 = value & 0xffff;
+        break;
+    case 0x38:
+        s->sacr2 = value & 0xffff;
+        break;
+    case 0x3c:
+        s->sacr3 = value & 0xffff;
+        break;
+    case 0x40:
+        s->sacr4 = value & 0xffff;
+        break;
+    case 0x50:
+        s->nfcsr = value & 0xffff;
+        break;
+    case 0x100:
+        s->nfeccr = value & 0x1f;
+        if (s->nfeccr & 0x2)
+        {
+            s->nfecc = 0x0;
+            s->nfpar0 = 0x0;
+            s->nfpar1 = 0x0;
+            s->nfpar2 = 0x0;
+            s->nfints = 0x0;
+            s->nfinte = 0x0;
+            s->nferr0 = 0x0;
+            s->nferr1 = 0x0;
+            s->nferr2 = 0x0;
+            s->nferr3 = 0x0;
+        }
+         /*RS*/
+            /*TODO: Real RS error correction */
+            if (s->nfeccr & 0x4)
+        {
+            if ((s->nfeccr & 0x10) && (!(s->nfeccr & 0x8)))
+            {
+                /*decode */
+                s->nfints = 0x8;
+                s->nferr0 = 0x0;
+                s->nferr1 = 0x0;
+                s->nferr2 = 0x0;
+            }
+            if (s->nfeccr & 0x8)
+            {
+                /*encoding */
+                s->nfints = 0x4;
+                s->nfpar0 = 0xffffffff; /*fake value. for debug */
+                s->nfpar1 = 0xffffffff; /*fake value */
+                s->nfpar2 = 0xff;       /*fake value */
+            }
+        }
+        else
+        {
+            s->nfecc = 0xffffff;
+        }
+        jz4740_emc_upate_interrupt(s);
+        break;
+    case 0x108:
+        s->nfpar0 = value;
+        break;
+    case 0x10c:
+        s->nfpar1 = value;
+        break;
+    case 0x110:
+        s->nfpar2 = value & 0xff;
+        break;
+    case 0x114:
+        s->nfints = value & 0x1fffffff;
+        jz4740_emc_upate_interrupt(s);
+        break;
+    case 0x118:
+        s->nfinte = value & 0x1f;
+        jz4740_emc_upate_interrupt(s);
+        break;
+    case 0x080:
+        s->dmcr = value & 0x9fbeff7f;
+        break;
+    case 0x90:
+        s->dmar = value & 0xffff;
+        break;
+    default:
+        cpu_abort(s->soc->env,
+                  "jz4740_emc_write32 undefined addr " JZ_FMT_plx
+                  "  value %x \n", addr, value);
+
+    }
+
+}
+
+static CPUReadMemoryFunc *jz4740_emc_readfn[] = {
+    jz4740_emc_read8,
+    jz4740_emc_read16,
+    jz4740_emc_read32,
+};
+
+static CPUWriteMemoryFunc *jz4740_emc_writefn[] = {
+    jz4740_emc_write8,
+    jz4740_emc_write16,
+    jz4740_emc_write32,
 };
 
-static void jz4740_emc_init(struct jz_state_s  *soc,qemu_irq irq)
+
+static struct jz4740_emc_s *jz4740_emc_init(struct jz_state_s *soc, qemu_irq irq)
 {
-       
+    int iomemtype;
+    struct jz4740_emc_s *s = (struct jz4740_emc_s *) qemu_mallocz(sizeof(*s));
+    s->base = JZ4740_PHYS_BASE(JZ4740_EMC_BASE);
+    s->soc = soc;
+    s->irq = irq;
+
+    jz4740_emc_reset(s);
+
+    iomemtype =
+        cpu_register_io_memory(0, jz4740_emc_readfn, jz4740_emc_writefn, s);
+    cpu_register_physical_memory(s->base, 0x00010000, iomemtype);
+    return s;
+
 }
 
+
 static void jz4740_cpu_reset(void *opaque)
 {
     fprintf(stderr, "%s: UNIMPLEMENTED!", __FUNCTION__);
 }
 
 struct jz_state_s *jz4740_init(unsigned long sdram_size,
-                                                              uint32_t osc_extal_freq)
+                               uint32_t osc_extal_freq)
 {
     struct jz_state_s *s = (struct jz_state_s *)
         qemu_mallocz(sizeof(struct jz_state_s));
     ram_addr_t sram_base, sdram_base;
-    qemu_irq * intc;
+    qemu_irq *intc;
 
     s->mpu_model = jz4740;
     s->env = cpu_init("jz4740");
-    
+
     if (!s->env)
     {
         fprintf(stderr, "Unable to find CPU definition\n");
@@ -601,7 +988,7 @@ struct jz_state_s *jz4740_init(unsigned long sdram_size,
     /* Clocks */
     jz_clk_init(s, osc_extal_freq);
 
-       /*map sram to 0x80000000 and sdram to 0x80004000 */
+    /*map sram to 0x80000000 and sdram to 0x80004000 */
     sram_base = qemu_ram_alloc(s->sram_size);
     cpu_register_physical_memory(JZ4740_SRAM_BASE, s->sram_size,
                                  (sram_base | IO_MEM_RAM));
@@ -613,13 +1000,13 @@ struct jz_state_s *jz4740_init(unsigned long sdram_size,
     cpu_mips_irq_init_cpu(s->env);
     cpu_mips_clock_init(s->env);
 
-    
+
     /* Clocks */
     jz_clk_init(s, osc_extal_freq);
 
-    intc = jz4740_intc_init(s,s->env->irq[2]);
+    intc = jz4740_intc_init(s, s->env->irq[2]);
     s->cpm = jz4740_cpm_init(s);
+    s->emc = jz4740_emc_init(s,intc[2]);
 
     return s;
 }
-
index ab2a6fd..4f0275e 100755 (executable)
@@ -194,6 +194,7 @@ struct jz_state_s {
        jz_clk clks;
 
        struct jz4740_cpm_s *cpm;
+       struct jz4740_emc_s *emc;
 
        
 };
index ac6e673..c5ac296 100755 (executable)
@@ -19,7 +19,7 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
+
 #include "hw.h"
 #include "mips_jz.h"
 
 
 
 static struct clk osc_extal = {
-    .name      = "osc_extal_12M",
-    .rate      = 12000000,
-    .flags     = ALWAYS_ENABLED | CLOCK_IN_JZ4740,
+    .name = "osc_extal_12M",
+    .rate = 12000000,
+    .flags = ALWAYS_ENABLED | CLOCK_IN_JZ4740,
 };
 
 static struct clk osc_32K = {
-    .name      = "osc_32K",
-    .rate      = 32768,
-    .flags     = ALWAYS_ENABLED | CLOCK_IN_JZ4740,
+    .name = "osc_32K",
+    .rate = 32768,
+    .flags = ALWAYS_ENABLED | CLOCK_IN_JZ4740,
 };
 
 static struct clk lcd_pclk = {
-    .name      = "lcd_pclk",
-    //.rate    = ??,
-    //.flags   = ALWAYS_ENABLED | CLOCK_IN_JZ4740,
+    .name = "lcd_pclk",
+    //.rate     = ??,
+    //.flags    = ALWAYS_ENABLED | CLOCK_IN_JZ4740,
 };
 
 static struct clk pll_output = {
-    .name      = "pll_output",
+    .name = "pll_output",
     .parent = &osc_extal,
-    .flags     = ALWAYS_ENABLED | CLOCK_IN_JZ4740,
+    .flags = ALWAYS_ENABLED | CLOCK_IN_JZ4740,
 };
 
-static struct clk pll_divider= {
-    .name      = "pll_divider",
+static struct clk pll_divider = {
+    .name = "pll_divider",
     .parent = &pll_output,
-    .flags     = ALWAYS_ENABLED | CLOCK_IN_JZ4740,
+    .flags = ALWAYS_ENABLED | CLOCK_IN_JZ4740,
 };
 
-static struct clk cclk= {
-    .name      = "cclk",
+static struct clk cclk = {
+    .name = "cclk",
     .parent = &pll_output,
-    .flags     = ALWAYS_ENABLED | CLOCK_IN_JZ4740,
+    .flags = ALWAYS_ENABLED | CLOCK_IN_JZ4740,
 };
 
-static struct clk pclk= {
-    .name      = "pclk",
+static struct clk pclk = {
+    .name = "pclk",
     .parent = &pll_output,
-    .flags     = ALWAYS_ENABLED | CLOCK_IN_JZ4740,
+    .flags = ALWAYS_ENABLED | CLOCK_IN_JZ4740,
 };
 
-static struct clk hclk= {
-    .name      = "hclk",
+static struct clk hclk = {
+    .name = "hclk",
     .parent = &pll_output,
-    .flags     = ALWAYS_ENABLED | CLOCK_IN_JZ4740,
+    .flags = ALWAYS_ENABLED | CLOCK_IN_JZ4740,
 };
 
-static struct clk mclk= {
-    .name      = "mclk",
+static struct clk mclk = {
+    .name = "mclk",
     .parent = &pll_output,
-    .flags     = ALWAYS_ENABLED | CLOCK_IN_JZ4740,
+    .flags = ALWAYS_ENABLED | CLOCK_IN_JZ4740,
 };
 
-static struct clk ldclk= {
-    .name      = "ldclk",
+static struct clk ldclk = {
+    .name = "ldclk",
     .parent = &pll_divider,
-    .flags     = ALWAYS_ENABLED | CLOCK_IN_JZ4740,
+    .flags = ALWAYS_ENABLED | CLOCK_IN_JZ4740,
 };
 
-static struct clk lpclk= {
-    .name      = "lpclk",
+static struct clk lpclk = {
+    .name = "lpclk",
     .parent = &pll_divider,
-    .flags     = ALWAYS_ENABLED | CLOCK_IN_JZ4740,
+    .flags = ALWAYS_ENABLED | CLOCK_IN_JZ4740,
 };
 
-static struct clk i2sclk= {
-    .name      = "i2sclk",
+static struct clk i2sclk = {
+    .name = "i2sclk",
     .parent = &pll_divider,
-    .flags     = ALWAYS_ENABLED | CLOCK_IN_JZ4740,
+    .flags = ALWAYS_ENABLED | CLOCK_IN_JZ4740,
 };
 
-static struct clk mscclk= {
-    .name      = "mscclk",
+static struct clk mscclk = {
+    .name = "mscclk",
     .parent = &pll_divider,
-    .flags     = ALWAYS_ENABLED | CLOCK_IN_JZ4740,
+    .flags = ALWAYS_ENABLED | CLOCK_IN_JZ4740,
 };
 
-static struct clk usbclk= {
-    .name      = "usbclk",
+static struct clk usbclk = {
+    .name = "usbclk",
     .parent = &pll_divider,
-    .flags     = ALWAYS_ENABLED | CLOCK_IN_JZ4740,
+    .flags = ALWAYS_ENABLED | CLOCK_IN_JZ4740,
 };
 
-static struct clk ssiclk= {
-    .name      = "ssiclk",
+static struct clk ssiclk = {
+    .name = "ssiclk",
     .parent = &pll_divider,
-    .flags     = ALWAYS_ENABLED | CLOCK_IN_JZ4740,
+    .flags = ALWAYS_ENABLED | CLOCK_IN_JZ4740,
 };
 
 
 static struct clk *onchip_clks[] = {
-       &osc_extal,
-       &lcd_pclk,
-       &osc_32K,
-       &pll_output,
-       &pll_divider,
-       &cclk,
-       &pclk,
-       &hclk,
-       &mclk,
-       &ldclk,
-       &lpclk,
-       &i2sclk,
-       &mscclk,
-       &usbclk,
-       &ssiclk,
+    &osc_extal,
+    &lcd_pclk,
+    &osc_32K,
+    &pll_output,
+    &pll_divider,
+    &cclk,
+    &pclk,
+    &hclk,
+    &mclk,
+    &ldclk,
+    &lpclk,
+    &i2sclk,
+    &mscclk,
+    &usbclk,
+    &ssiclk,
 };
 
 struct clk *jz_findclk(struct jz_state_s *cpu, const char *name)
 {
     struct clk *i;
 
-    for (i = cpu->clks; i->name; i ++)
+    for (i = cpu->clks; i->name; i++)
         if (!strcmp(i->name, name) || (i->alias && !strcmp(i->alias, name)))
             return i;
     cpu_abort(cpu->env, "%s: %s not found\n", __FUNCTION__, name);
@@ -153,14 +153,14 @@ struct clk *jz_findclk(struct jz_state_s *cpu, const char *name)
 
 void jz_clk_get(struct clk *clk)
 {
-    clk->usecount ++;
+    clk->usecount++;
 }
 
 void jz_clk_put(struct clk *clk)
 {
-    if (!(clk->usecount --))
+    if (!(clk->usecount--))
         cpu_abort(cpu_single_env, "%s: %s is not in use\n",
-                        __FUNCTION__, clk->name);
+                  __FUNCTION__, clk->name);
 }
 
 static void jz_clk_update(struct clk *clk)
@@ -175,8 +175,9 @@ static void jz_clk_update(struct clk *clk)
         parent = 1;
 
     running = parent && (clk->enabled ||
-                    ((clk->flags & ALWAYS_ENABLED) && clk->usecount));
-    if (clk->running != running) {
+                         ((clk->flags & ALWAYS_ENABLED) && clk->usecount));
+    if (clk->running != running)
+    {
         clk->running = running;
         //for (user = clk->users; *user; user ++)
         //    qemu_set_irq(*user, running);
@@ -186,7 +187,8 @@ static void jz_clk_update(struct clk *clk)
 }
 
 static void jz_clk_rate_update_full(struct clk *clk, unsigned long int rate,
-                unsigned long int div, unsigned long int mult)
+                                    unsigned long int div,
+                                    unsigned long int mult)
 {
     struct clk *i;
     //qemu_irq *user;
@@ -195,9 +197,9 @@ static void jz_clk_rate_update_full(struct clk *clk, unsigned long int rate,
     if (clk->running)
         //for (user = clk->users; *user; user ++)
         //    qemu_irq_raise(*user);
-    for (i = clk->child1; i; i = i->sibling)
-        jz_clk_rate_update_full(i, rate,
-                        div * i->divisor, mult * i->multiplier);
+        for (i = clk->child1; i; i = i->sibling)
+            jz_clk_rate_update_full(i, rate,
+                                    div * i->divisor, mult * i->multiplier);
 }
 
 static void jz_clk_rate_update(struct clk *clk)
@@ -205,7 +207,8 @@ static void jz_clk_rate_update(struct clk *clk)
     struct clk *i;
     unsigned long int div, mult = div = 1;
 
-    for (i = clk; i->parent; i = i->parent) {
+    for (i = clk; i->parent; i = i->parent)
+    {
         div *= i->divisor;
         mult *= i->multiplier;
     }
@@ -217,18 +220,21 @@ void jz_clk_reparent(struct clk *clk, struct clk *parent)
 {
     struct clk **p;
 
-    if (clk->parent) {
+    if (clk->parent)
+    {
         for (p = &clk->parent->child1; *p != clk; p = &(*p)->sibling);
         *p = clk->sibling;
     }
 
     clk->parent = parent;
-    if (parent) {
+    if (parent)
+    {
         clk->sibling = parent->child1;
         parent->child1 = clk;
         jz_clk_update(clk);
         jz_clk_rate_update(clk);
-    } else
+    }
+    else
         clk->sibling = 0;
 }
 
@@ -258,7 +264,7 @@ int64_t jz_clk_getrate(struct clk *clk)
     return clk->rate;
 }
 
-void jz_clk_init(struct jz_state_s *mpu,uint32_t osc_extal_freq)
+void jz_clk_init(struct jz_state_s *mpu, uint32_t osc_extal_freq)
 {
     struct clk **i, *j, *k;
     int count;
@@ -273,33 +279,36 @@ void jz_clk_init(struct jz_state_s *mpu,uint32_t osc_extal_freq)
     else
         return;
 
-    osc_extal.rate = osc_extal_freq;    
-       
-    for (i = onchip_clks, count = 0; *i; i ++)
+    osc_extal.rate = osc_extal_freq;
+
+    for (i = onchip_clks, count = 0; *i; i++)
         if ((*i)->flags & flag)
-            count ++;
+            count++;
     mpu->clks = (struct clk *) qemu_mallocz(sizeof(struct clk) * (count + 1));
-    for (i = onchip_clks, j = mpu->clks; *i; i ++)
-        if ((*i)->flags & flag) {
+    for (i = onchip_clks, j = mpu->clks; *i; i++)
+        if ((*i)->flags & flag)
+        {
             memcpy(j, *i, sizeof(struct clk));
-            for (k = mpu->clks; k < j; k ++)
-                if (j->parent && !strcmp(j->parent->name, k->name)) {
+            for (k = mpu->clks; k < j; k++)
+                if (j->parent && !strcmp(j->parent->name, k->name))
+                {
                     j->parent = k;
                     j->sibling = k->child1;
                     k->child1 = j;
-                } else if (k->parent && !strcmp(k->parent->name, j->name)) {
+                }
+                else if (k->parent && !strcmp(k->parent->name, j->name))
+                {
                     k->parent = j;
                     k->sibling = j->child1;
                     j->child1 = k;
                 }
-            j->divisor = j->divisor ?: 1;
-            j->multiplier = j->multiplier ?: 1;
-            j ++;
+            j->divisor = j->divisor ? : 1;
+            j->multiplier = j->multiplier ? : 1;
+            j++;
         }
-    for (j = mpu->clks; count --; j ++) {
+    for (j = mpu->clks; count--; j++)
+    {
         jz_clk_update(j);
         jz_clk_rate_update(j);
     }
 }
-
-
index 6a67db7..d925244 100755 (executable)
  *
  */
 
-#include "mips_jz.h"
-#include "qemu-common.h"
-#include "sysemu.h"
-#include "arm-misc.h"
-#include "irq.h"
-#include "console.h"
+#include "hw.h"
+#include "pc.h"
+#include "fdc.h"
+#include "net.h"
 #include "boards.h"
-#include "i2c.h"
-#include "devices.h"
+#include "smbus.h"
+#include "block.h"
 #include "flash.h"
-#include "hw.h"
+#include "mips.h"
+#include "pci.h"
+#include "qemu-char.h"
+#include "sysemu.h"
+#include "audio/audio.h"
+#include "boards.h"
+#include "qemu-log.h"
+#include "mips_jz.h"
 
 
 
 #define PAVO_RAM_SIZE       (0x4000000) /*64M */
-#define PAVO_OSC_EXTAL     (12000000)  /*12MHZ*/
+#define PAVO_OSC_EXTAL     (12000000)   /*12MHZ */
 
 /* pavo board support */
 struct mips_pavo_s
@@ -53,16 +58,11 @@ struct mips_pavo_s
 };
 
 
-
-
-
-
-
-
-    void mips_pavo_init(ram_addr_t ram_size, int vga_ram_size,
-                        const char *boot_device, DisplayState * ds,
-                        const char *kernel_filename, const char *kernel_cmdline,
-                        const char *initrd_filename, const char *cpu_model)
+static void mips_pavo_init(ram_addr_t ram_size, int vga_ram_size,
+                    const char *boot_device, DisplayState * ds,
+                    const char *kernel_filename,
+                    const char *kernel_cmdline,
+                    const char *initrd_filename, const char *cpu_model)
 {
     struct mips_pavo_s *s = (struct mips_pavo_s *) qemu_mallocz(sizeof(*s));
 
@@ -86,5 +86,3 @@ QEMUMachine mips_pavo_machine = {
     .ram_require = (JZ4740_SRAM_SIZE + PAVO_RAM_SIZE) | RAMSIZE_FIXED,
     .nodisk_ok = 1,
 };
-
-