hw/mips_jz.h

   1 /*
   2  * ingenic JZ Soc
   3  *
   4  * Copyright (C) 2009 yajin<yajin@vm-kernel.org>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 or
   9  * (at your option) version 3 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19  * MA 02111-1307 USA
  20  */
  21 #ifndef _MIPS_JZ_H_
  22 #define _MIPS_JZ_H_
  23
  24 #include "qemu-common.h"
  25
  26
  27
  28 #define JZ4740_SRAM_SIZE        0x4000
  29 #define JZ4740_SRAM_BASE 0x80000000
  30 #define JZ4740_SDRAM_BASE 0x80004000
  31
  32 #define JZ4740_PHYS_BASE(a) ((a)-0xa0000000)
  33
  34 #define JZ4740_CPM_BASE 0xB0000000
  35 #define JZ4740_INTC_BASE        0xB0001000
  36 #define JZ4740_TCU_BASE 0xB0002000
  37 #define JZ4740_WDT_BASE 0xB0002000
  38 #define JZ4740_RTC_BASE 0xB0003000
  39 #define JZ4740_GPIO_BASE        0xB0010000
  40 #define JZ4740_AIC_BASE 0xB0020000
  41 #define JZ4740_ICDC_BASE        0xB0020000
  42 #define JZ4740_MSC_BASE 0xB0021000
  43 #define JZ4740_UART0_BASE       0xB0030000
  44 #define JZ4740_I2C_BASE 0xB0042000
  45 #define JZ4740_SSI_BASE 0xB0043000
  46 #define JZ4740_SADC_BASE        0xB0070000
  47 #define JZ4740_EMC_BASE 0xB3010000
  48 #define JZ4740_DMAC_BASE        0xB3020000
  49 #define JZ4740_UHC_BASE 0xB3030000
  50 #define JZ4740_UDC_BASE 0xB3040000
  51 #define JZ4740_LCD_BASE 0xB3050000
  52 #define JZ4740_SLCD_BASE        0xB3050000
  53 #define JZ4740_CIM_BASE 0xB3060000
  54 #define JZ4740_ETH_BASE 0xB3100000
  55
  56 /* Clock Control Register */
  57 #define CPM_CPCCR_I2CS          (1 << 31)
  58 #define CPM_CPCCR_CLKOEN        (1 << 30)
  59 #define CPM_CPCCR_UCS           (1 << 29)
  60 #define CPM_CPCCR_UDIV_BIT      23
  61 #define CPM_CPCCR_UDIV_MASK     (0x3f << CPM_CPCCR_UDIV_BIT)
  62 #define CPM_CPCCR_CE            (1 << 22)
  63 #define CPM_CPCCR_PCS           (1 << 21)
  64 #define CPM_CPCCR_LDIV_BIT      16
  65 #define CPM_CPCCR_LDIV_MASK     (0x1f << CPM_CPCCR_LDIV_BIT)
  66 #define CPM_CPCCR_MDIV_BIT      12
  67 #define CPM_CPCCR_MDIV_MASK     (0x0f << CPM_CPCCR_MDIV_BIT)
  68 #define CPM_CPCCR_PDIV_BIT      8
  69 #define CPM_CPCCR_PDIV_MASK     (0x0f << CPM_CPCCR_PDIV_BIT)
  70 #define CPM_CPCCR_HDIV_BIT      4
  71 #define CPM_CPCCR_HDIV_MASK     (0x0f << CPM_CPCCR_HDIV_BIT)
  72 #define CPM_CPCCR_CDIV_BIT      0
  73 #define CPM_CPCCR_CDIV_MASK     (0x0f << CPM_CPCCR_CDIV_BIT)
  74
  75
  76 /* I2S Clock Divider Register */
  77 #define CPM_I2SCDR_I2SDIV_BIT   0
  78 #define CPM_I2SCDR_I2SDIV_MASK  (0x1ff << CPM_I2SCDR_I2SDIV_BIT)
  79
  80 /* LCD Pixel Clock Divider Register */
  81 #define CPM_LPCDR_PIXDIV_BIT    0
  82 #define CPM_LPCDR_PIXDIV_MASK   (0x1ff << CPM_LPCDR_PIXDIV_BIT)
  83
  84 /* MSC Clock Divider Register */
  85 #define CPM_MSCCDR_MSCDIV_BIT   0
  86 #define CPM_MSCCDR_MSCDIV_MASK  (0x1f << CPM_MSCCDR_MSCDIV_BIT)
  87
  88 /* PLL Control Register */
  89 #define CPM_CPPCR_PLLM_BIT      23
  90 #define CPM_CPPCR_PLLM_MASK     (0x1ff << CPM_CPPCR_PLLM_BIT)
  91 #define CPM_CPPCR_PLLN_BIT      18
  92 #define CPM_CPPCR_PLLN_MASK     (0x1f << CPM_CPPCR_PLLN_BIT)
  93 #define CPM_CPPCR_PLLOD_BIT     16
  94 #define CPM_CPPCR_PLLOD_MASK    (0x03 << CPM_CPPCR_PLLOD_BIT)
  95 #define CPM_CPPCR_PLLS          (1 << 10)
  96 #define CPM_CPPCR_PLLBP         (1 << 9)
  97 #define CPM_CPPCR_PLLEN         (1 << 8)
  98 #define CPM_CPPCR_PLLST_BIT     0
  99 #define CPM_CPPCR_PLLST_MASK    (0xff << CPM_CPPCR_PLLST_BIT)
 100
 101
 102
 103
 104
 105 #define JZ_FMT_plx "%#16x"
 106
 107 uint32_t jz4740_badwidth_read8(void *opaque, target_phys_addr_t addr);
 108 uint32_t jz4740_badwidth_read16(void *opaque, target_phys_addr_t addr);
 109 uint32_t jz4740_badwidth_read32(void *opaque, target_phys_addr_t addr);
 110 void jz4740_badwidth_write8(void *opaque, target_phys_addr_t addr,
 111                                     uint32_t value);
 112 void jz4740_badwidth_write16(void *opaque, target_phys_addr_t addr,
 113                                     uint32_t value);
 114 void jz4740_badwidth_write32(void *opaque, target_phys_addr_t addr,
 115                                     uint32_t value);
 116
 117 #define IO_ACCESS_VERBOSE                       1
 118
 119 #ifdef IO_ACCESS_VERBOSE
 120 #define JZ4740_8B_REG(paddr)            \
 121         fprintf(stderr, "%s: 8-bit register " JZ_FMT_plx "\n",  \
 122                         __FUNCTION__, paddr)
 123 #define JZ4740_16B_REG(paddr)           \
 124         fprintf(stderr, "%s: 16-bit register " JZ_FMT_plx "\n", \
 125                         __FUNCTION__, paddr)
 126 #define JZ4740_32B_REG(paddr)           \
 127         fprintf(stderr, "%s: 32-bit register " JZ_FMT_plx "\n", \
 128                         __FUNCTION__, paddr)
 129 #define JZ4740_RO_REG(paddr)            \
 130         fprintf(stderr, "%s: write to read only 32-bit register " JZ_FMT_plx "\n",      \
 131                         __FUNCTION__, paddr)
 132 #define JZ4740_WO_REG(paddr)            \
 133         fprintf(stderr, "%s: read from write only 32-bit register " JZ_FMT_plx "\n",    \
 134                         __FUNCTION__, paddr)
 135 #else
 136 #define JZ4740_8B_REG(paddr)
 137 #define JZ4740_16B_REG(paddr)
 138 #define JZ4740_32B_REG(paddr)
 139 #define JZ4740_RO_REG(paddr)
 140 #define JZ4740_WO_REG(paddr)
 141 #endif
 142
 143
 144
 145 /*forward define*/
 146 struct jz_state_s;
 147
 148
 149 /*mips_jz_clk.c*/
 150 struct clk {
 151     const char *name;
 152     const char *alias;
 153     struct clk *parent;
 154     struct clk *child1;
 155     struct clk *sibling;
 156
 157     uint32_t flags;
 158     int id;
 159
 160     int running;                /* Is currently ticking */
 161     int enabled;                /* Is enabled, regardless of its input clk */
 162     unsigned long rate;         /* Current rate (if .running) */
 163     unsigned int divisor;       /* Rate relative to input (if .enabled) */
 164     unsigned int multiplier;    /* Rate relative to input (if .enabled) */
 165     //int usecount;
 166 };
 167 typedef struct clk *jz_clk;
 168 void jz_clk_init(struct jz_state_s *mpu,uint32_t osc_extal_freq);
 169 jz_clk jz_findclk(struct jz_state_s *mpu, const char *name);
 170 void jz_clk_get(jz_clk clk);
 171 void jz_clk_put(jz_clk clk);
 172 void jz_clk_onoff(jz_clk clk, int on);
 173 void jz_clk_canidle(jz_clk clk, int can);
 174 void jz_clk_setrate(jz_clk clk, int divide, int multiply);
 175 int64_t jz_clk_getrate(jz_clk clk);
 176 void jz_clk_reparent(jz_clk clk, jz_clk parent);
 177
 178 /*mips_jz.c*/
 179 struct jz_state_s *jz4740_init(unsigned long sdram_size,
 180                                                               uint32_t osc_extal_freq,DisplayState * ds);
 181
 182 enum jz_cpu_model {
 183         jz4740,
 184         jz4730,
 185         jz4750
 186     };
 187 #define cpu_is_jz4730(cpu)              (cpu->mpu_model == jz4730)
 188 #define cpu_is_jz4740(cpu)              (cpu->mpu_model == jz4740)
 189 #define cpu_is_jz4750(cpu)              (cpu->mpu_model == jz4750)
 190
 191 struct jz_state_s {
 192         enum jz_cpu_model mpu_model;
 193         CPUState *env;
 194         unsigned long sdram_size;
 195     unsigned long sram_size;
 196
 197         jz_clk clks;
 198
 199         struct jz4740_cpm_s *cpm;
 200         struct jz4740_emc_s *emc;
 201         struct jz4740_gpio_s *gpio;
 202         struct jz4740_rtc_s *rtc;
 203         struct jz4740_tcu_s *tcu;
 204         struct jz4740_lcdc_s *lcdc;
 205         struct jz4740_dma_s *dma;
 206
 207 };
 208
 209 #endif