hw/mips_pavo.c

   1 /*
   2  * QEMU pavo demo board emulation
   3  *
   4  * Copyright (c) 2008 yajin (yajin@vm-kernel.org)
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25
  26 /*
  27  * The emulation target is pavo demo board.
  28  *  http://www.ingenic.cn/eng/productServ/kfyd/Hardware/pffaqQuestionContent.aspx?Category=2&Question=3
  29  *
  30  */
  31
  32 #include "hw.h"
  33 #include "pc.h"
  34 #include "fdc.h"
  35 #include "net.h"
  36 #include "boards.h"
  37 #include "smbus.h"
  38 #include "block.h"
  39 #include "flash.h"
  40 #include "mips.h"
  41 #include "pci.h"
  42 #include "qemu-char.h"
  43 #include "sysemu.h"
  44 #include "audio/audio.h"
  45 #include "boards.h"
  46 #include "qemu-log.h"
  47 #include "mips_jz.h"
  48
  49
  50
  51 #define PAVO_RAM_SIZE       (0x4000000) /*64M */
  52 #define PAVO_OSC_EXTAL     (12000000)   /*12MHZ */
  53
  54 /* pavo board support */
  55 struct mips_pavo_s
  56 {
  57     struct jz_state_s *soc;
  58
  59     struct nand_bflash_s *nand;
  60 };
  61
  62 static uint32_t pavo_nand_read8(void *opaque, target_phys_addr_t addr)
  63 {
  64         struct mips_pavo_s *s = (struct mips_pavo_s *) opaque;
  65
  66         switch (addr)
  67         {
  68                 case 0x8000: /*NAND_COMMAND*/
  69                 case 0x10000: /*NAND_ADDRESS*/
  70                         jz4740_badwidth_read8(s,addr);
  71                         break;
  72                 case 0x0: /*NAND_DATA*/
  73                         return nandb_read_data8(s->nand);
  74                         break;
  75                 default:
  76                         jz4740_badwidth_read8(s,addr);
  77                         break;
  78         }
  79     return 0;
  80 }
  81
  82 static void pavo_nand_write8(void *opaque, target_phys_addr_t addr,
  83                 uint32_t value)
  84 {
  85         struct mips_pavo_s *s = (struct mips_pavo_s *) opaque;
  86
  87         //printf("write addr %x value %x \n",addr,value);
  88
  89     switch (addr)
  90         {
  91                 case 0x8000: /*NAND_COMMAND*/
  92                         nandb_write_command(s->nand,value);
  93                         break;
  94                 case 0x10000: /*NAND_ADDRESS*/
  95                         nandb_write_address(s->nand,value);
  96                         break;
  97                 case 0x0: /*NAND_DATA*/
  98                         nandb_write_data8(s->nand,value);
  99                         break;
 100                 default:
 101                         jz4740_badwidth_write8(s,addr,value);
 102                         break;
 103         }
 104 }
 105
 106
 107 CPUReadMemoryFunc *pavo_nand_readfn[] = {
 108         pavo_nand_read8,
 109         jz4740_badwidth_read16,
 110         jz4740_badwidth_read32,
 111 };
 112 CPUWriteMemoryFunc *pavo_nand_writefn[] = {
 113         pavo_nand_write8,
 114         jz4740_badwidth_write16,
 115         jz4740_badwidth_write32,
 116 };
 117
 118 static void pavo_nand_setup(struct mips_pavo_s *s)
 119 {
 120         int iomemtype;
 121
 122         /*K9K8G08U0*/
 123         s->nand = nandb_init(NAND_MFR_SAMSUNG,0xd3);
 124
 125         iomemtype = cpu_register_io_memory(0, pavo_nand_readfn,
 126                     pavo_nand_writefn, s);
 127     cpu_register_physical_memory(0x18000000, 0x20000, iomemtype);
 128 }
 129
 130 static int pavo_nand_read_page(struct mips_pavo_s *s,uint8_t *buf, uint16_t page_addr)
 131 {
 132         uint8_t *p;
 133         int i;
 134
 135         p=(uint8_t *)buf;
 136
 137         /*send command 0x0*/
 138         pavo_nand_write8(s,0x00008000,0);
 139         /*send page address */
 140         pavo_nand_write8(s,0x00010000,page_addr&0xff);
 141         pavo_nand_write8(s,0x00010000,(page_addr>>8)&0x7);
 142         pavo_nand_write8(s,0x00010000,(page_addr>>11)&0xff);
 143         pavo_nand_write8(s,0x00010000,(page_addr>>19)&0xff);
 144         pavo_nand_write8(s,0x00010000,(page_addr>>27)&0xff);
 145         /*send command 0x30*/
 146         pavo_nand_write8(s,0x00008000,0x30);
 147
 148         for (i=0;i<0x800;i++)
 149         {
 150                 *p++ = pavo_nand_read8(s,0x00000000);
 151         }
 152         return 1;
 153 }
 154
 155 /*read the u-boot from NAND Flash into internal RAM*/
 156 static int pavo_boot_from_nand(struct mips_pavo_s *s)
 157 {
 158         uint32_t len;
 159         uint8_t nand_page[0x800],*load_dest;
 160         uint32_t nand_pages,i;
 161
 162         //int fd;
 163
 164
 165         len = 0x2000; /*8K*/
 166
 167         /*put the first page into internal ram*/
 168         load_dest = phys_ram_base;
 169
 170         nand_pages = len/0x800;
 171         //fd = open("u-boot.bin", O_RDWR | O_CREAT);
 172         for (i=0;i<nand_pages;i++)
 173         {
 174                 pavo_nand_read_page(s,nand_page,i*0x800);
 175                 memcpy(load_dest,nand_page,0x800);
 176                 //write(fd,nand_page,0x800);
 177                 load_dest += 0x800;
 178         }
 179         s->soc->env->active_tc.PC = 0x80000004;
 180
 181         //close(fd);
 182         return 0;
 183
 184 }
 185
 186
 187  static int pavo_rom_emu(struct mips_pavo_s *s)
 188 {
 189         if (pavo_boot_from_nand(s)<0)
 190                 return (-1);
 191         return (0);
 192 }
 193
 194 static void mips_pavo_init(ram_addr_t ram_size, int vga_ram_size,
 195                     const char *boot_device, DisplayState * ds,
 196                     const char *kernel_filename,
 197                     const char *kernel_cmdline,
 198                     const char *initrd_filename, const char *cpu_model)
 199 {
 200     struct mips_pavo_s *s = (struct mips_pavo_s *) qemu_mallocz(sizeof(*s));
 201
 202     if (ram_size < PAVO_RAM_SIZE + JZ4740_SRAM_SIZE)
 203     {
 204         fprintf(stderr, "This architecture uses %d bytes of memory\n",
 205                 PAVO_RAM_SIZE + JZ4740_SRAM_SIZE);
 206         exit(1);
 207     }
 208     s->soc = jz4740_init(PAVO_RAM_SIZE, PAVO_OSC_EXTAL,ds);
 209     pavo_nand_setup(s);
 210     if (pavo_rom_emu(s)<0)
 211         {
 212                 fprintf(stderr,"boot from nand failed \n");
 213                 exit(-1);
 214         }
 215
 216 }
 217
 218
 219
 220
 221 QEMUMachine mips_pavo_machine = {
 222     .name = "pavo",
 223     .desc = "JZ Pavo demo board",
 224     .init = mips_pavo_init,
 225     .ram_require = (JZ4740_SRAM_SIZE + PAVO_RAM_SIZE) | RAMSIZE_FIXED,
 226     .nodisk_ok = 1,
 227 };