hw/mips_jz_clk.c

   1 /*
   2  * JZ Soc clocks.
   3  *
   4  * Copyright (C) 2006-2008 yajin <yajin@vm-kernel.org>
   5  *
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include "hw.h"
  24 #include "mips_jz.h"
  25
  26
  27
  28 #define ALWAYS_ENABLED   (1 << 0)
  29 #define CLOCK_IN_JZ4730  (1 << 10)
  30 #define CLOCK_IN_JZ4740  (1 << 11)
  31 #define CLOCK_IN_JZ4750  (1 << 12)
  32
  33
  34
  35 static struct clk osc_extal = {
  36     .name = "osc_extal_12M",
  37     .rate = 12000000,
  38     .flags = ALWAYS_ENABLED | CLOCK_IN_JZ4740,
  39 };
  40
  41 static struct clk osc_32K = {
  42     .name = "osc_32K",
  43     .rate = 32768,
  44     .flags = ALWAYS_ENABLED | CLOCK_IN_JZ4740,
  45 };
  46
  47 static struct clk lcd_pclk = {
  48     .name = "lcd_pclk",
  49     //.rate     = ??,
  50     //.flags    = ALWAYS_ENABLED | CLOCK_IN_JZ4740,
  51 };
  52
  53 static struct clk pll_output = {
  54     .name = "pll_output",
  55     .parent = &osc_extal,
  56     .flags = ALWAYS_ENABLED | CLOCK_IN_JZ4740,
  57 };
  58
  59 static struct clk pll_divider = {
  60     .name = "pll_divider",
  61     .parent = &pll_output,
  62     .flags = ALWAYS_ENABLED | CLOCK_IN_JZ4740,
  63 };
  64
  65 static struct clk cclk = {
  66     .name = "cclk",
  67     .parent = &pll_output,
  68     .flags = ALWAYS_ENABLED | CLOCK_IN_JZ4740,
  69 };
  70
  71 static struct clk pclk = {
  72     .name = "pclk",
  73     .parent = &pll_output,
  74     .flags = ALWAYS_ENABLED | CLOCK_IN_JZ4740,
  75 };
  76
  77 static struct clk hclk = {
  78     .name = "hclk",
  79     .parent = &pll_output,
  80     .flags = ALWAYS_ENABLED | CLOCK_IN_JZ4740,
  81 };
  82
  83 static struct clk mclk = {
  84     .name = "mclk",
  85     .parent = &pll_output,
  86     .flags = ALWAYS_ENABLED | CLOCK_IN_JZ4740,
  87 };
  88
  89 static struct clk ldclk = {
  90     .name = "ldclk",
  91     .parent = &pll_divider,
  92     .flags = ALWAYS_ENABLED | CLOCK_IN_JZ4740,
  93 };
  94
  95 static struct clk lpclk = {
  96     .name = "lpclk",
  97     .parent = &pll_divider,
  98     .flags = ALWAYS_ENABLED | CLOCK_IN_JZ4740,
  99 };
 100
 101 static struct clk i2sclk = {
 102     .name = "i2sclk",
 103     .parent = &pll_divider,
 104     .flags = ALWAYS_ENABLED | CLOCK_IN_JZ4740,
 105 };
 106
 107 static struct clk mscclk = {
 108     .name = "mscclk",
 109     .parent = &pll_divider,
 110     .flags = ALWAYS_ENABLED | CLOCK_IN_JZ4740,
 111 };
 112
 113 static struct clk usbclk = {
 114     .name = "usbclk",
 115     .parent = &pll_divider,
 116     .flags = ALWAYS_ENABLED | CLOCK_IN_JZ4740,
 117 };
 118
 119 static struct clk ssiclk = {
 120     .name = "ssiclk",
 121     .parent = &pll_divider,
 122     .flags = ALWAYS_ENABLED | CLOCK_IN_JZ4740,
 123 };
 124
 125
 126 static struct clk *onchip_clks[] = {
 127     &osc_extal,
 128     &lcd_pclk,
 129     &osc_32K,
 130     &pll_output,
 131     &pll_divider,
 132     &cclk,
 133     &pclk,
 134     &hclk,
 135     &mclk,
 136     &ldclk,
 137     &lpclk,
 138     &i2sclk,
 139     &mscclk,
 140     &usbclk,
 141     &ssiclk,
 142 };
 143
 144 struct clk *jz_findclk(struct jz_state_s *cpu, const char *name)
 145 {
 146     struct clk *i;
 147
 148     for (i = cpu->clks; i->name; i++)
 149         if (!strcmp(i->name, name) || (i->alias && !strcmp(i->alias, name)))
 150             return i;
 151     cpu_abort(cpu->env, "%s: %s not found\n", __FUNCTION__, name);
 152 }
 153
 154 void jz_clk_get(struct clk *clk)
 155 {
 156     clk->usecount++;
 157 }
 158
 159 void jz_clk_put(struct clk *clk)
 160 {
 161     if (!(clk->usecount--))
 162         cpu_abort(cpu_single_env, "%s: %s is not in use\n",
 163                   __FUNCTION__, clk->name);
 164 }
 165
 166 static void jz_clk_update(struct clk *clk)
 167 {
 168     int parent, running;
 169     //qemu_irq *user;
 170     struct clk *i;
 171
 172     if (clk->parent)
 173         parent = clk->parent->running;
 174     else
 175         parent = 1;
 176
 177     running = parent && (clk->enabled ||
 178                          ((clk->flags & ALWAYS_ENABLED) && clk->usecount));
 179     if (clk->running != running)
 180     {
 181         clk->running = running;
 182         //for (user = clk->users; *user; user ++)
 183         //    qemu_set_irq(*user, running);
 184         for (i = clk->child1; i; i = i->sibling)
 185             jz_clk_update(i);
 186     }
 187 }
 188
 189 static void jz_clk_rate_update_full(struct clk *clk, unsigned long int rate,
 190                                     unsigned long int div,
 191                                     unsigned long int mult)
 192 {
 193     struct clk *i;
 194     //qemu_irq *user;
 195
 196     clk->rate = muldiv64(rate, mult, div);
 197     if (clk->running)
 198         //for (user = clk->users; *user; user ++)
 199         //    qemu_irq_raise(*user);
 200         for (i = clk->child1; i; i = i->sibling)
 201             jz_clk_rate_update_full(i, rate,
 202                                     div * i->divisor, mult * i->multiplier);
 203 }
 204
 205 static void jz_clk_rate_update(struct clk *clk)
 206 {
 207     struct clk *i;
 208     unsigned long int div, mult = div = 1;
 209
 210     for (i = clk; i->parent; i = i->parent)
 211     {
 212         div *= i->divisor;
 213         mult *= i->multiplier;
 214     }
 215
 216     jz_clk_rate_update_full(clk, i->rate, div, mult);
 217 }
 218
 219 void jz_clk_reparent(struct clk *clk, struct clk *parent)
 220 {
 221     struct clk **p;
 222
 223     if (clk->parent)
 224     {
 225         for (p = &clk->parent->child1; *p != clk; p = &(*p)->sibling);
 226         *p = clk->sibling;
 227     }
 228
 229     clk->parent = parent;
 230     if (parent)
 231     {
 232         clk->sibling = parent->child1;
 233         parent->child1 = clk;
 234         jz_clk_update(clk);
 235         jz_clk_rate_update(clk);
 236     }
 237     else
 238         clk->sibling = 0;
 239 }
 240
 241 void jz_clk_onoff(struct clk *clk, int on)
 242 {
 243     clk->enabled = on;
 244     jz_clk_update(clk);
 245 }
 246
 247 void jz_clk_canidle(struct clk *clk, int can)
 248 {
 249     if (can)
 250         jz_clk_put(clk);
 251     else
 252         jz_clk_get(clk);
 253 }
 254
 255 void jz_clk_setrate(struct clk *clk, int divide, int multiply)
 256 {
 257     clk->divisor = divide;
 258     clk->multiplier = multiply;
 259     jz_clk_rate_update(clk);
 260 }
 261
 262 int64_t jz_clk_getrate(struct clk *clk)
 263 {
 264     return clk->rate;
 265 }
 266
 267 void jz_clk_init(struct jz_state_s *mpu, uint32_t osc_extal_freq)
 268 {
 269     struct clk **i, *j, *k;
 270     int count;
 271     int flag;
 272
 273     if (cpu_is_jz4730(mpu))
 274         flag = CLOCK_IN_JZ4730;
 275     else if (cpu_is_jz4740(mpu))
 276         flag = CLOCK_IN_JZ4740;
 277     else if (cpu_is_jz4750(mpu))
 278         flag = CLOCK_IN_JZ4750;
 279     else
 280         return;
 281
 282     osc_extal.rate = osc_extal_freq;
 283
 284     for (i = onchip_clks, count = 0; *i; i++)
 285         if ((*i)->flags & flag)
 286             count++;
 287     mpu->clks = (struct clk *) qemu_mallocz(sizeof(struct clk) * (count + 1));
 288     for (i = onchip_clks, j = mpu->clks; *i; i++)
 289         if ((*i)->flags & flag)
 290         {
 291             memcpy(j, *i, sizeof(struct clk));
 292             for (k = mpu->clks; k < j; k++)
 293                 if (j->parent && !strcmp(j->parent->name, k->name))
 294                 {
 295                     j->parent = k;
 296                     j->sibling = k->child1;
 297                     k->child1 = j;
 298                 }
 299                 else if (k->parent && !strcmp(k->parent->name, j->name))
 300                 {
 301                     k->parent = j;
 302                     k->sibling = j->child1;
 303                     j->child1 = k;
 304                 }
 305             j->divisor = j->divisor ? : 1;
 306             j->multiplier = j->multiplier ? : 1;
 307             j++;
 308         }
 309     for (j = mpu->clks; count--; j++)
 310     {
 311         jz_clk_update(j);
 312         jz_clk_rate_update(j);
 313     }
 314 }