hw/mips_jz.c

   1 /*
   2  * QEMU JZ Soc emulation
   3  *
   4  * Copyright (c) 2009 yajin (yajin@vm-kernel.org)
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25
  26 /*
  27  * The emulation target is pavo demo board.
  28  *  http://www.ingenic.cn/eng/productServ/kfyd/Hardware/pffaqQuestionContent.aspx?Category=2&Question=3
  29  *
  30  */
  31
  32 #include "hw.h"
  33 #include "mips.h"
  34 #include "sysemu.h"
  35 #include "qemu-timer.h"
  36 #include "qemu-char.h"
  37 #include "flash.h"
  38 #include "soc_dma.h"
  39 #include "audio/audio.h"
  40 #include "pc.h"
  41 #include "osdep.h"
  42 #include "mips_jz.h"
  43 #include "console.h"
  44
  45 #define DEBUG                   /*global debug on/off */
  46
  47 #define DEBUG_CPM                     (1<<0x0)
  48 #define DEBUG_EMC                     (1<<0x1)
  49 #define DEBUG_GPIO                    (1<<0x2)
  50 #define DEBUG_RTC                       (1<<0x3)
  51 #define DEBUG_TCU                       (1<<0x4)
  52 #define DEBUG_LCDC                      (1<<0x5)
  53 #define DEBUG_DMA                      (1<<0x6)
  54 #define  DEBUG_FLAG                 DEBUG_RTC //(DEBUG_CPM|DEBUG_EMC|DEBUG_GPIO    \
  55                                                                                                                  //     | DEBUG_RTC | DEBUG_TCU | DEBUG_LCDC | DEBUG_DMA)
  56                                                                                                                 //DEBUG_TCU// (DEBUG_CPM|DEBUG_EMC|DEBUG_GPIO
  57                                                                                                                 //      | DEBUG_RTC | DEBUG_TCU | DEBUG_LCDC | DEBUG_DMA)
  58
  59
  60 #ifdef DEBUG
  61 FILE *fp;
  62 static void debug_init(void)
  63 {
  64     fp = fopen("jz4740.txt", "w+");
  65     if (fp == NULL)
  66     {
  67         fprintf(stderr, "can not open jz4740.txt \n");
  68         exit(-1);
  69     }
  70 }
  71 static void debug_out(uint32_t flag, const char *format, ...)
  72 {
  73     va_list ap;
  74     if (fp)
  75     {
  76         if (flag & DEBUG_FLAG)
  77         {
  78             va_start(ap, format);
  79             vfprintf(fp, format, ap);
  80             fflush(fp);
  81             va_end(ap);
  82         }
  83     }
  84 }
  85 #else
  86 static void debug_init(void)
  87 {
  88 }
  89 static void debug_out(uint32_t flag, const char *format, ...)
  90 {
  91 }
  92 #endif
  93
  94 uint32_t jz4740_badwidth_read8(void *opaque, target_phys_addr_t addr)
  95 {
  96     uint8_t ret;
  97
  98     JZ4740_8B_REG(addr);
  99     cpu_physical_memory_read(addr, (void *) &ret, 1);
 100     return ret;
 101 }
 102
 103 void jz4740_badwidth_write8(void *opaque, target_phys_addr_t addr,
 104                             uint32_t value)
 105 {
 106     uint8_t val8 = value;
 107
 108     JZ4740_8B_REG(addr);
 109     cpu_physical_memory_write(addr, (void *) &val8, 1);
 110 }
 111
 112 uint32_t jz4740_badwidth_read16(void *opaque, target_phys_addr_t addr)
 113 {
 114     uint16_t ret;
 115     JZ4740_16B_REG(addr);
 116     cpu_physical_memory_read(addr, (void *) &ret, 2);
 117     return ret;
 118 }
 119
 120 void jz4740_badwidth_write16(void *opaque, target_phys_addr_t addr,
 121                              uint32_t value)
 122 {
 123     uint16_t val16 = value;
 124
 125     JZ4740_16B_REG(addr);
 126     cpu_physical_memory_write(addr, (void *) &val16, 2);
 127 }
 128
 129 uint32_t jz4740_badwidth_read32(void *opaque, target_phys_addr_t addr)
 130 {
 131     uint32_t ret;
 132
 133     JZ4740_32B_REG(addr);
 134     cpu_physical_memory_read(addr, (void *) &ret, 4);
 135     return ret;
 136 }
 137
 138 void jz4740_badwidth_write32(void *opaque, target_phys_addr_t addr,
 139                              uint32_t value)
 140 {
 141     JZ4740_32B_REG(addr);
 142     cpu_physical_memory_write(addr, (void *) &value, 4);
 143 }
 144
 145
 146 /*clock reset and power control*/
 147 struct jz4740_cpm_s
 148 {
 149     target_phys_addr_t base;
 150     struct jz_state_s *soc;
 151
 152     uint32_t cpccr;
 153     uint32_t cppcr;
 154     uint32_t i2scdr;
 155     uint32_t lpcdr;
 156     uint32_t msccdr;
 157     uint32_t uhccdr;
 158     uint32_t uhctst;
 159     uint32_t ssicdr;
 160
 161     uint32_t lcr;
 162     uint32_t clkgr;
 163     uint32_t scr;
 164 };
 165
 166 static void jz4740_dump_clocks(jz_clk parent)
 167 {
 168     jz_clk i = parent;
 169
 170     debug_out(DEBUG_CPM, "clock %s rate %d \n", i->name, i->rate);
 171     for (i = i->child1; i; i = i->sibling)
 172         jz4740_dump_clocks(i);
 173 }
 174
 175 static inline void jz4740_cpccr_update(struct jz4740_cpm_s *s,
 176                                        uint32_t new_value)
 177 {
 178     uint32_t ldiv, mdiv, pdiv, hdiv, cdiv, udiv;
 179     uint32_t div_table[10] = {
 180         1, 2, 3, 4, 6, 8, 12, 16, 24, 32
 181     };
 182
 183     if (unlikely(new_value == s->cpccr))
 184         return;
 185
 186     if (new_value & CPM_CPCCR_PCS)
 187         jz_clk_setrate(jz_findclk(s->soc, "pll_divider"), 1, 1);
 188     else
 189         jz_clk_setrate(jz_findclk(s->soc, "pll_divider"), 2, 1);
 190
 191
 192     ldiv = (new_value & CPM_CPCCR_LDIV_MASK) >> CPM_CPCCR_LDIV_BIT;
 193     ldiv++;
 194
 195     mdiv = div_table[(new_value & CPM_CPCCR_MDIV_MASK) >> CPM_CPCCR_MDIV_BIT];
 196     pdiv = div_table[(new_value & CPM_CPCCR_PDIV_MASK) >> CPM_CPCCR_PDIV_BIT];
 197     hdiv = div_table[(new_value & CPM_CPCCR_HDIV_MASK) >> CPM_CPCCR_HDIV_BIT];
 198     cdiv = div_table[(new_value & CPM_CPCCR_CDIV_MASK) >> CPM_CPCCR_CDIV_BIT];
 199     udiv = div_table[(new_value & CPM_CPCCR_UDIV_MASK) >> CPM_CPCCR_UDIV_BIT];
 200
 201     jz_clk_setrate(jz_findclk(s->soc, "ldclk"), ldiv, 1);
 202     jz_clk_setrate(jz_findclk(s->soc, "mclk"), mdiv, 1);
 203     jz_clk_setrate(jz_findclk(s->soc, "pclk"), pdiv, 1);
 204     jz_clk_setrate(jz_findclk(s->soc, "hclk"), hdiv, 1);
 205     jz_clk_setrate(jz_findclk(s->soc, "cclk"), cdiv, 1);
 206     jz_clk_setrate(jz_findclk(s->soc, "usbclk"), udiv, 1);
 207
 208     if (new_value & CPM_CPCCR_UCS)
 209         jz_clk_reparent(jz_findclk(s->soc, "usbclk"),
 210                         jz_findclk(s->soc, "pll_divider"));
 211     else
 212         jz_clk_reparent(jz_findclk(s->soc, "usbclk"),
 213                         jz_findclk(s->soc, "osc_extal"));
 214
 215     if (new_value & CPM_CPCCR_I2CS)
 216         jz_clk_reparent(jz_findclk(s->soc, "i2sclk"),
 217                         jz_findclk(s->soc, "pll_divider"));
 218     else
 219         jz_clk_reparent(jz_findclk(s->soc, "i2sclk"),
 220                         jz_findclk(s->soc, "osc_extal"));
 221
 222     s->cpccr = new_value;
 223
 224     debug_out(DEBUG_CPM, "write to cpccr 0x%x\n", new_value);
 225
 226     jz4740_dump_clocks(jz_findclk(s->soc, "osc_extal"));
 227
 228 }
 229
 230 static inline void jz4740_cppcr_update(struct jz4740_cpm_s *s,
 231                                        uint32_t new_value)
 232 {
 233     uint32_t pllm, plln, pllod, pllbp, pllen;
 234     uint32_t pll0[4] = {
 235         1, 2, 2, 4
 236     };
 237
 238
 239     pllen = new_value & CPM_CPPCR_PLLEN;
 240     pllbp = new_value & CPM_CPPCR_PLLBP;
 241     if ((!pllen) || (pllen && pllbp))
 242     {
 243         jz_clk_setrate(jz_findclk(s->soc, "pll_output"), 1, 1);
 244         debug_out(DEBUG_CPM, "pll is bypassed \n");
 245         s->cppcr = new_value | CPM_CPPCR_PLLS;
 246         return;
 247     }
 248
 249
 250     pllm = (new_value & CPM_CPPCR_PLLM_MASK) >> CPM_CPPCR_PLLM_BIT;
 251     plln = (new_value & CPM_CPPCR_PLLN_MASK) >> CPM_CPPCR_PLLN_BIT;
 252     pllod = (new_value & CPM_CPPCR_PLLOD_MASK) >> CPM_CPPCR_PLLOD_BIT;
 253     jz_clk_setrate(jz_findclk(s->soc, "pll_output"), (plln + 2) * pll0[pllod],
 254                    pllm + 2);
 255
 256     s->cppcr = new_value;
 257
 258     debug_out(DEBUG_CPM, "write to cppcr 0x%x\n", new_value);
 259     jz4740_dump_clocks(jz_findclk(s->soc, "osc_extal"));
 260
 261 }
 262
 263 static inline void jz4740_i2scdr_update(struct jz4740_cpm_s *s,
 264                                         uint32_t new_value)
 265 {
 266     uint32_t i2scdr;
 267
 268     i2scdr = new_value & CPM_I2SCDR_I2SDIV_MASK;
 269     if (unlikely(i2scdr == s->i2scdr))
 270         return;
 271
 272
 273     jz_clk_setrate(jz_findclk(s->soc, "i2sclk"), i2scdr + 1, 1);
 274
 275     s->i2scdr = i2scdr;
 276
 277     debug_out(DEBUG_CPM, "write to i2scdr 0x%x\n", new_value);
 278     jz4740_dump_clocks(jz_findclk(s->soc, "osc_extal"));
 279
 280 }
 281
 282 static inline void jz4740_lpcdr_update(struct jz4740_cpm_s *s,
 283                                        uint32_t new_value)
 284 {
 285     uint32_t ipcdr;
 286
 287     ipcdr = new_value & CPM_LPCDR_PIXDIV_MASK;
 288     /*TODO: */
 289     s->lpcdr = ipcdr;
 290 }
 291
 292 static inline void jz4740_msccdr_update(struct jz4740_cpm_s *s,
 293                                         uint32_t new_value)
 294 {
 295     uint32_t msccdr;
 296
 297     msccdr = new_value & CPM_MSCCDR_MSCDIV_MASK;
 298
 299     if (unlikely(msccdr == s->msccdr))
 300         return;
 301
 302
 303     jz_clk_setrate(jz_findclk(s->soc, "mscclk"), msccdr + 1, 1);
 304
 305     s->msccdr = msccdr;
 306
 307     debug_out(DEBUG_CPM, "write to msccdr 0x%x\n", new_value);
 308     jz4740_dump_clocks(jz_findclk(s->soc, "osc_extal"));
 309
 310 }
 311
 312 static inline void jz4740_uhccdr_update(struct jz4740_cpm_s *s,
 313                                         uint32_t new_value)
 314 {
 315     uint32_t uhccdr;
 316
 317     uhccdr = new_value & 0xf;
 318     /*TODO: */
 319     s->uhccdr = uhccdr;
 320 }
 321
 322 static void jz4740_cpm_write(void *opaque, target_phys_addr_t addr,
 323                              uint32_t value)
 324 {
 325     struct jz4740_cpm_s *s = (struct jz4740_cpm_s *) opaque;
 326
 327     debug_out(DEBUG_CPM, "write to cpm addr %x value 0x%x\n", addr, value);
 328
 329     switch (addr)
 330     {
 331     case 0x0:
 332         jz4740_cpccr_update(s, value);
 333         break;
 334     case 0x4:
 335         s->lcr = value & 0xff;
 336         break;
 337     case 0x20:
 338         s->clkgr = value & 0xffff;
 339         break;
 340     case 0x24:
 341         s->scr = value & 0xffff;
 342         break;
 343     case 0x10:
 344         jz4740_cppcr_update(s, value);
 345         break;
 346     case 0x60:
 347         jz4740_i2scdr_update(s, value);
 348         break;
 349     case 0x64:
 350         jz4740_lpcdr_update(s, value);
 351         break;
 352     case 0x68:
 353         jz4740_msccdr_update(s, value);
 354         break;
 355     case 0x6c:
 356         jz4740_uhccdr_update(s, value);
 357         break;
 358     case 0x70:
 359         s->uhctst = value & 0x3f;
 360         break;
 361     case 0x74:
 362         s->ssicdr = value & 0xf;
 363         break;
 364     default:
 365         cpu_abort(s->soc->env,
 366                   "jz4740_cpm_write undefined addr " JZ_FMT_plx
 367                   "  value %x \n", addr, value);
 368     }
 369
 370 }
 371
 372
 373 static uint32_t jz474_cpm_read(void *opaque, target_phys_addr_t addr)
 374 {
 375     struct jz4740_cpm_s *s = (struct jz4740_cpm_s *) opaque;
 376
 377     switch (addr)
 378     {
 379     case 0x0:
 380         return s->cpccr;
 381     case 0x4:
 382         return s->lcr;
 383     case 0x20:
 384         return s->clkgr;
 385     case 0x24:
 386         return s->scr;
 387     case 0x10:
 388         return s->cppcr;
 389     case 0x60:
 390         return s->i2scdr;
 391     case 0x64:
 392         return s->lpcdr;
 393     case 0x68:
 394         return s->msccdr;
 395     case 0x6c:
 396         return s->uhccdr;
 397     case 0x70:
 398         return s->uhctst;
 399     case 0x74:
 400         return s->ssicdr;
 401     default:
 402         cpu_abort(s->soc->env,
 403                   "jz474_cpm_read undefined addr " JZ_FMT_plx "  \n", addr);
 404     }
 405
 406 }
 407
 408
 409
 410 static CPUReadMemoryFunc *jz4740_cpm_readfn[] = {
 411     jz4740_badwidth_read32,
 412     jz4740_badwidth_read32,
 413     jz474_cpm_read,
 414 };
 415
 416 static CPUWriteMemoryFunc *jz4740_cpm_writefn[] = {
 417     jz4740_badwidth_write32,
 418     jz4740_badwidth_write32,
 419     jz4740_cpm_write,
 420 };
 421
 422 static void jz4740_cpm_reset(struct jz4740_cpm_s *s)
 423 {
 424     s->cpccr = 0x42040000;
 425     s->cppcr = 0x28080011;
 426     s->i2scdr = 0x00000004;
 427     s->lpcdr = 0x00000004;
 428     s->msccdr = 0x00000004;
 429     s->uhccdr = 0x00000004;
 430     s->uhctst = 0x0;
 431     s->ssicdr = 0x00000004;
 432
 433     s->lcr = 0xf8;
 434     s->clkgr = 0x0;
 435     s->scr = 0x1500;
 436 }
 437
 438 static struct jz4740_cpm_s *jz4740_cpm_init(struct jz_state_s *soc)
 439 {
 440     int iomemtype;
 441     struct jz4740_cpm_s *s = (struct jz4740_cpm_s *) qemu_mallocz(sizeof(*s));
 442     s->base = JZ4740_PHYS_BASE(JZ4740_CPM_BASE);
 443     s->soc = soc;
 444
 445     jz4740_cpm_reset(s);
 446
 447     iomemtype =
 448         cpu_register_io_memory(0, jz4740_cpm_readfn, jz4740_cpm_writefn, s);
 449     cpu_register_physical_memory(s->base, 0x00001000, iomemtype);
 450     return s;
 451 }
 452
 453
 454 /* JZ4740 interrupt controller
 455   * It issues INT2 to MIPS
 456   */
 457 struct jz4740_intc_s
 458 {
 459     qemu_irq parent_irq;
 460
 461     target_phys_addr_t base;
 462     struct jz_state_s *soc;
 463
 464     uint32_t icsr;
 465     uint32_t icmr;
 466     uint32_t icmsr;
 467     uint32_t icmcr;
 468     uint32_t icpr;
 469 };
 470
 471 static uint32_t jz4740_intc_read(void *opaque, target_phys_addr_t addr)
 472 {
 473     struct jz4740_intc_s *s = (struct jz4740_intc_s *) opaque;
 474
 475     switch (addr)
 476     {
 477     case 0x8:
 478     case 0xc:
 479         JZ4740_WO_REG(addr);
 480         break;
 481     case 0x0:
 482         return s->icsr;
 483     case 0x4:
 484         return s->icmr;
 485     case 0x10:
 486         return s->icpr;
 487     default:
 488         cpu_abort(s->soc->env,
 489                   "jz4740_intc_read undefined addr " JZ_FMT_plx "  \n", addr);
 490
 491     }
 492     return (0);
 493 }
 494
 495 static void jz4740_intc_write(void *opaque, target_phys_addr_t addr,
 496                               uint32_t value)
 497 {
 498     struct jz4740_intc_s *s = (struct jz4740_intc_s *) opaque;
 499
 500     switch (addr)
 501     {
 502     case 0x0:
 503         JZ4740_RO_REG(addr);
 504         break;
 505     case 0x4:
 506         s->icmr = value;
 507         break;
 508     case 0x8:
 509         s->icmr |= value;
 510         break;
 511     case 0xc:
 512         s->icmr &= ~value;
 513         break;
 514     case 0x10:
 515         s->icpr &= ~value;
 516         qemu_set_irq(s->parent_irq, 0);
 517         break;
 518     default:
 519         cpu_abort(s->soc->env,
 520                   "jz4740_intc_write undefined addr " JZ_FMT_plx
 521                   "  value %x \n", addr, value);
 522     }
 523 }
 524
 525
 526 static CPUReadMemoryFunc *jz4740_intc_readfn[] = {
 527     jz4740_badwidth_read32,
 528     jz4740_badwidth_read32,
 529     jz4740_intc_read,
 530 };
 531
 532 static CPUWriteMemoryFunc *jz4740_intc_writefn[] = {
 533     jz4740_badwidth_write32,
 534     jz4740_badwidth_write32,
 535     jz4740_intc_write,
 536 };
 537
 538 static void jz4740_intc_reset(struct jz4740_intc_s *s)
 539 {
 540     s->icsr = 0x0;
 541     s->icmr = 0xffffffff;
 542     s->icpr = 0x0;
 543 }
 544
 545 static void jz4740_set_irq(void *opaque, int irq, int level)
 546 {
 547     struct jz4740_intc_s *s = (struct jz4740_intc_s *) opaque;
 548     uint32_t irq_mask = 1 << irq;
 549
 550
 551     if (level)
 552     {
 553         s->icsr |= irq_mask;
 554         s->icpr &= ~irq_mask;
 555         if (!(s->icmr & irq_mask))
 556         {
 557             s->icpr |= irq_mask;
 558             qemu_set_irq(s->parent_irq, 1);
 559         }
 560     }
 561
 562 }
 563
 564 static qemu_irq *jz4740_intc_init(struct jz_state_s *soc, qemu_irq parent_irq)
 565 {
 566     int iomemtype;
 567     struct jz4740_intc_s *s = (struct jz4740_intc_s *) qemu_mallocz(sizeof(*s));
 568     s->base = JZ4740_PHYS_BASE(JZ4740_INTC_BASE);
 569     s->parent_irq = parent_irq;
 570     s->soc = soc;
 571
 572     jz4740_intc_reset(s);
 573
 574     iomemtype =
 575         cpu_register_io_memory(0, jz4740_intc_readfn, jz4740_intc_writefn, s);
 576     cpu_register_physical_memory(s->base, 0x00001000, iomemtype);
 577     return qemu_allocate_irqs(jz4740_set_irq, s, 32);
 578 }
 579
 580 /*external memory controller*/
 581 struct jz4740_emc_s
 582 {
 583     qemu_irq irq;
 584     target_phys_addr_t base;
 585     struct jz_state_s *soc;
 586
 587     uint32_t bcr;
 588     uint32_t smcr1;             /*0x13010014 */
 589     uint32_t smcr2;             /*0x13010018 */
 590     uint32_t smcr3;             /*0x1301001c */
 591     uint32_t smcr4;             /*0x13010020 */
 592     uint32_t sacr1;             /*0x13010034 */
 593     uint32_t sacr2;             /*0x13010038 */
 594     uint32_t sacr3;             /*0x1301003c */
 595     uint32_t sacr4;             /*0x13010040 */
 596
 597     uint32_t nfcsr;             /*0x13010050 */
 598     uint32_t nfeccr;            /*0x13010100 */
 599     uint32_t nfecc;             /*0x13010104 */
 600     uint32_t nfpar0;            /*0x13010108 */
 601     uint32_t nfpar1;            /*0x1301010c */
 602     uint32_t nfpar2;            /*0x13010110 */
 603     uint32_t nfints;            /*0x13010114 */
 604     uint32_t nfinte;            /*0x13010118 */
 605     uint32_t nferr0;            /*0x1301011c */
 606     uint32_t nferr1;            /*0x13010120 */
 607     uint32_t nferr2;            /*0x13010124 */
 608     uint32_t nferr3;            /*0x13010128 */
 609
 610     uint32_t dmcr;              /*0x13010080 */
 611     uint32_t rtcsr;             /*0x13010084 */
 612     uint32_t rtcnt;             /*0x13010088 */
 613     uint32_t rtcor;             /*0x1301008c */
 614     uint32_t dmar;              /*0x13010090 */
 615     uint32_t sdmr;              /*0x1301a000 */
 616
 617 };
 618
 619
 620 static void jz4740_emc_reset(struct jz4740_emc_s *s)
 621 {
 622     s->smcr1 = 0xfff7700;
 623     s->smcr2 = 0xfff7700;
 624     s->smcr3 = 0xfff7700;
 625     s->smcr4 = 0xfff7700;
 626     s->sacr1 = 0x18fc;
 627     s->sacr2 = 0x16fe;
 628     s->sacr3 = 0x14fe;
 629     s->sacr4 = 0xcfc;
 630
 631     s->nfcsr = 0x0;
 632     s->nfeccr = 0x0;
 633     s->nfecc = 0x0;
 634     s->nfpar0 = 0x0;
 635     s->nfpar1 = 0x0;
 636     s->nfpar2 = 0x0;
 637     s->nfints = 0x0;
 638     s->nfinte = 0x0;
 639     s->nferr0 = 0x0;
 640     s->nferr1 = 0x0;
 641     s->nferr2 = 0x0;
 642     s->nferr3 = 0x0;
 643
 644     s->dmcr = 0x0;
 645     s->rtcsr = 0x0;
 646     s->rtcnt = 0x0;
 647     s->rtcor = 0x0;
 648     s->dmar = 0x20f8;
 649     s->sdmr = 0x0;
 650
 651 }
 652
 653 static uint32_t jz4740_emc_read8(void *opaque, target_phys_addr_t addr)
 654 {
 655     struct jz4740_emc_s *s = (struct jz4740_emc_s *) opaque;
 656
 657     switch (addr)
 658     {
 659     case 0x108:
 660     case 0x109:
 661     case 0x10a:
 662     case 0x10b:
 663         return (s->nfpar0 >> ((addr - 0x108) * 8)) & 0xff;
 664     case 0x10c:
 665     case 0x10d:
 666     case 0x10e:
 667     case 0x10f:
 668         return (s->nfpar1 >> ((addr - 0x10c) * 8)) & 0xff;
 669     case 0x110:
 670     case 0x111:
 671     case 0x112:
 672     case 0x113:
 673         return (s->nfpar2 >> ((addr - 0x110) * 8)) & 0xff;
 674     case 0xa000:
 675     case 0xa001:
 676     case 0xa002:
 677     case 0xa003:
 678         return (s->sdmr >> ((addr - 0xa000) * 8)) & 0xff;
 679     default:
 680         cpu_abort(s->soc->env,
 681                   "jz4740_emc_read8 undefined addr " JZ_FMT_plx " \n", addr);
 682
 683
 684     }
 685     return (0);
 686 }
 687
 688 static uint32_t jz4740_emc_read16(void *opaque, target_phys_addr_t addr)
 689 {
 690     struct jz4740_emc_s *s = (struct jz4740_emc_s *) opaque;
 691
 692     switch (addr)
 693     {
 694     case 0x108:
 695     case 0x10a:
 696         return (s->nfpar0 >> ((addr - 0x108) * 8)) & 0xffff;
 697     case 0x10c:
 698     case 0x10e:
 699         return (s->nfpar1 >> ((addr - 0x10c) * 8)) & 0xffff;
 700     case 0x110:
 701     case 0x112:
 702         return (s->nfpar2 >> ((addr - 0x110) * 8)) & 0xffff;
 703     case 0x11c:
 704     case 0x11e:
 705         return (s->nferr0 >> ((addr - 0x11c) * 8)) & 0xffff;
 706     case 0x120:
 707     case 0x122:
 708         return (s->nferr1 >> ((addr - 0x120) * 8)) & 0xffff;
 709     case 0x124:
 710     case 0x126:
 711         return (s->nferr2 >> ((addr - 0x124) * 8)) & 0xffff;
 712     case 0x128:
 713     case 0x12a:
 714         return (s->nferr3 >> ((addr - 0x128) * 8)) & 0xffff;
 715     default:
 716         cpu_abort(s->soc->env,
 717                   "jz4740_emc_read16 undefined addr " JZ_FMT_plx " \n", addr);
 718     }
 719     return (0);
 720 }
 721
 722 static uint32_t jz4740_emc_read32(void *opaque, target_phys_addr_t addr)
 723 {
 724     struct jz4740_emc_s *s = (struct jz4740_emc_s *) opaque;
 725
 726     switch (addr)
 727     {
 728     case 0x0:
 729         return s->bcr;
 730     case 0x14:
 731         return s->smcr1;
 732     case 0x18:
 733         return s->smcr2;
 734     case 0x1c:
 735         return s->smcr3;
 736     case 0x20:
 737         return s->smcr4;
 738     case 0x34:
 739         return s->sacr1;
 740     case 0x38:
 741         return s->sacr2;
 742     case 0x3c:
 743         return s->sacr3;
 744     case 0x40:
 745         return s->sacr4;
 746     case 0x50:
 747         return s->nfcsr;
 748     case 0x100:
 749         return s->nfeccr;
 750     case 0x104:
 751         return s->nfecc;
 752     case 0x108:
 753         return s->nfpar0;
 754     case 0x10c:
 755         return s->nfpar1;
 756     case 0x110:
 757         return s->nfpar2;
 758     case 0x114:
 759         return s->nfints;
 760     case 0x118:
 761         return s->nfinte;
 762     case 0x11c:
 763         return s->nferr0;
 764     case 0x120:
 765         return s->nferr1;
 766     case 0x124:
 767         return s->nferr2;
 768     case 0x128:
 769         return s->nferr3;
 770     case 0x80:
 771         return s->dmcr;
 772     case 0x90:
 773         return s->dmar;
 774     default:
 775         cpu_abort(s->soc->env,
 776                   "jz4740_emc_read32 undefined addr " JZ_FMT_plx " \n", addr);
 777     }
 778     return (0);
 779 }
 780
 781 static void jz4740_emc_write8(void *opaque, target_phys_addr_t addr,
 782                               uint32_t value)
 783 {
 784     struct jz4740_emc_s *s = (struct jz4740_emc_s *) opaque;
 785
 786     debug_out(DEBUG_EMC, "jz4740_emc_write8 addr %x value %x\n", addr, value);
 787
 788     switch (addr)
 789     {
 790     case 0x108:
 791     case 0x109:
 792     case 0x10a:
 793     case 0x10b:
 794         s->nfpar0 |= (value & 0xff) << ((addr - 0x108) * 8);
 795         break;
 796     case 0x10c:
 797     case 0x10d:
 798     case 0x10e:
 799     case 0x10f:
 800         s->nfpar1 |= (value & 0xff) << ((addr - 0x10c) * 8);
 801         break;
 802     case 0x110:
 803     case 0x111:
 804     case 0x112:
 805     case 0x113:
 806         s->nfpar2 |= (value & 0xff) << ((addr - 0x110) * 8);
 807         break;
 808     case 0xa000 ... 0xa3ff:
 809         break;
 810     default:
 811         cpu_abort(s->soc->env,
 812                   "jz4740_emc_write8 undefined addr " JZ_FMT_plx
 813                   "  value %x \n", addr, value);
 814     }
 815 }
 816 static void jz4740_emc_write16(void *opaque, target_phys_addr_t addr,
 817                                uint32_t value)
 818 {
 819     struct jz4740_emc_s *s = (struct jz4740_emc_s *) opaque;
 820
 821     debug_out(DEBUG_EMC, "jz4740_emc_write16 addr %x value %x\n", addr, value);
 822     switch (addr)
 823     {
 824     case 0x108:
 825     case 0x10a:
 826         s->nfpar0 |= (value & 0xffff) << ((addr - 0x108) * 8);
 827         break;
 828     case 0x10c:
 829     case 0x10e:
 830         s->nfpar1 |= (value & 0xffff) << ((addr - 0x10c) * 8);
 831         break;
 832     case 0x110:
 833     case 0x112:
 834         s->nfpar2 |= (value & 0xffff) << ((addr - 0x110) * 8);
 835         break;
 836     case 0x84:
 837     case 0x86:
 838         s->rtcsr |= (value & 0xffff) << ((addr - 0x84) * 8);
 839         break;
 840     case 0x88:
 841     case 0x8a:
 842         s->rtcnt |= (value & 0xffff) << ((addr - 0x88) * 8);
 843         break;
 844     case 0x8c:
 845         s->rtcor |= (value & 0xffff) << ((addr - 0x8c) * 8);
 846         break;
 847     default:
 848         cpu_abort(s->soc->env,
 849                   "jz4740_emc_write16 undefined addr " JZ_FMT_plx
 850                   "  value %x \n", addr, value);
 851     }
 852 }
 853
 854 static void jz4740_emc_upate_interrupt(struct jz4740_emc_s *s)
 855 {
 856     qemu_set_irq(s->irq, s->nfints & s->nfinte);
 857 }
 858
 859 static void jz4740_emc_write32(void *opaque, target_phys_addr_t addr,
 860                                uint32_t value)
 861 {
 862     struct jz4740_emc_s *s = (struct jz4740_emc_s *) opaque;
 863
 864     debug_out(DEBUG_EMC, "jz4740_emc_write32 addr %x value %x\n", addr, value);
 865     switch (addr)
 866     {
 867     case 0x104:
 868     case 0x11c:
 869     case 0x120:
 870     case 0x124:
 871     case 0x128:
 872         JZ4740_RO_REG(addr);
 873         break;
 874     case 0x0:
 875         s->bcr = value;
 876         break;
 877     case 0x14:
 878         s->smcr1 = value & 0xfff77cf;
 879         break;
 880     case 0x18:
 881         s->smcr2 = value & 0xfff77cf;
 882         break;
 883     case 0x1c:
 884         s->smcr3 = value & 0xfff77cf;
 885         break;
 886     case 0x20:
 887         s->smcr4 = value & 0xfff77cf;
 888         break;
 889     case 0x34:
 890         s->sacr1 = value & 0xffff;
 891         break;
 892     case 0x38:
 893         s->sacr2 = value & 0xffff;
 894         break;
 895     case 0x3c:
 896         s->sacr3 = value & 0xffff;
 897         break;
 898     case 0x40:
 899         s->sacr4 = value & 0xffff;
 900         break;
 901     case 0x50:
 902         s->nfcsr = value & 0xffff;
 903         break;
 904     case 0x100:
 905         s->nfeccr = value & 0x1f;
 906         if (s->nfeccr & 0x2)
 907         {
 908             s->nfecc = 0x0;
 909             s->nfpar0 = 0x0;
 910             s->nfpar1 = 0x0;
 911             s->nfpar2 = 0x0;
 912             s->nfints = 0x0;
 913             s->nfinte = 0x0;
 914             s->nferr0 = 0x0;
 915             s->nferr1 = 0x0;
 916             s->nferr2 = 0x0;
 917             s->nferr3 = 0x0;
 918         }
 919          /*RS*/
 920             /*TODO: Real RS error correction */
 921             if (s->nfeccr & 0x4)
 922         {
 923             if ((s->nfeccr & 0x10) && (!(s->nfeccr & 0x8)))
 924             {
 925                 /*decode */
 926                 s->nfints = 0x8;
 927                 s->nferr0 = 0x0;
 928                 s->nferr1 = 0x0;
 929                 s->nferr2 = 0x0;
 930             }
 931             if (s->nfeccr & 0x8)
 932             {
 933                 /*encoding */
 934                 s->nfints = 0x4;
 935                 s->nfpar0 = 0xffffffff; /*fake value. for debug */
 936                 s->nfpar1 = 0xffffffff; /*fake value */
 937                 s->nfpar2 = 0xff;       /*fake value */
 938             }
 939         }
 940         else
 941         {
 942             s->nfecc = 0xffffff;
 943         }
 944         jz4740_emc_upate_interrupt(s);
 945         break;
 946     case 0x108:
 947         s->nfpar0 = value;
 948         break;
 949     case 0x10c:
 950         s->nfpar1 = value;
 951         break;
 952     case 0x110:
 953         s->nfpar2 = value & 0xff;
 954         break;
 955     case 0x114:
 956         s->nfints = value & 0x1fffffff;
 957         jz4740_emc_upate_interrupt(s);
 958         break;
 959     case 0x118:
 960         s->nfinte = value & 0x1f;
 961         jz4740_emc_upate_interrupt(s);
 962         break;
 963     case 0x080:
 964         s->dmcr = value & 0x9fbeff7f;
 965         break;
 966     case 0x90:
 967         s->dmar = value & 0xffff;
 968         break;
 969     default:
 970         cpu_abort(s->soc->env,
 971                   "jz4740_emc_write32 undefined addr " JZ_FMT_plx
 972                   "  value %x \n", addr, value);
 973
 974     }
 975
 976 }
 977
 978 static CPUReadMemoryFunc *jz4740_emc_readfn[] = {
 979     jz4740_emc_read8,
 980     jz4740_emc_read16,
 981     jz4740_emc_read32,
 982 };
 983
 984 static CPUWriteMemoryFunc *jz4740_emc_writefn[] = {
 985     jz4740_emc_write8,
 986     jz4740_emc_write16,
 987     jz4740_emc_write32,
 988 };
 989
 990
 991 static struct jz4740_emc_s *jz4740_emc_init(struct jz_state_s *soc,
 992                                             qemu_irq irq)
 993 {
 994     int iomemtype;
 995     struct jz4740_emc_s *s = (struct jz4740_emc_s *) qemu_mallocz(sizeof(*s));
 996     s->base = JZ4740_PHYS_BASE(JZ4740_EMC_BASE);
 997     s->soc = soc;
 998     s->irq = irq;
 999
1000     jz4740_emc_reset(s);
1001
1002     iomemtype =
1003         cpu_register_io_memory(0, jz4740_emc_readfn, jz4740_emc_writefn, s);
1004     cpu_register_physical_memory(s->base, 0x00010000, iomemtype);
1005     return s;
1006
1007 }
1008
1009 struct jz4740_gpio_s
1010 {
1011     qemu_irq irq;
1012     target_phys_addr_t base;
1013     struct jz_state_s *soc;
1014
1015     uint32_t papin[4];
1016     uint32_t padat[4];
1017     uint32_t paim[4];
1018     uint32_t pape[4];
1019     uint32_t pafun[4];
1020     uint32_t pasel[4];
1021     uint32_t padir[4];
1022     uint32_t patrg[4];
1023     uint32_t paflg[4];
1024 };
1025
1026 static void jz4740_gpio_reset(struct jz4740_gpio_s *s)
1027 {
1028     memset(s->papin, 0x0, sizeof(s->papin));
1029     memset(s->padat, 0x0, sizeof(s->padat));
1030     memset(s->paim, 0xffffffff, sizeof(s->paim));
1031     memset(s->pape, 0x0, sizeof(s->pape));
1032     memset(s->pafun, 0x0, sizeof(s->pafun));
1033     memset(s->pasel, 0x0, sizeof(s->pasel));
1034     memset(s->padir, 0x0, sizeof(s->padir));
1035     memset(s->patrg, 0x0, sizeof(s->patrg));
1036     memset(s->paflg, 0x0, sizeof(s->paflg));
1037 }
1038
1039 static uint32_t jz4740_gpio_read(void *opaque, target_phys_addr_t addr)
1040 {
1041     struct jz4740_gpio_s *s = (struct jz4740_gpio_s *) opaque;
1042     uint32_t group;
1043     debug_out(DEBUG_GPIO, "jz4740_gpio_read addr %x\n", addr);
1044
1045     switch (addr)
1046     {
1047     case 0x14:
1048     case 0x114:
1049     case 0x214:
1050     case 0x314:
1051     case 0x18:
1052     case 0x118:
1053     case 0x218:
1054     case 0x318:
1055     case 0x24:
1056     case 0x124:
1057     case 0x224:
1058     case 0x324:
1059     case 0x28:
1060     case 0x128:
1061     case 0x228:
1062     case 0x328:
1063     case 0x34:
1064     case 0x134:
1065     case 0x234:
1066     case 0x334:
1067     case 0x38:
1068     case 0x138:
1069     case 0x238:
1070     case 0x338:
1071     case 0x44:
1072     case 0x144:
1073     case 0x244:
1074     case 0x344:
1075     case 0x48:
1076     case 0x148:
1077     case 0x248:
1078     case 0x348:
1079     case 0x54:
1080     case 0x154:
1081     case 0x254:
1082     case 0x354:
1083     case 0x58:
1084     case 0x158:
1085     case 0x258:
1086     case 0x358:
1087     case 0x64:
1088     case 0x164:
1089     case 0x264:
1090     case 0x364:
1091     case 0x68:
1092     case 0x168:
1093     case 0x268:
1094     case 0x368:
1095     case 0x74:
1096     case 0x174:
1097     case 0x274:
1098     case 0x374:
1099     case 0x78:
1100     case 0x178:
1101     case 0x278:
1102     case 0x378:
1103     case 0x84:
1104     case 0x184:
1105     case 0x284:
1106     case 0x384:
1107         JZ4740_WO_REG(addr);
1108         break;
1109
1110     case 0x0:
1111     case 0x100:
1112     case 0x200:
1113     case 0x300:
1114         group = (addr - 0x0) / 0x100;
1115         if (addr == 0x200)
1116         {
1117             /*GPIO(C) PIN 30  -> NAND FLASH R/B. */
1118             /*FOR NAND FLASH.PIN 30 ----|_____|------ */
1119             s->papin[2] &= 0x40000000;
1120             if (s->papin[2])
1121                 s->papin[2] &= ~0x40000000;
1122             else
1123                 s->papin[2] |= 0x40000000;
1124         }
1125         return s->papin[group];
1126     case 0x10:
1127     case 0x110:
1128     case 0x210:
1129     case 0x310:
1130         group = (addr - 0x10) / 0x100;
1131         return s->padat[group];
1132     case 0x20:
1133     case 0x120:
1134     case 0x220:
1135     case 0x320:
1136         group = (addr - 0x20) / 0x100;
1137         return s->paim[group];
1138     case 0x30:
1139     case 0x130:
1140     case 0x230:
1141     case 0x330:
1142         group = (addr - 0x30) / 0x100;
1143         return s->pape[group];
1144     case 0x40:
1145     case 0x140:
1146     case 0x240:
1147     case 0x340:
1148         group = (addr - 0x40) / 0x100;
1149         return s->pafun[group];
1150     case 0x50:
1151     case 0x150:
1152     case 0x250:
1153     case 0x350:
1154         group = (addr - 0x50) / 0x100;
1155         return s->pasel[group];
1156     case 0x60:
1157     case 0x160:
1158     case 0x260:
1159     case 0x360:
1160         group = (addr - 0x60) / 0x100;
1161         return s->padir[group];
1162     case 0x70:
1163     case 0x170:
1164     case 0x270:
1165     case 0x370:
1166         group = (addr - 0x70) / 0x100;
1167         return s->patrg[group];
1168     case 0x80:
1169     case 0x180:
1170     case 0x280:
1171     case 0x380:
1172         group = (addr - 0x80) / 0x100;
1173         return s->paflg[group];
1174     default:
1175         cpu_abort(s->soc->env,
1176                   "jz4740_gpio_read undefined addr " JZ_FMT_plx " \n", addr);
1177     }
1178     return (0);
1179 }
1180
1181 static void jz4740_gpio_write(void *opaque, target_phys_addr_t addr,
1182                               uint32_t value)
1183 {
1184     struct jz4740_gpio_s *s = (struct jz4740_gpio_s *) opaque;
1185     uint32_t group;
1186
1187     debug_out(DEBUG_GPIO, "jz4740_gpio_write addr %x value %x\n", addr, value);
1188
1189     switch (addr)
1190     {
1191     case 0x0:
1192     case 0x100:
1193     case 0x200:
1194     case 0x300:
1195     case 0x10:
1196     case 0x110:
1197     case 0x210:
1198     case 0x310:
1199     case 0x20:
1200     case 0x120:
1201     case 0x220:
1202     case 0x320:
1203     case 0x30:
1204     case 0x130:
1205     case 0x230:
1206     case 0x330:
1207     case 0x40:
1208     case 0x140:
1209     case 0x240:
1210     case 0x340:
1211     case 0x50:
1212     case 0x150:
1213     case 0x250:
1214     case 0x350:
1215     case 0x60:
1216     case 0x160:
1217     case 0x260:
1218     case 0x360:
1219     case 0x70:
1220     case 0x170:
1221     case 0x270:
1222     case 0x370:
1223     case 0x80:
1224     case 0x180:
1225     case 0x280:
1226     case 0x380:
1227         JZ4740_RO_REG(addr);
1228         break;
1229     case 0x14:
1230     case 0x114:
1231     case 0x214:
1232     case 0x314:
1233         group = (addr - 0x14) / 0x100;
1234         s->padat[group] = value;
1235         break;
1236     case 0x18:
1237     case 0x118:
1238     case 0x218:
1239     case 0x318:
1240         group = (addr - 0x18) / 0x100;
1241         s->padat[group] &= ~value;
1242         break;
1243     case 0x24:
1244     case 0x124:
1245     case 0x224:
1246     case 0x324:
1247         group = (addr - 0x24) / 0x100;
1248         s->paim[group] = value;
1249         break;
1250     case 0x28:
1251     case 0x128:
1252     case 0x228:
1253     case 0x328:
1254         group = (addr - 0x28) / 0x100;
1255         s->paim[group] &= ~value;
1256         break;
1257     case 0x34:
1258     case 0x134:
1259     case 0x234:
1260     case 0x334:
1261         group = (addr - 0x34) / 0x100;
1262         s->pape[group] = value;
1263         break;
1264     case 0x38:
1265     case 0x138:
1266     case 0x238:
1267     case 0x338:
1268         group = (addr - 0x38) / 0x100;
1269         s->pape[group] &= ~value;
1270         break;
1271     case 0x44:
1272     case 0x144:
1273     case 0x244:
1274     case 0x344:
1275         group = (addr - 0x44) / 0x100;
1276         s->pafun[group] = value;
1277         break;
1278     case 0x48:
1279     case 0x148:
1280     case 0x248:
1281     case 0x348:
1282         group = (addr - 0x48) / 0x100;
1283         s->pafun[group] &= ~value;
1284         break;
1285     case 0x54:
1286     case 0x154:
1287     case 0x254:
1288     case 0x354:
1289         group = (addr - 0x54) / 0x100;
1290         s->pasel[group] = value;
1291         break;
1292     case 0x58:
1293     case 0x158:
1294     case 0x258:
1295     case 0x358:
1296         group = (addr - 0x58) / 0x100;
1297         s->pasel[group] &= ~value;
1298         break;
1299     case 0x64:
1300     case 0x164:
1301     case 0x264:
1302     case 0x364:
1303         group = (addr - 0x64) / 0x100;
1304         s->padir[group] = value;
1305         break;
1306     case 0x68:
1307     case 0x168:
1308     case 0x268:
1309     case 0x368:
1310         group = (addr - 0x68) / 0x100;
1311         s->padir[group] &= ~value;
1312         break;
1313     case 0x74:
1314     case 0x174:
1315     case 0x274:
1316     case 0x374:
1317         group = (addr - 0x74) / 0x100;
1318         s->patrg[group] = value;
1319         break;
1320     case 0x78:
1321     case 0x178:
1322     case 0x278:
1323     case 0x378:
1324         group = (addr - 0x78) / 0x100;
1325         s->patrg[group] &= ~value;
1326         break;
1327     case 0x84:
1328     case 0x184:
1329     case 0x284:
1330     case 0x384:
1331         group = (addr - 0x74) / 0x100;
1332         s->paflg[group] &= ~value;
1333         break;
1334     default:
1335         cpu_abort(s->soc->env,
1336                   "jz4740_gpio_write undefined addr " JZ_FMT_plx
1337                   "  value %x \n", addr, value);
1338
1339     }
1340
1341
1342 }
1343
1344
1345 static CPUReadMemoryFunc *jz4740_gpio_readfn[] = {
1346     jz4740_badwidth_read32,
1347     jz4740_badwidth_read32,
1348     jz4740_gpio_read,
1349 };
1350
1351 static CPUWriteMemoryFunc *jz4740_gpio_writefn[] = {
1352     jz4740_badwidth_write32,
1353     jz4740_badwidth_write32,
1354     jz4740_gpio_write,
1355 };
1356
1357 static struct jz4740_gpio_s *jz4740_gpio_init(struct jz_state_s *soc,
1358                                               qemu_irq irq)
1359 {
1360     int iomemtype;
1361     struct jz4740_gpio_s *s = (struct jz4740_gpio_s *) qemu_mallocz(sizeof(*s));
1362     s->base = JZ4740_PHYS_BASE(JZ4740_GPIO_BASE);
1363     s->soc = soc;
1364     s->irq = irq;
1365
1366     jz4740_gpio_reset(s);
1367
1368     iomemtype =
1369         cpu_register_io_memory(0, jz4740_gpio_readfn, jz4740_gpio_writefn, s);
1370     cpu_register_physical_memory(s->base, 0x00010000, iomemtype);
1371     return s;
1372
1373 }
1374
1375 struct jz4740_rtc_s
1376 {
1377     qemu_irq irq;
1378     target_phys_addr_t base;
1379     struct jz_state_s *soc;
1380
1381     QEMUTimer *hz_tm;
1382     //struct tm tm;
1383     //int sec_offset;
1384     int64_t next;
1385
1386     uint32_t rtccr;
1387     uint32_t rtcsr;
1388     uint32_t rtcsar;
1389     uint32_t rtcgr;
1390
1391     uint32_t hcr;
1392     uint32_t hwfcr;
1393     uint32_t hrcr;
1394     uint32_t hwcr;
1395     uint32_t hwrsr;
1396     uint32_t hspr;
1397
1398 };
1399
1400
1401 static void jz4740_rtc_update_interrupt(struct jz4740_rtc_s *s)
1402 {
1403    /* if (((s->rtcsr & 0x40) && (s->rtcsr & 0x20))
1404         || ((s->rtcsr & 0x10) && (s->rtcsr & 0x8)))
1405         qemu_set_irq(s->irq, 1);*/
1406     //else
1407     //    qemu_set_irq(s->irq, 0);
1408 }
1409
1410 static inline void jz4740_rtc_start(struct jz4740_rtc_s *s)
1411 {
1412     s->next = +qemu_get_clock(rt_clock);
1413     qemu_mod_timer(s->hz_tm, s->next);
1414 }
1415
1416 static inline void jz4740_rtc_stop(struct jz4740_rtc_s *s)
1417 {
1418     qemu_del_timer(s->hz_tm);
1419     s->next = -qemu_get_clock(rt_clock);
1420     if (s->next < 1)
1421         s->next = 1;
1422 }
1423
1424 static void jz4740_rtc_hz(void *opaque)
1425 {
1426     struct jz4740_rtc_s *s = (struct jz4740_rtc_s *) opaque;
1427
1428     s->next += 1000;
1429     qemu_mod_timer(s->hz_tm, s->next);
1430     if (s->rtccr & 0x1)
1431     {
1432         s->rtcsr++;
1433         s->rtccr |= 0x40;
1434         if (s->rtcsr & 0x4)
1435         {
1436             if (s->rtcsr == s->rtcsar)
1437                 s->rtccr |= 0x10;
1438         }
1439         jz4740_rtc_update_interrupt(s);
1440     }
1441 }
1442
1443 static void jz4740_rtc_reset(struct jz4740_rtc_s *s)
1444 {
1445     s->rtccr = 0x81;
1446
1447     s->next = 1000;
1448
1449     /*Maybe rtcsr need to be saved to file */
1450     s->rtcsr = 0;
1451     //s->sec_offset = 0;
1452     //qemu_get_timedate(&s->tm, s->sec_offset);
1453     jz4740_rtc_start(s);
1454
1455 }
1456
1457 static uint32_t jz4740_rtc_read(void *opaque, target_phys_addr_t addr)
1458 {
1459     struct jz4740_rtc_s *s = (struct jz4740_rtc_s *) opaque;
1460
1461     debug_out(DEBUG_RTC, "jz4740_rtc_read addr %x\n", addr);
1462     switch (addr)
1463     {
1464     case 0x0:
1465         return s->rtccr | 0x80;
1466     case 0x4:
1467         return s->rtcsr;
1468     case 0x8:
1469         return s->rtcsar;
1470     case 0xc:
1471         return s->rtcgr;
1472     case 0x20:
1473         return s->hcr;
1474     case 0x24:
1475         return s->hwfcr;
1476     case 0x28:
1477         return s->hrcr;
1478     case 0x2c:
1479         return s->hwcr;
1480     case 0x30:
1481         return s->hwrsr;
1482     case 0x34:
1483         return s->hspr;
1484     default:
1485         cpu_abort(s->soc->env,
1486                   "jz4740_rtc_read undefined addr " JZ_FMT_plx "\n", addr);
1487     }
1488
1489     return (0);
1490 }
1491
1492 static void jz4740_rtc_write(void *opaque, target_phys_addr_t addr,
1493                              uint32_t value)
1494 {
1495     struct jz4740_rtc_s *s = (struct jz4740_rtc_s *) opaque;
1496
1497     debug_out(DEBUG_RTC, "jz4740_rtc_write addr %x value %x\n", addr, value);
1498
1499     switch (addr)
1500     {
1501     case 0x0:
1502         s->rtccr = value & 0x2d;
1503         if (!value & 0x40)
1504             s->rtccr &= ~0x40;
1505         if (!value & 0x10)
1506             s->rtccr &= ~0x10;
1507         if (s->rtccr & 0x1)
1508         {
1509             //jz4740_rtc_start(s);
1510             jz4740_rtc_update_interrupt(s);
1511         }
1512         else
1513                 jz4740_rtc_stop(s);
1514         break;
1515     case 0x4:
1516         s->rtcsr = value;
1517         //s->sec_offset = qemu_timedate_diff(&s->tm);
1518         break;
1519     case 0x8:
1520         s->rtcsar = value;
1521         break;
1522     case 0xc:
1523         s->rtcgr = value & 0x13ffffff;
1524         break;
1525     case 0x20:
1526         s->hcr = value & 0x1;
1527         break;
1528     case 0x24:
1529         s->hwfcr = value & 0xffe0;
1530         break;
1531     case 0x28:
1532         s->hrcr = value & 0xfe0;
1533         break;
1534     case 0x2c:
1535         s->hwcr = value & 0x1;
1536         break;
1537     case 0x30:
1538         s->hwrsr = value & 0x33;
1539         break;
1540     case 0x34:
1541         s->hspr = value;
1542         break;
1543     default:
1544         cpu_abort(s->soc->env,
1545                   "jz4740_rtc_write undefined addr " JZ_FMT_plx
1546                   "  value %x \n", addr, value);
1547     }
1548
1549 }
1550
1551 static CPUReadMemoryFunc *jz4740_rtc_readfn[] = {
1552     jz4740_badwidth_read32,
1553     jz4740_badwidth_read32,
1554     jz4740_rtc_read,
1555 };
1556
1557 static CPUWriteMemoryFunc *jz4740_rtc_writefn[] = {
1558     jz4740_badwidth_write32,
1559     jz4740_badwidth_write32,
1560     jz4740_rtc_write,
1561 };
1562
1563 static struct jz4740_rtc_s *jz4740_rtc_init(struct jz_state_s *soc,
1564                                             qemu_irq irq)
1565 {
1566     int iomemtype;
1567     struct jz4740_rtc_s *s = (struct jz4740_rtc_s *) qemu_mallocz(sizeof(*s));
1568     s->base = JZ4740_PHYS_BASE(JZ4740_RTC_BASE);
1569     s->soc = soc;
1570     s->irq = irq;
1571
1572     s->hz_tm = qemu_new_timer(rt_clock, jz4740_rtc_hz, s);
1573
1574     jz4740_rtc_reset(s);
1575
1576     iomemtype =
1577         cpu_register_io_memory(0, jz4740_rtc_readfn, jz4740_rtc_writefn, s);
1578     cpu_register_physical_memory(s->base, 0x00001000, iomemtype);
1579     return s;
1580 }
1581
1582 struct jz4740_tcu_s
1583 {
1584     qemu_irq tcu_irq0;
1585     qemu_irq tcu_irq1;
1586     qemu_irq tcu_irq2;
1587
1588     target_phys_addr_t base;
1589     struct jz_state_s *soc;
1590
1591
1592     QEMUTimer *half_timer[8];
1593     QEMUTimer *full_timer[8];
1594     int64_t time[8];
1595
1596     uint32_t tsr;
1597     uint32_t ter;
1598     uint32_t tfr;
1599     uint32_t tmr;
1600
1601     uint32_t tdfr[8];
1602     uint32_t tdhr[8];
1603     uint32_t tcnt[8];
1604     uint32_t tcsr[8];
1605
1606     uint32_t prescale[8];
1607     uint32_t freq[8];
1608 };
1609
1610 static void jz4740_tcu_update_interrupt(struct jz4740_tcu_s *s)
1611 {
1612     //printf("s->tfr %x s->tmr %x \n",s->tfr,s->tmr);
1613     if (((s->tfr & 0x1) & (~(s->tmr & 0x1)))
1614         || ((s->tfr & 0x10000) & (~(s->tmr & 0x10000))))
1615     {
1616         qemu_set_irq(s->tcu_irq0, 1);
1617     }
1618     else
1619         qemu_set_irq(s->tcu_irq0, 0);
1620 #if 0
1621     if (((s->tfr & 0x2) & (~(s->tmr & 0x2)))
1622         || ((s->tfr & 0x20000) & (~(s->tmr & 0x20000))))
1623     {
1624         qemu_set_irq(s->tcu_irq1, 1);
1625     }
1626     else
1627         qemu_set_irq(s->tcu_irq1, 0);
1628
1629     if (((s->tfr & 0xfc) & (~(s->tmr & 0xfc)))
1630         || ((s->tfr & 0xfc0000) & (~(s->tmr & 0xfc0000))))
1631     {
1632         qemu_set_irq(s->tcu_irq2, 1);
1633     }
1634     else
1635         qemu_set_irq(s->tcu_irq2, 0);
1636 #endif
1637 }
1638
1639 #undef TCU_INDEX
1640 #define TCU_INDEX   0
1641 #include "mips_jz_glue.h"
1642 #define TCU_INDEX   1
1643 #include "mips_jz_glue.h"
1644 #define TCU_INDEX   2
1645 #include "mips_jz_glue.h"
1646 #define TCU_INDEX   3
1647 #include "mips_jz_glue.h"
1648 #define TCU_INDEX   4
1649 #include "mips_jz_glue.h"
1650 #define TCU_INDEX   5
1651 #include "mips_jz_glue.h"
1652 #define TCU_INDEX   6
1653 #include "mips_jz_glue.h"
1654 #define TCU_INDEX   7
1655 #include "mips_jz_glue.h"
1656 #undef TCU_INDEX
1657
1658 #define  jz4740_tcu_start(s) do {        \
1659         jz4740_tcu_start_half0(s);              \
1660         jz4740_tcu_start_full0(s);    \
1661         jz4740_tcu_start_half1(s); \
1662         jz4740_tcu_start_full1(s); \
1663         jz4740_tcu_start_half2(s); \
1664         jz4740_tcu_start_full2(s); \
1665         jz4740_tcu_start_half3(s); \
1666         jz4740_tcu_start_full3(s); \
1667         jz4740_tcu_start_half4(s); \
1668         jz4740_tcu_start_full4(s); \
1669         jz4740_tcu_start_half5(s); \
1670         jz4740_tcu_start_full5(s); \
1671         jz4740_tcu_start_half6(s); \
1672         jz4740_tcu_start_full6(s); \
1673         jz4740_tcu_start_half7(s); \
1674         jz4740_tcu_start_full7(s); \
1675 }while (0)
1676
1677 static void jz4740_tcu_if_reset(struct jz4740_tcu_s *s)
1678 {
1679     int i;
1680
1681     s->tsr = 0x0;
1682     s->ter = 0x0;
1683     s->tfr = 0x0;
1684     s->tmr = 0x0;
1685     for (i = 0; i < 8; i++)
1686     {
1687         s->tdfr[i] = 0xffff;
1688         s->tdhr[i] = 0x8000;
1689         s->tcnt[i] = 0x0;
1690         s->tcsr[i] = 0x0;
1691         s->half_timer[i] = NULL;
1692         s->full_timer[i] = NULL;
1693     }
1694 }
1695
1696 static void jz4740_tcu_if_write8(void *opaque, target_phys_addr_t addr,
1697                                  uint32_t value)
1698 {
1699     struct jz4740_tcu_s *s = (struct jz4740_tcu_s *) opaque;
1700
1701     debug_out(DEBUG_TCU, "jz4740_tcu_if_write8 addr %x value %x\n", addr,
1702               value);
1703
1704     switch (addr)
1705     {
1706     case 0x14:
1707         s->ter |= (value & 0xff);
1708         jz4740_tcu_start(s);
1709         break;
1710     case 0x18:
1711         s->ter &= ~(value & 0xff);
1712         jz4740_tcu_start(s);
1713         break;
1714     default:
1715         cpu_abort(s->soc->env,
1716                   "jz4740_tcu_if_write8 undefined addr " JZ_FMT_plx
1717                   " value %x \n", addr, value);
1718     }
1719
1720 }
1721
1722 static void jz4740_tcu_if_write32(void *opaque, target_phys_addr_t addr,
1723                                   uint32_t value)
1724 {
1725     struct jz4740_tcu_s *s = (struct jz4740_tcu_s *) opaque;
1726
1727     debug_out(DEBUG_TCU, "jz4740_tcu_if_write32 addr %x value %x\n", addr,
1728               value);
1729
1730     fprintf(fp, "jz4740_tcu_if_write32 addr %x value %x\n", addr, value);
1731     switch (addr)
1732     {
1733     case 0x2c:
1734         s->tsr |= (value & 0x100ff);
1735         jz4740_tcu_start(s);
1736         break;
1737     case 0x3c:
1738         s->tsr &= ~(value & 0x100ff);
1739         jz4740_tcu_start(s);
1740         break;
1741     case 0x24:
1742         s->tfr |= (value & 0xff00ff);
1743         break;
1744     case 0x28:
1745         s->tfr &= ~(value & 0xff00ff);
1746         break;
1747     case 0x34:
1748         s->tmr |= (value & 0xff00ff);
1749         jz4740_tcu_update_interrupt(s);
1750         break;
1751     case 0x38:
1752         s->tmr &= ~(value & 0xff00ff);
1753         jz4740_tcu_update_interrupt(s);
1754         break;
1755     default:
1756         cpu_abort(s->soc->env,
1757                   "jz4740_tcu_if_write32 undefined addr " JZ_FMT_plx
1758                   " value %x \n", addr, value);
1759
1760     }
1761 }
1762
1763 static uint32_t jz4740_tcu_if_read8(void *opaque, target_phys_addr_t addr)
1764 {
1765     struct jz4740_tcu_s *s = (struct jz4740_tcu_s *) opaque;
1766
1767     debug_out(DEBUG_TCU, "jz4740_tcu_if_read8 addr %x\n", addr);
1768
1769     switch (addr)
1770     {
1771     case 0x10:
1772         return s->ter;
1773     default:
1774         cpu_abort(s->soc->env,
1775                   "jz4740_tcu_if_read8 undefined addr " JZ_FMT_plx "\n", addr);
1776     }
1777     return (0);
1778 }
1779
1780 static uint32_t jz4740_tcu_if_read32(void *opaque, target_phys_addr_t addr)
1781 {
1782     struct jz4740_tcu_s *s = (struct jz4740_tcu_s *) opaque;
1783
1784     debug_out(DEBUG_TCU, "jz4740_tcu_if_read32 addr %x\n", addr);
1785
1786     switch (addr)
1787     {
1788     case 0x1c:
1789         return s->tsr;
1790     case 0x20:
1791         return s->tfr;
1792     case 0x30:
1793         return s->tmr;
1794     default:
1795         cpu_abort(s->soc->env,
1796                   "jz4740_tcu_if_read32 undefined addr " JZ_FMT_plx "\n", addr);
1797
1798     }
1799     return (0);
1800
1801 }
1802
1803 static CPUReadMemoryFunc *jz4740_tcu_if_readfn[] = {
1804     jz4740_tcu_if_read8,
1805     jz4740_badwidth_read32,
1806     jz4740_tcu_if_read32,
1807 };
1808
1809 static CPUWriteMemoryFunc *jz4740_tcu_if_writefn[] = {
1810     jz4740_tcu_if_write8,
1811     jz4740_badwidth_write32,
1812     jz4740_tcu_if_write32,
1813 };
1814
1815 static struct jz4740_tcu_s *jz4740_tcu_if_init(struct jz_state_s *soc,
1816                                                qemu_irq tcu_irq0,
1817                                                qemu_irq tcu_irq1,
1818                                                qemu_irq tcu_irq2)
1819 {
1820     int iomemtype;
1821     //int i;
1822
1823     struct jz4740_tcu_s *s = (struct jz4740_tcu_s *) qemu_mallocz(sizeof(*s));
1824     s->base = JZ4740_PHYS_BASE(JZ4740_TCU_BASE);
1825     s->soc = soc;
1826     s->tcu_irq0 = tcu_irq0;
1827     s->tcu_irq1 = tcu_irq1;
1828     s->tcu_irq2 = tcu_irq2;
1829
1830     jz4740_tcu_if_reset(s);
1831
1832     iomemtype =
1833         cpu_register_io_memory(0, jz4740_tcu_if_readfn, jz4740_tcu_if_writefn,
1834                                s);
1835     cpu_register_physical_memory(s->base, 0x00000040, iomemtype);
1836     return s;
1837
1838 }
1839
1840 static void jz4740_tcu_init(struct jz_state_s *soc,
1841                             struct jz4740_tcu_s *s, int timer_index)
1842 {
1843     switch (timer_index)
1844     {
1845     case 0x0:
1846         jz4740_tcu_init0(soc, s);
1847         break;
1848     case 0x1:
1849         jz4740_tcu_init1(soc, s);
1850         break;
1851     case 0x2:
1852         jz4740_tcu_init2(soc, s);
1853         break;
1854     case 0x3:
1855         jz4740_tcu_init3(soc, s);
1856         break;
1857     case 0x4:
1858         jz4740_tcu_init4(soc, s);
1859         break;
1860     case 0x5:
1861         jz4740_tcu_init5(soc, s);
1862         break;
1863     case 0x6:
1864         jz4740_tcu_init6(soc, s);
1865         break;
1866     case 0x7:
1867         jz4740_tcu_init7(soc, s);
1868         break;
1869     default:
1870         cpu_abort(s->soc->env,
1871                   "jz4740_tcu_init undefined timer %x \n", timer_index);
1872     }
1873 }
1874
1875 typedef void (*jz4740_lcd_fn_t) (uint8_t * d, const uint8_t * s, int width,
1876                                  const uint16_t * pal);
1877 struct jz_fb_descriptor
1878 {
1879     uint32_t fdadr;             /* Frame descriptor address register */
1880     uint32_t fsadr;             /* Frame source address register */
1881     uint32_t fidr;              /* Frame ID register */
1882     uint32_t ldcmd;             /* Command register */
1883 };
1884
1885 struct jz4740_lcdc_s
1886 {
1887     qemu_irq irq;
1888
1889     target_phys_addr_t base;
1890     struct jz_state_s *soc;
1891
1892     DisplayState *state;
1893     QEMUConsole *console;
1894     jz4740_lcd_fn_t *line_fn_tab;
1895     jz4740_lcd_fn_t line_fn;
1896
1897
1898     uint32_t lcdcfg;
1899     uint32_t lcdvsync;
1900     uint32_t lcdhsync;
1901     uint32_t lcdvat;
1902     uint32_t lcddah;
1903     uint32_t lcddav;
1904     uint32_t lcdps;
1905     uint32_t lcdcls;
1906     uint32_t lcdspl;
1907     uint32_t lcdrev;
1908     uint32_t lcdctrl;
1909     uint32_t lcdstate;
1910     uint32_t lcdiid;
1911     uint32_t lcdda0;
1912     uint32_t lcdsa0;
1913     uint32_t lcdfid0;
1914     uint32_t lcdcmd0;
1915     uint32_t lcdda1;
1916     uint32_t lcdsa1;
1917     uint32_t lcdfid1;
1918     uint32_t lcdcmd1;
1919
1920     uint32_t ena;
1921     uint32_t dis;
1922     uint32_t width;
1923     uint32_t height;
1924     uint32_t bpp;               /*bit per second */
1925     uint16_t palette[256];
1926     uint32_t invalidate;
1927
1928 };
1929
1930 /*bit per pixel*/
1931 static const int jz4740_lcd_bpp[0x6] = {
1932     1, 2, 4, 8, 16, 32          /*4740 uses 32 bit for 24bpp */
1933 };
1934
1935 static void jz4740_lcdc_reset(struct jz4740_lcdc_s *s)
1936 {
1937
1938 }
1939
1940 static uint32_t jz4740_lcdc_read(void *opaque, target_phys_addr_t addr)
1941 {
1942     struct jz4740_lcdc_s *s = (struct jz4740_lcdc_s *) opaque;
1943
1944     debug_out(DEBUG_LCDC, "jz4740_lcdc_read addr %x \n", addr);
1945     switch (addr)
1946     {
1947     case 0x0:
1948         return s->lcdcfg;
1949     case 0x4:
1950         return s->lcdvsync;
1951     case 0x8:
1952         return s->lcdhsync;
1953     case 0xc:
1954         return s->lcdvat;
1955     case 0x10:
1956         return s->lcddah;
1957     case 0x14:
1958         return s->lcddav;
1959     case 0x18:
1960         return s->lcdps;
1961     case 0x1c:
1962         return s->lcdcls;
1963     case 0x20:
1964         return s->lcdspl;
1965     case 0x24:
1966         return s->lcdrev;
1967     case 0x30:
1968         return s->lcdctrl;
1969     case 0x34:
1970         return s->lcdstate;
1971     case 0x38:
1972         return s->lcdiid;
1973     case 0x40:
1974         return s->lcdda0;
1975     case 0x44:
1976         return s->lcdsa0;
1977     case 0x48:
1978         return s->lcdfid0;
1979     case 0x4c:
1980         return s->lcdcmd0;
1981     case 0x50:
1982         return s->lcdda1;
1983     case 0x54:
1984         return s->lcdsa1;
1985     case 0x58:
1986         return s->lcdfid1;
1987     case 0x5c:
1988         return s->lcdcmd1;
1989     default:
1990         cpu_abort(s->soc->env,
1991                   "jz4740_lcdc_read undefined addr " JZ_FMT_plx " \n", addr);
1992
1993     }
1994
1995 }
1996
1997 static void jz4740_lcdc_write(void *opaque, target_phys_addr_t addr,
1998                               uint32_t value)
1999 {
2000     struct jz4740_lcdc_s *s = (struct jz4740_lcdc_s *) opaque;
2001
2002     debug_out(DEBUG_LCDC, "jz4740_lcdc_write addr %x value %x\n", addr, value);
2003
2004     switch (addr)
2005     {
2006     case 0x44:
2007     case 0x48:
2008     case 0x4c:
2009         JZ4740_RO_REG(addr);
2010         break;
2011     case 0x0:
2012         s->lcdcfg = value & 0x80ffffbf;
2013         break;
2014     case 0x4:
2015         s->lcdvsync = value & 0x7ff07ff;
2016         break;
2017     case 0x8:
2018         s->lcdhsync = value & 0x7ff07ff;
2019         break;
2020     case 0xc:
2021         s->lcdvat = value & 0x7ff07ff;
2022         break;
2023     case 0x10:
2024         s->lcddah = value & 0x7ff07ff;
2025         s->width = (value & 0x7ff) - ((value >> 16) & 0x7ff);
2026         break;
2027     case 0x14:
2028         s->height = (value & 0x7ff) - ((value >> 16) & 0x7ff);
2029         s->lcddav = value & 0x7ff07ff;
2030         break;
2031     case 0x18:
2032         s->lcdps = value & 0x7ff07ff;
2033         break;
2034     case 0x1c:
2035         s->lcdcls = value & 0x7ff07ff;
2036         break;
2037     case 0x20:
2038         s->lcdspl = value & 0x7ff07ff;
2039         break;
2040     case 0x24:
2041         s->lcdrev = value & 0x7ff0000;
2042         break;
2043     case 0x30:
2044         s->lcdctrl = value & 0x3fff3fff;
2045         s->ena = (value & 0x8) >> 3;
2046         s->dis = (value & 0x10) >> 4;
2047         s->bpp = jz4740_lcd_bpp[value & 0x7];
2048         if ((s->bpp == 1))
2049         {
2050             fprintf(stderr, "bpp =1 is not supported\n");
2051             exit(-1);
2052         }
2053         s->line_fn = s->line_fn_tab[value & 0x7];
2054         break;
2055     case 0x34:
2056         s->lcdstate = value & 0xbf;
2057         break;
2058     case 0x38:
2059         s->lcdiid = value;
2060         break;
2061     case 0x40:
2062         s->lcdda0 = value;
2063         break;
2064     case 0x50:
2065         s->lcdda1 = value;
2066         break;
2067     default:
2068         cpu_abort(s->soc->env,
2069                   "jz4740_lcdc_write undefined addr " JZ_FMT_plx " value %x \n",
2070                   addr, value);
2071     }
2072
2073 }
2074
2075 static CPUReadMemoryFunc *jz4740_lcdc_readfn[] = {
2076     jz4740_badwidth_read32,
2077     jz4740_badwidth_read32,
2078     jz4740_lcdc_read,
2079 };
2080
2081 static CPUWriteMemoryFunc *jz4740_lcdc_writefn[] = {
2082     jz4740_badwidth_write32,
2083     jz4740_badwidth_write32,
2084     jz4740_lcdc_write,
2085 };
2086
2087 #include "pixel_ops.h"
2088 #define JZ4740_LCD_PANEL
2089 #define DEPTH 8
2090 #include "mips_jz_glue.h"
2091 #define DEPTH 15
2092 #include "mips_jz_glue.h"
2093 #define DEPTH 16
2094 #include "mips_jz_glue.h"
2095 #define DEPTH 24
2096 #include "mips_jz_glue.h"
2097 #define DEPTH 32
2098 #include "mips_jz_glue.h"
2099 #undef JZ4740_LCD_PANEL
2100
2101 static void *jz4740_lcd_get_buffer(struct jz4740_lcdc_s *s,
2102                                    target_phys_addr_t addr)
2103 {
2104     uint32_t pd;
2105
2106     pd = cpu_get_physical_page_desc(addr);
2107     if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM)
2108         /* TODO */
2109         cpu_abort(cpu_single_env, "%s: framebuffer outside RAM!\n",
2110                   __FUNCTION__);
2111     else
2112         return phys_ram_base +
2113             (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
2114 }
2115
2116 static void jz4740_lcd_update_display(void *opaque)
2117 {
2118     struct jz4740_lcdc_s *s = (struct jz4740_lcdc_s *) opaque;
2119
2120     uint8_t *src, *dest;
2121     struct jz_fb_descriptor *fb_des;
2122
2123     int step, linesize;
2124     int y;
2125
2126
2127     if (!s->ena)
2128         return;
2129     if (s->dis)
2130         return;
2131
2132     if (!s->lcdda0)
2133         return;
2134
2135     fb_des = (struct jz_fb_descriptor *) jz4740_lcd_get_buffer(s, s->lcdda0);
2136     s->lcdda0 = fb_des->fdadr;
2137     s->lcdsa0 = fb_des->fsadr;
2138     s->lcdfid0 = fb_des->fidr;
2139     s->lcdcmd0 = fb_des->ldcmd;
2140
2141     src = (uint8_t *) jz4740_lcd_get_buffer(s, fb_des->fsadr);
2142     if (s->lcdcmd0 & (0x1 << 28))
2143     {
2144         /*palette */
2145         memcpy(s->palette, src, sizeof(s->palette));
2146         return;
2147     }
2148
2149     /*frame buffer */
2150
2151     if (s->width != ds_get_width(s->state) ||
2152         s->height != ds_get_height(s->state))
2153     {
2154         qemu_console_resize(s->console, s->width, s->height);
2155         s->invalidate = 1;
2156     }
2157
2158     step = (s->width * s->bpp) >> 3;
2159     dest = ds_get_data(s->state);
2160     linesize = ds_get_linesize(s->state);
2161
2162     //printf("s->width %d s->height  %d s->bpp %d linesize %d \n",s->width,s->height ,s->bpp,linesize);
2163
2164     for (y = 0; y < s->height; y++)
2165     {
2166         s->line_fn(dest, src, s->width, s->palette);
2167         //memcpy(dest,src,step);
2168         src += step;
2169         dest += linesize;
2170     }
2171
2172
2173     dpy_update(s->state, 0, 0, s->width, s->height);
2174     s->lcdstate |= 0x20;
2175     if ((s->lcdcmd0 & 0x40000000) && (!(s->lcdctrl & 0x2000)))
2176         qemu_set_irq(s->irq, 1);
2177 }
2178
2179 static inline void jz4740_lcd_invalidate_display(void *opaque)
2180 {
2181     struct jz4740_lcdc_s *s = (struct jz4740_lcdc_s *) opaque;
2182     s->invalidate = 1;
2183 }
2184
2185 static struct jz4740_lcdc_s *jz4740_lcdc_init(struct jz_state_s *soc,
2186                                               qemu_irq irq, DisplayState * ds)
2187 {
2188     int iomemtype;
2189
2190     struct jz4740_lcdc_s *s = (struct jz4740_lcdc_s *) qemu_mallocz(sizeof(*s));
2191     s->base = JZ4740_PHYS_BASE(JZ4740_LCD_BASE);
2192     s->soc = soc;
2193     s->irq = irq;
2194     s->state = ds;
2195
2196
2197     jz4740_lcdc_reset(s);
2198
2199     iomemtype =
2200         cpu_register_io_memory(0, jz4740_lcdc_readfn, jz4740_lcdc_writefn, s);
2201     cpu_register_physical_memory(s->base, 0x10000, iomemtype);
2202
2203     s->console = graphic_console_init(s->state, jz4740_lcd_update_display,
2204                                       jz4740_lcd_invalidate_display,
2205                                       NULL, NULL, s);
2206     switch (ds_get_bits_per_pixel(s->state))
2207     {
2208     case 0x0:
2209         s->line_fn_tab = qemu_mallocz(sizeof(jz4740_lcd_fn_t) * 6);
2210         break;
2211     case 8:
2212         s->line_fn_tab = jz4740_lcd_draw_fn_8;
2213         break;
2214     case 15:
2215         s->line_fn_tab = jz4740_lcd_draw_fn_15;
2216         break;
2217     case 16:
2218         s->line_fn_tab = jz4740_lcd_draw_fn_16;
2219         break;
2220     case 24:
2221         s->line_fn_tab = jz4740_lcd_draw_fn_24;
2222         break;
2223     case 32:
2224         s->line_fn_tab = jz4740_lcd_draw_fn_32;
2225         break;
2226     default:
2227         fprintf(stderr, "%s: Bad color depth\n", __FUNCTION__);
2228         exit(1);
2229     }
2230
2231     return s;
2232
2233 }
2234
2235 #define JZ4740_DMA_NUM         6
2236 struct jz4740_dma_s
2237 {
2238     qemu_irq irq;
2239
2240     target_phys_addr_t base;
2241     struct jz_state_s *soc;
2242
2243     uint32_t dmac;
2244     uint32_t dirqp;
2245     uint32_t ddr;
2246     uint32_t ddrs;
2247
2248     uint32_t dsa[JZ4740_DMA_NUM];
2249     uint32_t dta[JZ4740_DMA_NUM];
2250     uint32_t dtc[JZ4740_DMA_NUM];
2251     uint32_t drs[JZ4740_DMA_NUM];
2252     uint32_t dcs[JZ4740_DMA_NUM];
2253     uint32_t dcm[JZ4740_DMA_NUM];
2254     uint32_t dda[JZ4740_DMA_NUM];
2255
2256 };
2257
2258 struct jz4740_desc_s
2259 {
2260     uint32_t dcmd;              /* DCMD value for the current transfer */
2261     uint32_t dsadr;             /* DSAR value for the current transfer */
2262     uint32_t dtadr;             /* DTAR value for the current transfer */
2263     uint32_t ddadr;             /* Points to the next descriptor + transfer count */
2264 };
2265
2266 static inline void jz4740_dma_transfer(struct jz4740_dma_s *s,
2267                                        target_phys_addr_t src,
2268                                        target_phys_addr_t dest, uint32_t len)
2269 {
2270     uint32_t pd_src, pd_dest;
2271     uint8_t *sr, *de;
2272
2273     pd_src = cpu_get_physical_page_desc(src);
2274     if ((pd_src & ~TARGET_PAGE_MASK) != IO_MEM_RAM)
2275         /* TODO */
2276         cpu_abort(cpu_single_env, "%s: DMA source address %x outside RAM!\n",
2277                   __FUNCTION__, src);
2278     else
2279         sr = phys_ram_base +
2280             (pd_src & TARGET_PAGE_MASK) + (src & ~TARGET_PAGE_MASK);
2281
2282     pd_dest = cpu_get_physical_page_desc(dest);
2283     if ((pd_dest & ~TARGET_PAGE_MASK) != IO_MEM_RAM)
2284         /* TODO */
2285         cpu_abort(cpu_single_env,
2286                   "%s: DMA destination address %x outside RAM!\n",
2287                   __FUNCTION__, dest);
2288     else
2289         de = phys_ram_base +
2290             (pd_dest & TARGET_PAGE_MASK) + (dest & ~TARGET_PAGE_MASK);
2291
2292     memcpy(de, sr, len);
2293 }
2294
2295 static inline uint32_t jz4740_dma_unit_size(struct jz4740_dma_s *s,
2296                                             uint32_t cmd)
2297 {
2298     switch ((cmd & 0x700) >> 8)
2299     {
2300     case 0x0:
2301         return 4;
2302     case 0x1:
2303         return 1;
2304     case 0x2:
2305         return 2;
2306     case 0x3:
2307         return 16;
2308     case 0x4:
2309         return 32;
2310     }
2311     return (0);
2312 }
2313
2314
2315 /*No-descriptor transfer*/
2316 static inline void jz4740_dma_ndrun(struct jz4740_dma_s *s, int channel)
2317 {
2318     uint32_t len;
2319
2320     len = jz4740_dma_unit_size(s, s->dcs[channel]) * s->dtc[channel];
2321
2322     jz4740_dma_transfer(s, s->dsa[channel], s->dta[channel], len);
2323
2324     /*finish dma transfer */
2325     s->dtc[channel] = 0;
2326     /*set DIR QP */
2327     s->dirqp |= 1 << channel;
2328
2329     /*some cleanup work */
2330     /*clean AR TT GLOBAL AR */
2331     s->dcs[channel] &= 0xffffffe7;
2332     s->dmac &= 0xfffffffb;
2333
2334     if (s->dcm[channel] & 0x2)
2335         qemu_set_irq(s->irq, 1);
2336 }
2337
2338         /*descriptor transfer */
2339 static inline void jz4740_dma_drun(struct jz4740_dma_s *s, int channel)
2340 {
2341     struct jz4740_desc_s *desc;
2342     target_phys_addr_t desc_phy;
2343     uint32_t pd;
2344
2345     desc_phy = s->dda[channel];
2346     if (desc_phy & 0xf)
2347         cpu_abort(s->soc->env,
2348                   "jz4740_dma_drun descriptor address " JZ_FMT_plx
2349                   " must be 4 bytes aligned \n", desc_phy);
2350
2351     pd = cpu_get_physical_page_desc(desc_phy);
2352     if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM)
2353         cpu_abort(cpu_single_env,
2354                   "%s: DMA descriptor address " JZ_FMT_plx " outside RAM!\n",
2355                   __FUNCTION__, desc_phy);
2356     else
2357         desc = (struct jz4740_desc_s *) (phys_ram_base +
2358                                          (pd & TARGET_PAGE_MASK) +
2359                                          (desc_phy & ~TARGET_PAGE_MASK));
2360
2361     if (!desc)
2362         cpu_abort(cpu_single_env,
2363                   "%s: DMA descriptor " JZ_FMT_plx " is NULL!\n", __FUNCTION__,
2364                   (uint32_t) desc);
2365
2366     while (1)
2367     {
2368         if ((desc->dcmd & 0x8) && (!(desc->dcmd & 0x10)))
2369         {
2370             /*Stop DMA and set DCSN.INV=1 */
2371             s->dcs[channel] |= 1 << 6;
2372             return;
2373         }
2374         jz4740_dma_transfer(s, desc->dtadr, desc->dsadr,
2375                             (desc->ddadr & 0xffffff) *
2376                             jz4740_dma_unit_size(s, desc->dcmd));
2377
2378         if ((desc->dcmd) & (1 << 3))
2379             /*clear v */
2380             desc->dcmd &= ~(1 << 4);
2381         if (desc->dcmd & 0x1)
2382             /*set DCSN.CT=1 */
2383             s->dcs[channel] |= 0x2;
2384         else
2385             /*set DCSN.TT=1 */
2386             s->dcs[channel] |= 0x8;
2387
2388         if (desc->dcmd & 0x2)
2389             qemu_set_irq(s->irq, 1);
2390
2391         if ((desc->dcmd) & 0x1)
2392         {
2393             /*fetch next descriptor */
2394             desc_phy = s->dda[channel] & 0xfffff000;
2395             desc_phy += (desc->dtadr & 0xff000000) >> 24;
2396             pd = cpu_get_physical_page_desc(desc_phy);
2397             if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM)
2398                 cpu_abort(cpu_single_env,
2399                           "%s: DMA descriptor address %x outside RAM!\n",
2400                           __FUNCTION__, desc_phy);
2401             else
2402                 desc = (struct jz4740_desc_s *) (phys_ram_base +
2403                                                  (pd & TARGET_PAGE_MASK)
2404                                                  +
2405                                                  (desc_phy &
2406                                                   ~TARGET_PAGE_MASK));
2407             if (!desc)
2408                 cpu_abort(cpu_single_env,
2409                           "%s: DMA descriptor %x is NULL!\n",
2410                           __FUNCTION__, (uint32_t) desc);
2411         }
2412         else
2413             break;
2414     }
2415 }
2416
2417 static void jz4740_dma_en_channel(struct jz4740_dma_s *s, int channel)
2418 {
2419     if (s->dmac & 0x1)
2420     {
2421         if (s->dcs[channel] & (1 << 31))
2422         {
2423             /*NON DESCRIPTOR */
2424             jz4740_dma_ndrun(s, channel);
2425         }
2426     }
2427 }
2428
2429 static inline void jz4740_dma_en_global(struct jz4740_dma_s *s)
2430 {
2431     int channel;
2432     for (channel = 0; channel < JZ4740_DMA_NUM; channel++)
2433     {
2434         jz4740_dma_en_channel(s, channel);
2435     }
2436 }
2437
2438 static inline void jz4740_dma_en_dbn(struct jz4740_dma_s *s, int channel)
2439 {
2440     if ((s->dmac & 0x1) && (s->dcs[channel] & (1 << 31)))
2441     {
2442         jz4740_dma_drun(s, channel);
2443     }
2444 }
2445
2446 static void jz4740_dma_reset(struct jz4740_dma_s *s)
2447 {
2448
2449 }
2450
2451 static uint32_t jz4740_dma_read(void *opaque, target_phys_addr_t addr)
2452 {
2453     struct jz4740_dma_s *s = (struct jz4740_dma_s *) opaque;
2454     int channel;
2455
2456     debug_out(DEBUG_DMA, "jz4740_dma_read addr %x \n", addr);
2457     switch (addr)
2458     {
2459     case 0x300:
2460         return s->dmac;
2461     case 0x304:
2462         return s->dirqp;
2463     case 0x308:
2464         return s->ddr;
2465     case 0x0:
2466     case 0x20:
2467     case 0x40:
2468     case 0x60:
2469     case 0x80:
2470     case 0xa0:
2471         channel = (addr - 0x0) / 0x20;
2472         return s->dsa[channel];
2473     case 0x4:
2474     case 0x24:
2475     case 0x44:
2476     case 0x64:
2477     case 0x84:
2478     case 0xa4:
2479         channel = (addr - 0x4) / 0x20;
2480         return s->dta[channel];
2481     case 0x8:
2482     case 0x28:
2483     case 0x48:
2484     case 0x68:
2485     case 0x88:
2486     case 0xa8:
2487         channel = (addr - 0x8) / 0x20;
2488         return s->dtc[channel];
2489     case 0xc:
2490     case 0x2c:
2491     case 0x4c:
2492     case 0x6c:
2493     case 0x8c:
2494     case 0xac:
2495         channel = (addr - 0xc) / 0x20;
2496         return s->drs[channel];
2497     case 0x10:
2498     case 0x30:
2499     case 0x50:
2500     case 0x70:
2501     case 0x90:
2502     case 0xb0:
2503         channel = (addr - 0x10) / 0x20;
2504         return s->dcs[channel];
2505     case 0x14:
2506     case 0x34:
2507     case 0x54:
2508     case 0x74:
2509     case 0x94:
2510     case 0xb4:
2511         channel = (addr - 0x14) / 0x20;
2512         return s->dcm[channel];
2513     case 0x18:
2514     case 0x38:
2515     case 0x58:
2516     case 0x78:
2517     case 0x98:
2518     case 0xb8:
2519         channel = (addr - 0x18) / 0x20;
2520         return s->dda[channel];
2521     default:
2522         cpu_abort(s->soc->env,
2523                   "jz4740_dma_read undefined addr " JZ_FMT_plx "  \n", addr);
2524     }
2525     return (0);
2526 }
2527
2528 static void jz4740_dma_write(void *opaque, target_phys_addr_t addr,
2529                              uint32_t value)
2530 {
2531     struct jz4740_dma_s *s = (struct jz4740_dma_s *) opaque;
2532     int channel;
2533
2534     debug_out(DEBUG_DMA, "jz4740_dma_write addr %x value %x \n", addr, value);
2535     switch (addr)
2536     {
2537     case 0x304:
2538         JZ4740_RO_REG(addr);
2539         break;
2540     case 0x300:
2541         s->dmac = value & 0x30d;
2542         if (s->dmac & 0x1)
2543             jz4740_dma_en_global(s);
2544         break;
2545     case 0x308:
2546     case 0x30c:
2547         s->ddr = value & 0xff;
2548         for (channel = 0; channel < JZ4740_DMA_NUM; channel++)
2549         {
2550             if (s->ddr & (1 << channel))
2551             {
2552                 jz4740_dma_en_dbn(s, channel);
2553                 break;
2554             }
2555         }
2556         break;
2557     case 0x0:
2558     case 0x20:
2559     case 0x40:
2560     case 0x60:
2561     case 0x80:
2562     case 0xa0:
2563         channel = (addr - 0x0) / 0x20;
2564         s->dsa[channel] = value;
2565         break;
2566     case 0x4:
2567     case 0x24:
2568     case 0x44:
2569     case 0x64:
2570     case 0x84:
2571     case 0xa4:
2572         channel = (addr - 0x4) / 0x20;
2573         s->dta[channel] = value;
2574         break;
2575     case 0x8:
2576     case 0x28:
2577     case 0x48:
2578     case 0x68:
2579     case 0x88:
2580     case 0xa8:
2581         channel = (addr - 0x8) / 0x20;
2582         s->dtc[channel] = value;
2583         break;
2584     case 0xc:
2585     case 0x2c:
2586     case 0x4c:
2587     case 0x6c:
2588     case 0x8c:
2589     case 0xac:
2590         channel = (addr - 0xc) / 0x20;
2591         s->drs[channel] = value & 0x10;
2592         if (s->drs[channel] != 0x8)
2593         {
2594             fprintf(stderr, "Only auto request is supproted \n");
2595         }
2596         break;
2597     case 0x10:
2598     case 0x30:
2599     case 0x50:
2600     case 0x70:
2601     case 0x90:
2602     case 0xb0:
2603         channel = (addr - 0x10) / 0x20;
2604         s->dcs[channel] = value & 0x80ff005f;
2605         if (s->dcs[channel] & 0x1)
2606             jz4740_dma_en_channel(s, channel);
2607         break;
2608     case 0x14:
2609     case 0x34:
2610     case 0x54:
2611     case 0x74:
2612     case 0x94:
2613     case 0xb4:
2614         channel = (addr - 0x14) / 0x20;
2615         s->dcm[channel] = value & 0xcff79f;
2616         break;
2617     case 0x18:
2618     case 0x38:
2619     case 0x58:
2620     case 0x78:
2621     case 0x98:
2622     case 0xb8:
2623         channel = (addr - 0x18) / 0x20;
2624         s->dda[channel] = 0xfffffff0;
2625         break;
2626     default:
2627         cpu_abort(s->soc->env,
2628                   "jz4740_dma_read undefined addr " JZ_FMT_plx "  \n", addr);
2629     }
2630
2631 }
2632
2633 static CPUReadMemoryFunc *jz4740_dma_readfn[] = {
2634     jz4740_badwidth_read32,
2635     jz4740_badwidth_read32,
2636     jz4740_dma_read,
2637 };
2638
2639 static CPUWriteMemoryFunc *jz4740_dma_writefn[] = {
2640     jz4740_badwidth_write32,
2641     jz4740_badwidth_write32,
2642     jz4740_dma_write,
2643 };
2644
2645
2646 static struct jz4740_dma_s *jz4740_dma_init(struct jz_state_s *soc,
2647                                             qemu_irq irq)
2648 {
2649     int iomemtype;
2650     struct jz4740_dma_s *s = (struct jz4740_dma_s *) qemu_mallocz(sizeof(*s));
2651     s->base = JZ4740_PHYS_BASE(JZ4740_DMAC_BASE);
2652     s->soc = soc;
2653     s->irq = irq;
2654
2655     jz4740_dma_reset(s);
2656
2657     iomemtype =
2658         cpu_register_io_memory(0, jz4740_dma_readfn, jz4740_dma_writefn, s);
2659     cpu_register_physical_memory(s->base, 0x00010000, iomemtype);
2660     return s;
2661
2662 }
2663
2664 static void jz4740_cpu_reset(void *opaque)
2665 {
2666     fprintf(stderr, "%s: UNIMPLEMENTED!", __FUNCTION__);
2667 }
2668
2669 struct jz_state_s *jz4740_init(unsigned long sdram_size,
2670                                uint32_t osc_extal_freq, DisplayState * ds)
2671 {
2672     struct jz_state_s *s = (struct jz_state_s *)
2673         qemu_mallocz(sizeof(struct jz_state_s));
2674     ram_addr_t sram_base, sdram_base;
2675     qemu_irq *intc;
2676
2677     s->mpu_model = jz4740;
2678     s->env = cpu_init("jz4740");
2679
2680     if (!s->env)
2681     {
2682         fprintf(stderr, "Unable to find CPU definition\n");
2683         exit(1);
2684     }
2685
2686     debug_init();
2687     qemu_register_reset(jz4740_cpu_reset, s->env);
2688
2689     s->sdram_size = sdram_size;
2690     s->sram_size = JZ4740_SRAM_SIZE;
2691
2692     /* Clocks */
2693     jz_clk_init(s, osc_extal_freq);
2694
2695     /*map sram to 0x80000000 and sdram to 0x80004000 */
2696     sram_base = qemu_ram_alloc(s->sram_size);
2697     cpu_register_physical_memory(0x0, s->sram_size, (sram_base | IO_MEM_RAM));
2698     sdram_base = qemu_ram_alloc(s->sdram_size);
2699     cpu_register_physical_memory(JZ4740_SRAM_SIZE, s->sdram_size,
2700                                  (sdram_base | IO_MEM_RAM));
2701
2702     /* Init internal devices */
2703     cpu_mips_irq_init_cpu(s->env);
2704     cpu_mips_clock_init(s->env);
2705
2706
2707     /* Clocks */
2708     jz_clk_init(s, osc_extal_freq);
2709
2710     intc = jz4740_intc_init(s, s->env->irq[2]);
2711     s->cpm = jz4740_cpm_init(s);
2712     s->emc = jz4740_emc_init(s, intc[2]);
2713     s->gpio = jz4740_gpio_init(s, intc[25]);
2714     s->rtc = jz4740_rtc_init(s, intc[15]);
2715     s->tcu = jz4740_tcu_if_init(s, intc[23], intc[22], intc[21]);
2716     jz4740_tcu_init(s, s->tcu, 0);
2717     s->lcdc = jz4740_lcdc_init(s, intc[30], ds);
2718     s->dma = jz4740_dma_init(s, intc[20]);
2719
2720     if (serial_hds[0])
2721         serial_mm_init(0x10030000, 2, intc[9], 57600, serial_hds[0], 1);
2722
2723     return s;
2724 }